830GM still woes

Hi Daniel, dear list,

just tried the latest nightly build of 3.15.0+, and I'm sorry to say that the watermark configuration of the 830GM is still off.

This is what I get from the kernel: (not to be taken too serious, but
humor is the only thing that keeps me from getting seriously anoyed after so much time of the same bug...)

May 16 15:15:42 pike kernel: [    6.705950] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 1: Noop due to uninitialized mode.
May 16 15:15:42 pike kernel: [    6.710930] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:42 pike kernel: [    6.710936] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:42 pike kernel: [    6.710942] [drm:i9xx_update_wm] FIFO watermarks - A: 45, B: 46
May 16 15:15:42 pike kernel: [    6.710947] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 45, B: 46, C: 2, SR 1
May 16 15:15:42 pike kernel: [    6.710953] [drm:intel_sanitize_crtc] [CRTC:7] hw state adjusted, was enabled, now disabled

Watermarks of 45 and 46 upon initialization. Weird, but it gets weirder...

May 16 15:15:42 pike kernel: [    6.842042] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:42 pike kernel: [    6.842046] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:42 pike kernel: [    6.842050] [drm:i9xx_update_wm] FIFO watermarks - A: 45, B: 46
May 16 15:15:42 pike kernel: [    6.842053] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 45, B: 46, C: 2, SR 1
May 16 15:15:42 pike kernel: [    6.842061] [drm:drm_calc_timestamping_constants] crtc 5: hwmode: htotal 1688, vtotal 1066, vdisplay 1024
May 16 15:15:42 pike kernel: [    6.842065] [drm:drm_calc_timestamping_constants] crtc 5: clock 108000 kHz framedur 16661185 linedur 15629, pixeldur 9
May 16 15:15:42 pike kernel: [    6.847625] [drm:i9xx_update_primary_plane] Writing base 00060000 00000000 0 0 5120
May 16 15:15:42 pike kernel: [    6.847633] [drm:intel_crtc_mode_set] [ENCODER:9:DAC-9] set [MODE:0:1280x1024]
May 16 15:15:42 pike kernel: [    6.848287] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:42 pike kernel: [    6.848290] [drm:intel_calculate_wm] FIFO entries required for mode: 68
May 16 15:15:42 pike kernel: [    6.848292] [drm:intel_calculate_wm] FIFO watermark level: -23
May 16 15:15:42 pike kernel: [    6.848295] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:42 pike kernel: [    6.848297] [drm:i9xx_update_wm] FIFO watermarks - A: 1, B: 46
May 16 15:15:42 pike kernel: [    6.848300] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 1, B: 46, C: 2, SR 1
May 16 15:15:42 pike kernel: [    6.856893] [drm:intel_connector_check_state] [CONNECTOR:8:VGA-1]
May 16 15:15:42 pike kernel: [    6.856897] [drm:check_encoder_state] [ENCODER:9:DAC-9]
May 16 15:15:42 pike kernel: [    6.856901] [drm:check_encoder_state] [ENCODER:10:None-10]

Ok, so that computes a watermark of -23 for pipe A (WTF?) then rounded up to +1 (but still too small, needs to be +8), B remains at +46 even though an external monitor is connected.

May 16 15:15:42 pike kernel: [    6.857023] [drm:intel_dump_pipe_config] adjusted mode:
May 16 15:15:42 pike kernel: [    6.857029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0x5
May 16 15:15:42 pike kernel: [    6.857034] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x8 flags: 0x5
May 16 15:15:42 pike kernel: [    6.857036] [drm:intel_dump_pipe_config] port clock: 65000
May 16 15:15:42 pike kernel: [    6.857038] [drm:intel_dump_pipe_config] pipe src size: 1024x768
May 16 15:15:42 pike kernel: [    6.857040] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
May 16 15:15:42 pike kernel: [    6.857043] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
May 16 15:15:42 pike kernel: [    6.857045] [drm:intel_dump_pipe_config] ips: 0
May 16 15:15:42 pike kernel: [    6.857047] [drm:intel_dump_pipe_config] double wide: 0
May 16 15:15:42 pike kernel: [    6.857052] [drm:drm_calc_timestamping_constants] crtc 7: hwmode: htotal 1344, vtotal 806, vdisplay 768
May 16 15:15:42 pike kernel: [    6.857055] [drm:drm_calc_timestamping_constants] crtc 7: clock 65000 kHz framedur 16665600 linedur 20676, pixeldur 15
May 16 15:15:42 pike kernel: [    6.868773] [drm:i9xx_update_primary_plane] Writing base 00060000 00000000 0 0 5120
May 16 15:15:42 pike kernel: [    6.868784] [drm:intel_crtc_mode_set] [ENCODER:10:None-10] set [MODE:0:1024x768]
May 16 15:15:42 pike kernel: [    6.869450] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:42 pike kernel: [    6.869454] [drm:intel_calculate_wm] FIFO entries required for mode: 68
May 16 15:15:42 pike kernel: [    6.869456] [drm:intel_calculate_wm] FIFO watermark level: -23
May 16 15:15:42 pike kernel: [    6.869459] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:42 pike kernel: [    6.869461] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:42 pike kernel: [    6.869463] [drm:intel_calculate_wm] FIFO watermark level: 5
May 16 15:15:42 pike kernel: [    6.869466] [drm:i9xx_update_wm] FIFO watermarks - A: 1, B: 5
May 16 15:15:42 pike kernel: [    6.869469] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 1, B: 5, C: 2, SR 1

Ah, finally the driver notes that there's an external monitor! Watermark still at -23, rounded up to +1. Nice try, but no dice.

May 16 15:15:52 pike kernel: [   31.091473] [drm:intel_dump_pipe_config] requested mode:
May 16 15:15:52 pike kernel: [   31.091481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x0 0xa
May 16 15:15:52 pike kernel: [   31.091485] [drm:intel_dump_pipe_config] adjusted mode:
May 16 15:15:52 pike kernel: [   31.091493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x0 0xa
May 16 15:15:52 pike kernel: [   31.091500] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x0 flags: 0xa
May 16 15:15:52 pike kernel: [   31.091504] [drm:intel_dump_pipe_config] port clock: 65000
May 16 15:15:52 pike kernel: [   31.091508] [drm:intel_dump_pipe_config] pipe src size: 1024x768
May 16 15:15:52 pike kernel: [   31.091513] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
May 16 15:15:52 pike kernel: [   31.091518] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
May 16 15:15:52 pike kernel: [   31.091522] [drm:intel_dump_pipe_config] ips: 0
May 16 15:15:52 pike kernel: [   31.091526] [drm:intel_dump_pipe_config] double wide: 0
May 16 15:15:52 pike kernel: [   31.091546] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 5 p(0,73)@ 31.91540 -> 31.90400 [e 1 us, 0 rep]
May 16 15:15:52 pike kernel: [   31.112062] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:52 pike kernel: [   31.112071] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:52 pike kernel: [   31.112077] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:52 pike kernel: [   31.112081] [drm:intel_calculate_wm] FIFO watermark level: 5
May 16 15:15:52 pike kernel: [   31.112086] [drm:i9xx_update_wm] FIFO watermarks - A: 45, B: 5
May 16 15:15:52 pike kernel: [   31.112091] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 45, B: 5, C: 2, SR 1
May 16 15:15:52 pike kernel: [   31.112102] [drm:drm_calc_timestamping_constants] crtc 5: hwmode: htotal 1344, vtotal 806, vdisplay 768
May 16 15:15:52 pike kernel: [   31.112108] [drm:drm_calc_timestamping_constants] crtc 5: clock 65000 kHz framedur 16665600 linedur 20676, pixeldur 15
May 16 15:15:52 pike kernel: [   31.126344] [drm:i9xx_update_primary_plane] Writing base 00800000 00000000 0 0 4096
May 16 15:15:52 pike kernel: [   31.126365] [drm:intel_crtc_mode_set] [ENCODER:9:DAC-9] set [MODE:0:1024x768]
May 16 15:15:52 pike kernel: [   31.127030] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:52 pike kernel: [   31.127036] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:52 pike kernel: [   31.127040] [drm:intel_calculate_wm] FIFO watermark level: 4
May 16 15:15:52 pike kernel: [   31.127045] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:52 pike kernel: [   31.127049] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:52 pike kernel: [   31.127053] [drm:intel_calculate_wm] FIFO watermark level: 5
May 16 15:15:52 pike kernel: [   31.127058] [drm:i9xx_update_wm] FIFO watermarks - A: 4, B: 5
May 16 15:15:52 pike kernel: [   31.127063] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 4, B: 5, C: 2, SR 1
May 16 15:15:52 pike kernel: [   31.132908] [drm:intel_connector_check_state] [CONNECTOR:11:LVDS-1]
May 16 15:15:52 pike kernel: [   31.132919] [drm:intel_connector_check_state] [CONNECTOR:8:VGA-1]
May 16 15:15:52 pike kernel: [   31.132925] [drm:check_encoder_state] [ENCODER:9:DAC-9]
May 16 15:15:52 pike kernel: [   31.132931] [drm:check_encoder_state] [ENCODER:10:None-10]
May 16 15:15:52 pike kernel: [   31.132936] [drm:check_crtc_state] [CRTC:5]
May 16 15:15:52 pike kernel: [   31.132953] [drm:check_crtc_state] [CRTC:7]

Still later: Ok, why should I use pipe A altogether... Probably because there are two monitors, maybe? Watermarks at +4 and +5. Better, but still wrong.

Later...

May 16 15:15:57 pike kernel: [   36.435245] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:57 pike kernel: [   36.435261] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:57 pike kernel: [   36.435265] [drm:intel_calculate_wm] FIFO watermark level: 4
May 16 15:15:57 pike kernel: [   36.435270] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:57 pike kernel: [   36.435275] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:57 pike kernel: [   36.435279] [drm:intel_calculate_wm] FIFO watermark level: 5
May 16 15:15:57 pike kernel: [   36.435284] [drm:i9xx_update_wm] FIFO watermarks - A: 4, B: 5
May 16 15:15:57 pike kernel: [   36.435289] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 4, B: 5, C: 2, SR 1
May 16 15:15:57 pike kernel: [   36.435320] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
May 16 15:15:57 pike kernel: [   36.435333] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
May 16 15:15:57 pike kernel: [   36.435682] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:15:57 pike kernel: [   36.435696] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:57 pike kernel: [   36.435700] [drm:intel_calculate_wm] FIFO watermark level: 4
May 16 15:15:57 pike kernel: [   36.435705] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:15:57 pike kernel: [   36.435710] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:15:57 pike kernel: [   36.435713] [drm:intel_calculate_wm] FIFO watermark level: 5
May 16 15:15:57 pike kernel: [   36.435719] [drm:i9xx_update_wm] FIFO watermarks - A: 4, B: 5
May 16 15:15:57 pike kernel: [   36.435724] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 4, B: 5, C: 2, SR 1

Ok, at least a bit of consistency. We're at +4,+5. Too bad, it's off...

Later...

May 16 15:35:34 pike kernel: [ 1213.520226] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 1 : v 5 p(0,146)@ 1213.520193 -> 1213.517175 [e 1 us, 0 rep]
May 16 15:35:34 pike kernel: [ 1213.575897] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:35:34 pike kernel: [ 1213.575916] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:35:34 pike kernel: [ 1213.575920] [drm:intel_calculate_wm] FIFO watermark level: 4
May 16 15:35:34 pike kernel: [ 1213.575926] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:35:34 pike kernel: [ 1213.575931] [drm:i9xx_update_wm] FIFO watermarks - A: 4, B: 46
May 16 15:35:34 pike kernel: [ 1213.575937] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 4, B: 46, C: 2, SR 1
May 16 15:35:34 pike kernel: [ 1213.577316] [drm:intel_connector_check_state] [CONNECTOR:8:VGA-1]
May 16 15:35:34 pike kernel: [ 1213.577328] [drm:check_encoder_state] [ENCODER:9:DAC-9]
May 16 15:35:34 pike kernel: [ 1213.577334] [drm:check_encoder_state] [ENCODER:10:None-10]
May 16 15:35:34 pike kernel: [ 1213.577342] [drm:check_crtc_state] [CRTC:5]
May 16 15:35:34 pike kernel: [ 1213.577362] [drm:check_crtc_state] [CRTC:7]
May 16 15:35:34 pike kernel: [ 1213.577400] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.577414] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.577427] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.577436] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.577448] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.577476] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 5 p(0,509)@ 1213.577468 -> 1213.566943 [e 1 us, 0 rep]
May 16 15:35:34 pike kernel: [ 1213.584069] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:35:34 pike kernel: [ 1213.584079] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:35:34 pike kernel: [ 1213.584085] [drm:i9xx_update_wm] FIFO watermarks - A: 45, B: 46
May 16 15:35:34 pike kernel: [ 1213.584090] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 45, B: 46, C: 2, SR 1
May 16 15:35:34 pike kernel: [ 1213.584957] [drm:check_encoder_state] [ENCODER:9:DAC-9]
May 16 15:35:34 pike kernel: [ 1213.584964] [drm:check_encoder_state] [ENCODER:10:None-10]
May 16 15:35:34 pike kernel: [ 1213.584970] [drm:check_crtc_state] [CRTC:5]
May 16 15:35:34 pike kernel: [ 1213.584983] [drm:check_crtc_state] [CRTC:7]

Huh, let's try something completely new! +45,+46. Well, guess what, doesn't work...

May 16 15:35:34 pike kernel: [ 1213.650767] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.650790] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.650807] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.650816] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.650829] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.651004] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.651014] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.651023] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.651031] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.651041] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETPROPERTY
May 16 15:35:34 pike kernel: [ 1213.651730] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) A: 47
May 16 15:35:34 pike kernel: [ 1213.651737] [drm:intel_calculate_wm] FIFO entries required for mode: 41
May 16 15:35:34 pike kernel: [ 1213.651741] [drm:intel_calculate_wm] FIFO watermark level: 4
May 16 15:35:34 pike kernel: [ 1213.651746] [drm:i830_get_fifo_size] FIFO size - (0x00017e5f) B: 48
May 16 15:35:34 pike kernel: [ 1213.651752] [drm:i9xx_update_wm] FIFO watermarks - A: 4, B: 46
May 16 15:35:34 pike kernel: [ 1213.651757] [drm:i9xx_update_wm] Setting FIFO watermarks - A: 4, B: 46, C: 2, SR 1
May 16 15:35:34 pike kernel: [ 1213.669006] [drm:intel_connector_check_state] [CONNECTOR:8:VGA-1]
May 16 15:35:34 pike kernel: [ 1213.669024] [drm:check_encoder_state] [ENCODER:9:DAC-9]
May 16 15:35:34 pike kernel: [ 1213.669030] [drm:check_encoder_state] [ENCODER:10:None-10]
May 16 15:35:34 pike kernel: [ 1213.669038] [drm:check_crtc_state] [CRTC:5]
May 16 15:35:34 pike kernel: [ 1213.669058] [drm:check_crtc_state] [CRTC:7]
May 16 15:35:34 pike kernel: [ 1213.669123] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, I915_GEM_THROTTLE
May 16 15:35:34 pike kernel: [ 1213.670062] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, I915_GEM_PWRITE
May 16 15:35:34 pike kernel: [ 1213.670104] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, I915_GEM_EXECBUFFER2
May 16 15:35:34 pike kernel: [ 1213.670117] [drm:i915_gem_do_execbuffer] UXA submitting garbage DR4, fixing up
May 16 15:35:34 pike kernel: [ 1213.670227] [drm:drm_ioctl] pid=3040, dev=0xe200, auth=1, I915_GEM_MADVISE

Ok, why not disable pipe B again, and use a wrong value for pipe A. Guess what... still not working...

Anyhow, you get the story. The fix is actually simple.

1) Detect that you have a 830GM or 835GM.
2) If the value for the watermark register is lower than 8, set it to 8.

Done. Added to the kernel, stuff works.

Know what? Basel isn't far from Stuttgart. I'm close to catch a train and promise a good "Schocki" just to get this fixed. (-; I'll bring the R31 along.

It's not that I haven't had a patch for it. Really trivial. I wonder what keeps you from adding this to the kernel and just make things working?

Thanks, enjoy, and have a nice weekend!

Greetings,
Thomas

You mean this patch?

index f671aca..3981898 100644
@@ -944,7 +944,7 @@ static const struct intel_watermark_params i915_wm_info = {
 static const struct intel_watermark_params i830_wm_info = {
        I855GM_FIFO_SIZE,
        I915_MAX_WM,
-       1,
+       8,
        2,
        I830_FIFO_LINE_SIZE
 };

@@ -1001,7 +1001,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
        /* Don't promote wm_size to unsigned... */
        if (wm_size > (long)wm->max_wm)
                wm_size = wm->max_wm;
-       if (wm_size <= 0)
+       if (wm_size < (long)wm->default_wm)
                wm_size = wm->default_wm;
        return wm_size;
 }

I haven't spotted any explanation as to why that is, but a rough guess would be that we program it to read in blocks of 8 superwords and that it tries and fails to read from memory when the fifo only has room for 1 superword.
-Chris

Chris Wilson, Intel Open Source Technology Centre

I have it - we need to proper align watermark limits and fifo sizes and round them apparently. Bspec at least strongly suggests that, and it would perfectly fit Thomas' symptoms.

Unfortunately that branch is still sitting ducks somewhere on a machine :( The problem is that we need to frob the watermark functions a bit to make this work correctly and in all cases, and my first attempt looked horribly and disappeared in a tangential death trap ...

Still trying to grab some time from somewhere to resurrect this. -Daniel

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Where have you seen that? And how should they be aligned? I've never seen anything like that in the spec. Also based on tests on my 830 it doesn't need special alignment, it just needs some kind of minumum value that's always somewhere around 6-8 (IIRC).

I do see this note "Up to FIFO Size minus burst length + 32 bytes" in one of the tables in the display doc. I can't tell if that means 'fifo_size - (burst_size + 32B)' or 'fifo_size - burst_size + 32B'. But in any case would actually make the minimum allowed value 7 or 9 since we always configure the burst size to 8.

On Gen3 the units change to 64B but it still has the same note with the +32B, so I'm not sure what should be done there. I guess it's just a copy paste fumble and maybe the same minimum value should still apply.

Ville Syrjälä
Intel OTC

Yeah the burst size stuff - afaiu we should select the biggest one possible and if that's not working out round the watermark up to match the burst size. I didn't spot the +32/-32bytes anywhere though ... I guess going with burst_size + 1 should be safest, especially if we make the code more flexible to also allow a burst size of 4 for the really high-res stuff.
-Daniel

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Am 16.05.2014 18:50, schrieb Daniel Vetter:

For example. There are a couple of possibilities to add this. If this is too invasive, it is not too hard to add a similar check to i9xx_update_wm for generation 2 only, and enforce the same type of check to i830_update_wm

This would be highly appreciated, yes. I currently constantly patch my kernel to keep the graphics working, but that's please not a permanent solution.

Thank you, and have a nice weekend.

Greetings,
Thomas

Hi Daniel, hi folks,

still a couple of observations from my side on this. The 1024x786x24 mode here uses a clock of 65MHz (65000kHz), if that is inserted into the
watermark computation, it computes from that a prefetch of 40 entries, and thus a watermark level of four, which is much much too high. To get a stable display, the watermark level can be at most eight.

However, if I program the FW_BLC register by hand, I can set the watermark down to 32, i.e. 15(!) entries, and I still get a wonderful stable display, scrolling and everything included.

If I compare that with what is required by intel_calculate_wm() to get the same value, I find that the input is, in some place, off by about a factor of two. Which could mean:

a) the latency is too high by a factor of two. Even with a latency of 2500ns, I do get a good watermark level and a stable display. The limit is around 1500ns.

b) the I830_FIFO_LINE_SIZE is off by a factor of two. Is it really 32 bytes? Is it *measured* in bytes? With a line size twice as large, the result would fit again.

c) Is the I830 FIFO_SIZE really 47? This is the value I get when I debug i9xx_update_wm(). It seems the code splits the totally available fifo (unified fifo of the 830GM) of 95 entries approximately in half for pipe A and pipe B. Is the *unit* correct? Is the fifo size measured in *entries*?

What makes me wonder is that there is really approximately a factor of two between the *real* limit and the value computed by the code, which looks to me that at some point a division or multiplication by two is missing.

Finally, a regression with the 3.15.0 code: I already had the phenomenon that the boot console is vertically shifted, which is caused by the pipe-a quirk (without that quirk, the display is correct), but it now also happens from time to time that the DVO is again not clocked correctly. The screen then goes dead in the boot console, but as soon as X starts up, I get again a display. This display is sometimes a bit broken (flickers, as if the frequency is about 40Hz, not 60Hz) or no display at all. Switching to the boot console and back to X resolves the issue. As said, disable the pipe_A quirk and we are good.

A second observation is that the boot console now reports PIPE_A (and sometimes also) PIPE_B underruns during the bootstrap, only once. The system recovers from this (if you call a dead boot console as above "recovery"), so something is likely broken with the quirk. (No news, of course).

Greetings,
Thomas

Hi Daniel, hi folks,

according to my knowledge, the pipe A quirk is unconditionally enabled on the 830 to allow resume to work properly. Unfortunately, it does quite the opposite on the S6010, it breaks resume completely.

If the pipe A quirk is disabled, then the boot console works correctly. Resume does not, the display is dead, but it is possible to remotely connect to the machine, from there POST the video card (via vbetool post), stop X, then restart X, then the display is back.

If the pipe A quirk is enabled, then try to resume from suspend, then the machine is dead completely. You can ping it, but not log in. I currently have not yet tried to figure out where it hangs, but I would suspect the problem is somewhere in the i915 kernel module. The display just stays black.

Thus, in addition to the watermark fix I proposed, please *disable* the unconditional pipe A quirk for the 830GM since it really breaks things, not only the boot console.

Greetings,
Thomas

Can you go right ahead and please submit this as a patch?

Thanks, Daniel

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Hi folks,

as by discussion, the problem with the i830 watermark problems is likely that the 830 requires the number of entries in the buffer to be a multiple of the cache line size. I provide hereby a small patch against intel_pm.c that performs the alignment for GEN2 chips.

Tested on the Fujitsu S6010 and R31, seems to work fine here and generates reasonable watermarks that do not flicker.

What is a bit unsatisfactory is that, due to the nature of the patch, the number of entries in the buffer is always rounded up (necessarily, to be conservative), even though for all practical configurations, the rounded up size is too large to fit into the buffer, and thus the rounding direction is "round down" instead of "round up" for all realistic settings.

Anyhow, the stuff works.

Greetings,
Thomas

From: thor <[email protected]>
Date: Sun, 1 Jun 2014 18:33:20 +0200
Subject: [PATCH] Align i830 watermark to cache lines.

---
 drivers/gpu/drm/i915/intel_pm.c |   38 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

index 1840d15..fbfd57c 100644
@@ -1489,6 +1489,22 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
 	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 
+static int round_to_lines(int watermark, int fifo_size, int line_size)
+{
+	int entries = fifo_size - watermark;
+
+	if (entries < 0)
+		entries = 0;
+
+	entries = DIV_ROUND_UP(entries, line_size);
+	while (entries > fifo_size)
+		entries -= line_size;
+
+	watermark = fifo_size - line_size;
+
+	return watermark;
+}
+
 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 {
 	struct drm_device *dev = unused_crtc->dev;

@@ -1520,6 +1536,12 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
 					       wm_info, fifo_size, cpp,
 					       latency_ns);
+
+		if (IS_GEN2(dev))
+			planea_wm = round_to_lines(planea_wm,
+						   fifo_size,
+						   I830_FIFO_LINE_SIZE);
+
 		enabled = crtc;
 	} else
 		planea_wm = fifo_size - wm_info->guard_size;

@@ -1536,6 +1558,12 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
 					       wm_info, fifo_size, cpp,
 					       latency_ns);
+
+		if (IS_GEN2(dev))
+			planeb_wm = round_to_lines(planeb_wm,
+						   fifo_size,
+						   I830_FIFO_LINE_SIZE);
+
 		if (enabled == NULL)
 			enabled = crtc;
 		else

@@ -1631,16 +1659,24 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
 	const struct drm_display_mode *adjusted_mode;
 	uint32_t fwater_lo;
 	int planea_wm;
+	int fifo_size;
 
 	crtc = single_enabled_crtc(dev);
 	if (crtc == NULL)
 		return;
 
 	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
 	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
 				       &i845_wm_info,
-				       dev_priv->display.get_fifo_size(dev, 0),
+				       fifo_size,
 				       4, latency_ns);
+
+	planea_wm = round_to_lines(planea_wm,
+				   fifo_size,
+				   I830_FIFO_LINE_SIZE);
+
+
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
 	fwater_lo |= (3<<8) | planea_wm;
 

1.7.10.4

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Am 02.06.2014 10:27, schrieb Daniel Vetter:

Certainly, but I would prefer to get more information on this. Even though the R31 *also* works without the pipe A quirk, I am not sure it does work on all other hardware configurations.

There is, however, an important difference between the R31 and the S6010: The R31 uses two independent display pipes for the generating the display, LVDS for the internal and VGA for the external display. As a result, frame rates and resolutions can be different between the two outputs.

The S6010, however, seems to use a single pipe design, with the internal display connected via DVI (not LVDS!) and the external by VGA. This has the unfortunate side effect that I cannot set the resolutions of internal and external display independently. Any attempt to modify the external resolution while using the internal screen results in an "no crtc found for output VGA1" when using xrandr. (Not quite sure what this means, but I believe that the VGA output is simply a duplicate of the DVI output, and the two are probably connected through a bios-switchable bridge chip).

Thus, I would *prefer* to be conservative and only disable the pipe_A quirk only in situations where there is a single display pipe (as in the S6010) and, just to be on the safe side, keep it enabled in dual-pipe (as in R31) configurations.

Now I wonder how I could possibly distinguish between the two. Could you please provide some pointers?

Greetings,
Thomas

We've put a crtc restriction on VGA (it needs to be crtc 0) to work around some issues. DVI/LVDS should work on crtc 1. You can set this with the --crtc knob for xrandr.

You're probably the last real user of this hw left. You're needs win, especially if you know that it fixes stuff on other platforms, too.

So holesale removal of the pipe quirk for i830M seems like the right thing to do here. Especially since Chris also complained that it makes stuff worse for his i845.
-Daniel

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Hi Daniel, hi others,

please find a patch attached that disables the pipe A quirk for the Fujitsu S6010. I will probably add a line for the R31 later, I only need to add the model number.

How is the watermark-alignment patch for the 830 doing, btw?

Greetings,
Thomas

From: thor <[email protected]>
Date: Mon, 2 Jun 2014 17:32:55 +0200
Subject: [PATCH 2/2] Disabling the pipe A quirk for the Fujitsu S6010.

---
 drivers/gpu/drm/i915/intel_display.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

index 54095d4..02b6525 100644
@@ -11535,6 +11535,18 @@ static void quirk_pipea_force(struct drm_device *dev)
 }
 
 /*
+ * Some 830 based systems do not work with the pipe A quirk
+ * correctly since they do not use pipe A in first place
+ */
+static void quirk_disable_pipea_force(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	dev_priv->quirks &= ~QUIRK_PIPEA_FORCE;
+	DRM_INFO("removing the pipe a force quirk for this hardware\n");
+}
+
+/*
  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  */
 static void quirk_ssc_force_disable(struct drm_device *dev)

@@ -11603,6 +11615,9 @@ static struct intel_quirk intel_quirks[] = {
 	/* 830 needs to leave pipe A & dpll A up */
 	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 
+	/* However, do not enable the quirk on S6010 */
+	{ 0x3577, 0x10cf, 0x113c, quirk_disable_pipea_force },
+
 	/* Lenovo U160 cannot use SSC on LVDS */
 	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
 

1.7.10.4

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Like I've explained, this is nacked. I'll merge the patch I've wanted now. -Daniel

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Hi Daniel,

Excuse my ignorance, but what do you mean by "naked"? Do you need anything else (for the watermark patch) to get it going? It is signed-off? Is this not done correctly?

Sorry for my ignorance.

Greetings,
Thomas

nack = not acknowledged, i.e. rejected. Comes from tcp. I've applied the patch instead to just remove the quirk on all i830M.
-Daniel

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Am 02.06.2014 19:39, schrieb Daniel Vetter:

Ok, thanks, I'm fine with that.

Greetings,
Thomas

Hi Daniel, dear intel experts,

Unfortunately, I cannot. Whenever I put DVI1 (which is connected to the internal screen) on crt1, the internal screen stays blank. Where would I need to modify the sources to test whether I could try the reverse, i.e. drive VGA with crt1? (That's not possibly, as you say).

I neither found a way to un-clone the screens, i.e. you can say that xrandr should place VGA1 to the left of DVI1, but xrandr --verbose still claims that VGA1 and DVI1 are clones of each other. The best you get is a blank screen on DVI1, and a high-resolution display on VGA1, but not two independent monitors with differing resolutions.

Here is the configuration when booting. It clones the monitors, even though the bios says "internal only". Never mind, this works:

(p.s. any news from the watermark-alignment patch? Is this acceptable?)

Screen 0: minimum 320 x 200, current 2048 x 1536, maximum 2048 x 2048
VGA1 disconnected 2048x1536+0+0 (0x48) normal (normal left inverted right x axis y axis) 0mm x 0mm panning 2048x1536+0+0

    Identifier: 0x41
    Timestamp:  463642
    Subpixel:   unknown
    Gamma:      1.0:1.0:1.0
    Brightness: 1.0
    Clones:     DVI1
    CRTC:       0
    CRTCs:      0
    Panning:    2048x1536+0+0
    Tracking:   0x0+0+0
    Border:     0/0/0/0
    Transform:  1.000000 0.000000 0.000000
                0.000000 1.000000 0.000000
                0.000000 0.000000 1.000000
               filter:
DVI1 connected 2048x1536+0+0 (0x48) normal (normal left inverted right x axis y axis) 0mm x 0mm panning 2048x1536+0+0
    Identifier: 0x42
    Timestamp:  463642
    Subpixel:   horizontal rgb
    Gamma:      1.0:1.0:1.0
    Brightness: 1.0
    Clones:     VGA1
    CRTC:       0
    CRTCs:      0 1
    Panning:    2048x1536+0+0
    Tracking:   0x0+0+0
    Border:     0/0/0/0
    Transform:  1.000000 0.000000 0.000000
                0.000000 1.000000 0.000000
                0.000000 0.000000 1.000000
               filter:
  1024x768 (0x48)   65.0MHz -HSync -VSync *current
        h: width  1024 start 1048 end 1184 total 1344 skew    0 clock   

48.4KHz
v: height 768 start 771 end 777 total 806 clock
60.0Hz
800x600 (0x4c) 40.0MHz +HSync +VSync
h: width 800 start 840 end 968 total 1056 skew 0 clock
37.9KHz
v: height 600 start 601 end 605 total 628 clock
60.3Hz
800x600 (0x4d) 36.0MHz +HSync +VSync
h: width 800 start 824 end 896 total 1024 skew 0 clock
35.2KHz
v: height 600 start 601 end 603 total 625 clock
56.2Hz
640x480 (0x52) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock
31.5KHz
v: height 480 start 489 end 492 total 525 clock
59.9Hz

--

And this is the register dump:

                 DCC: 0x00000000 (`7rbFtndu)
           CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh 
disabled, ch0 enh disabled, flex disabled, ep not present)
              C0DRB0: 0x00000000 (0x0000)
              C0DRB1: 0x00000000 (0x0000)
              C0DRB2: 0x00000000 (0x0000)
              C0DRB3: 0x00000000 (0x0000)
              C1DRB0: 0x00000000 (0x0000)
              C1DRB1: 0x00000000 (0x0000)
              C1DRB2: 0x00000000 (0x0000)
              C1DRB3: 0x00000000 (0x0000)
             C0DRA01: 0x00000000 (0x0000)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000000 (0x0000)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x3ff60001
   VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, 
p2 = 4)
           DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB 
input buffer disabled)
        CACHE_MODE_0: 0x00000000
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT)
      RENCLK_GATE_D1: 0x00000000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x80004084 (enabled, pipe A, stall disabled, 
detected)
               SDVOC: 0x90004084 (enabled, pipe A, stall disabled, 
detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00017e5f
              DSPFW1: 0x00000000
              DSPFW2: 0x00000000
              DSPFW3: 0x00000000
                ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, 
-vsync)
                DVOB: 0x80004084 (enabled, pipe A, no stall, -hsync, 
-vsync)
                DVOC: 0x90004084 (enabled, pipe A, stall, -hsync, -vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x00000000
     PORT_HOTPLUG_EN: 0x00000000
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0x98000000 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x02ff03ff (1024, 768)
            DSPABASE: 0x03000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0x80000000 (enabled, single-wide)
            PIPEASRC: 0x03ff02ff (1024, 768)
           PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE 
VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x35a28000
    CURSOR_A_CONTROL: 0x04000027
   CURSOR_A_POSITION: 0x000a0271
                FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
                FPA1: 0x0004150d (n = 4, m1 = 21, m2 = 13)
              DPLL_A: 0xd0820000 (enabled, dvo, default clock, 
DAC/serial mode, p1 = 4, p2 = 4)
           DPLL_A_MD: 0x00000000
            HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
            HBLANK_A: 0x053f03ff (1024 start, 1344 end)
             HSYNC_A: 0x049f0417 (1048 start, 1184 end)
            VTOTAL_A: 0x032502ff (768 active, 806 total)
            VBLANK_A: 0x032502ff (768 start, 806 end)
             VSYNC_A: 0x03080302 (771 start, 777 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x19000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00001400 (5120 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x02ff03ff (1024, 768)
            DSPBBASE: 0x00060000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0x00000000 (disabled, single-wide)
            PIPEBSRC: 0x03ff02ff (1024, 768)
           PIPEBSTAT: 0x10000000 (status: CRC_DONE_ENABLE)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x10000000
   CURSOR_B_POSITION: 0x009f801d
                FPB0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
                FPB1: 0x0004150d (n = 4, m1 = 21, m2 = 13)
              DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default 
clock, DAC/serial mode, p1 = 2, p2 = 2)
           DPLL_B_MD: 0x00000000
            HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
            HBLANK_B: 0x053f03ff (1024 start, 1344 end)
             HSYNC_B: 0x049f0417 (1048 start, 1184 end)
            VTOTAL_B: 0x032502ff (768 active, 806 total)
            VBLANK_B: 0x032502ff (768 start, 806 end)
             VSYNC_B: 0x03080302 (771 start, 777 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00021207
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x0000888b
            VGACNTRL: 0x80000000 (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0x00000000
         FBC_LL_BASE: 0x00000000
         FBC_CONTROL: 0x00000000
         FBC_COMMAND: 0x00000000
          FBC_STATUS: 0x00000000
        FBC_CONTROL2: 0x00000000
       FBC_FENCE_OFF: 0x00000000
         FBC_MOD_NUM: 0x00000000
             MI_MODE: 0x00000000
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000307
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x01000351 (enabled, X tiled, 16384 pitch, 
0x01000000 - 0x01800000 (8192kb))
            FENCE  1: 0x05000561 (enabled, X tiled, 32768 pitch, 
0x05000000 - 0x07000000 (32768kb))
            FENCE  2: 0x01600131 (enabled, X tiled, 4096 pitch, 
0x01600000 - 0x01800000 (2048kb))
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x03000561 (enabled, X tiled, 32768 pitch, 
0x03000000 - 0x05000000 (32768kb))
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x00000000 (disabled)
            FENCE  9: 0x00000000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000048 (disabled)
           FENCE  13: 0x00000002 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x00000000 (disabled)
         FENCE END 0: 0x00000000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000048 (disabled)
         FENCE END 2: 0x00000002 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000

pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4
pipe B dot 260000 n 4 m1 21 m2 13 p1 2 p2 2

---

If I try to move DVI1 to crtc 1, the internal screen stays blank. Then, I can change the resolution of the external screen, but without any picture on DVI1. This is what I get:

Screen 0: minimum 320 x 200, current 2048 x 1536, maximum 2048 x 2048
VGA1 connected 2048x1536+0+0 (0x46) normal (normal left inverted right x axis y axis) 338mm x 270mm panning 2048x1536+0+0

    Identifier: 0x41
    Timestamp:  258836
    Subpixel:   unknown
    Gamma:      1.0:1.0:1.0
    Brightness: 1.0
    Clones:     DVI1
    CRTC:       0
    CRTCs:      0
    Panning:    2048x1536+0+0
    Tracking:   0x0+0+0
    Border:     0/0/0/0
    Transform:  1.000000 0.000000 0.000000
                0.000000 1.000000 0.000000
                0.000000 0.000000 1.000000
               filter:
    EDID:
        00ffffffffffff004c2d1d0037314847
        1a0c01030f221b8cea6f8ba25a4d9424
        1a5156bfef8081806140454031400101
        010101010101302a009851002a403070
        1300520e1100001e000000fd0038551e
        510e000a202020202020000000fc0053
        796e634d61737465720a2020000000ff
        0048344c543630343930380a20200054
  1280x1024 (0x43)  108.0MHz +HSync +VSync +preferred
        h: width  1280 start 1328 end 1440 total 1688 skew    0 clock   
64.0KHz
        v: height 1024 start 1025 end 1028 total 1066           clock   
60.0Hz
  1280x1024 (0x44)  135.0MHz +HSync +VSync
        h: width  1280 start 1296 end 1440 total 1688 skew    0 clock   
80.0KHz
        v: height 1024 start 1025 end 1028 total 1066           clock   
75.0Hz
  1152x864 (0x45)  108.0MHz +HSync +VSync
        h: width  1152 start 1216 end 1344 total 1600 skew    0 clock   

67.5KHz
v: height 864 start 865 end 868 total 900 clock
75.0Hz
1024x768 (0x46) 78.8MHz +HSync +VSync *current

        h: width  1024 start 1040 end 1136 total 1312 skew    0 clock   

60.1KHz
v: height 768 start 769 end 772 total 800 clock
75.1Hz
1024x768 (0x47) 75.0MHz -HSync -VSync

        h: width  1024 start 1048 end 1184 total 1328 skew    0 clock   

56.5KHz
v: height 768 start 771 end 777 total 806 clock
70.1Hz
1024x768 (0x48) 65.0MHz -HSync -VSync

        h: width  1024 start 1048 end 1184 total 1344 skew    0 clock   

48.4KHz
v: height 768 start 771 end 777 total 806 clock
60.0Hz
832x624 (0x49) 57.3MHz -HSync -VSync
h: width 832 start 864 end 928 total 1152 skew 0 clock
49.7KHz
v: height 624 start 625 end 628 total 667 clock
74.6Hz
800x600 (0x4a) 50.0MHz +HSync +VSync
h: width 800 start 856 end 976 total 1040 skew 0 clock
48.1KHz
v: height 600 start 637 end 643 total 666 clock
72.2Hz
800x600 (0x4b) 49.5MHz +HSync +VSync
h: width 800 start 816 end 896 total 1056 skew 0 clock
46.9KHz
v: height 600 start 601 end 604 total 625 clock
75.0Hz
800x600 (0x4c) 40.0MHz +HSync +VSync
h: width 800 start 840 end 968 total 1056 skew 0 clock
37.9KHz
v: height 600 start 601 end 605 total 628 clock
60.3Hz
800x600 (0x4d) 36.0MHz +HSync +VSync
h: width 800 start 824 end 896 total 1024 skew 0 clock
35.2KHz
v: height 600 start 601 end 603 total 625 clock
56.2Hz
640x480 (0x4e) 31.5MHz -HSync -VSync
h: width 640 start 656 end 720 total 840 skew 0 clock
37.5KHz
v: height 480 start 481 end 484 total 500 clock
75.0Hz
640x480 (0x4f) 31.5MHz -HSync -VSync
h: width 640 start 664 end 704 total 832 skew 0 clock
37.9KHz
v: height 480 start 489 end 491 total 520 clock
72.8Hz
640x480 (0x50) 30.2MHz -HSync -VSync
h: width 640 start 704 end 768 total 864 skew 0 clock
35.0KHz
v: height 480 start 483 end 486 total 525 clock
66.7Hz
640x480 (0x51) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock
31.5KHz
v: height 480 start 490 end 492 total 525 clock
60.0Hz
640x480 (0x52) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock
31.5KHz
v: height 480 start 489 end 492 total 525 clock
59.9Hz
720x400 (0x53) 28.3MHz -HSync +VSync
h: width 720 start 738 end 846 total 900 skew 0 clock
31.5KHz
v: height 400 start 412 end 414 total 449 clock
70.1Hz
DVI1 connected 800x600+1024+0 (0x4c) normal (normal left inverted right x axis y axis) 0mm x 0mm

    Identifier: 0x42
    Timestamp:  258836
    Subpixel:   horizontal rgb
    Gamma:      1.0:1.0:1.0
    Brightness: 1.0
    Clones:     VGA1
    CRTC:       1
    CRTCs:      0 1
    Transform:  1.000000 0.000000 0.000000
                0.000000 1.000000 0.000000
                0.000000 0.000000 1.000000
               filter:
  1024x768 (0x48)   65.0MHz -HSync -VSync
        h: width  1024 start 1048 end 1184 total 1344 skew    0 clock   

48.4KHz
v: height 768 start 771 end 777 total 806 clock
60.0Hz
800x600 (0x4c) 40.0MHz +HSync +VSync *current
h: width 800 start 840 end 968 total 1056 skew 0 clock
37.9KHz
v: height 600 start 601 end 605 total 628 clock
60.3Hz
800x600 (0x4d) 36.0MHz +HSync +VSync
h: width 800 start 824 end 896 total 1024 skew 0 clock
35.2KHz
v: height 600 start 601 end 603 total 625 clock
56.2Hz
640x480 (0x52) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock
31.5KHz
v: height 480 start 489 end 492 total 525 clock
59.9Hz

Note that DVI1 still claims being a clone of VGA1, but the screen remains dark. The resolution is now a different one, but black in 800x600 is still black. (-: This is the register configuration:

                 DCC: 0x00000000 (`tbvqxd
x)
           CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh 
disabled, ch0 enh disabled, flex disabled, ep not present)
              C0DRB0: 0x00000000 (0x0000)
              C0DRB1: 0x00000000 (0x0000)
              C0DRB2: 0x00000000 (0x0000)
              C0DRB3: 0x00000000 (0x0000)
              C1DRB0: 0x00000000 (0x0000)
              C1DRB1: 0x00000000 (0x0000)
              C1DRB2: 0x00000000 (0x0000)
              C1DRB3: 0x00000000 (0x0000)
             C0DRA01: 0x00000000 (0x0000)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000000 (0x0000)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x3ff60001
   VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, 
p2 = 4)
           DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB 
input buffer disabled)
        CACHE_MODE_0: 0x00000000
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT)
      RENCLK_GATE_D1: 0x00000000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x80004084 (enabled, pipe A, stall disabled, 
detected)
               SDVOC: 0xd000409c (enabled, pipe B, stall disabled, 
detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00017e5f
              DSPFW1: 0x00000000
              DSPFW2: 0x00000000
              DSPFW3: 0x00000000
                ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, 
-vsync)
                DVOB: 0x80004084 (enabled, pipe A, no stall, -hsync, 
-vsync)
                DVOC: 0xd000409c (enabled, pipe B, stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x00000000
     PORT_HOTPLUG_EN: 0x00000000
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0x98000000 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x02ff03ff (1024, 768)
            DSPABASE: 0x04000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0x80000000 (enabled, single-wide)
            PIPEASRC: 0x03ff02ff (1024, 768)
           PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE 
VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x34d6c000
    CURSOR_A_CONTROL: 0x04000027
   CURSOR_A_POSITION: 0x00180050
                FPA0: 0x00051610 (n = 5, m1 = 22, m2 = 16)
                FPA1: 0x00051610 (n = 5, m1 = 22, m2 = 16)
              DPLL_A: 0x90810000 (enabled, non-dvo, default clock, 
DAC/serial mode, p1 = 3, p2 = 4)
           DPLL_A_MD: 0x00000000
            HTOTAL_A: 0x051f03ff (1024 active, 1312 total)
            HBLANK_A: 0x051f03ff (1024 start, 1312 end)
             HSYNC_A: 0x046f040f (1040 start, 1136 end)
            VTOTAL_A: 0x031f02ff (768 active, 800 total)
            VBLANK_A: 0x031f02ff (768 start, 800 end)
             VSYNC_A: 0x03030300 (769 start, 772 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x99000000 (enabled, pipe B)
          DSPBSTRIDE: 0x00002000 (8192 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x0257031f (800, 600)
            DSPBBASE: 0x04001000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0x80000000 (enabled, single-wide)
            PIPEBSRC: 0x031f0257 (800, 600)
           PIPEBSTAT: 0x10000206 (status: CRC_DONE_ENABLE 
VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x10000000
   CURSOR_B_POSITION: 0x00180050
                FPB0: 0x0002130d (n = 2, m1 = 19, m2 = 13)
                FPB1: 0x0002130d (n = 2, m1 = 19, m2 = 13)
              DPLL_B: 0xd0870000 (enabled, dvo, default clock, 
DAC/serial mode, p1 = 9, p2 = 4)
           DPLL_B_MD: 0x00000000
            HTOTAL_B: 0x041f031f (800 active, 1056 total)
            HBLANK_B: 0x041f031f (800 start, 1056 end)
             HSYNC_B: 0x03c70347 (840 start, 968 end)
            VTOTAL_B: 0x02730257 (600 active, 628 total)
            VBLANK_B: 0x02730257 (600 start, 628 end)
             VSYNC_B: 0x025c0258 (601 start, 605 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00021207
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x0000888b
            VGACNTRL: 0x80000000 (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0x00000000
         FBC_LL_BASE: 0x00000000
         FBC_CONTROL: 0x00000000
         FBC_COMMAND: 0x00000000
          FBC_STATUS: 0x00000000
        FBC_CONTROL2: 0x00000000
       FBC_FENCE_OFF: 0x00000000
         FBC_MOD_NUM: 0x00000000
             MI_MODE: 0x00000000
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000307
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x04000561 (enabled, X tiled, 32768 pitch, 
0x04000000 - 0x06000000 (32768kb))
            FENCE  1: 0x01000561 (enabled, X tiled, 32768 pitch, 
0x01000000 - 0x03000000 (32768kb))
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x03500131 (enabled, X tiled, 4096 pitch, 
0x03500000 - 0x03700000 (2048kb))
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x00000000 (disabled)
            FENCE  9: 0x00000000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000048 (disabled)
           FENCE  13: 0x00000002 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x00000000 (disabled)
         FENCE END 0: 0x00000000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000048 (disabled)
         FENCE END 2: 0x00000002 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000

pipe A dot 78857 n 5 m1 22 m2 16 p1 3 p2 4
pipe B dot 40000 n 2 m1 19 m2 13 p1 9 p2 4

Greetings,
Thomas

index 22d8347f7838..80e3f1fc1ad6 100644
@@ -833,10 +833,7 @@ void intel_crt_init(struct drm_device *dev)
 
 	crt->base.type = INTEL_OUTPUT_ANALOG;
 	crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
-	if (IS_I830(dev))
-		crt->base.crtc_mask = (1 << 0);
-	else
-		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
 	if (IS_GEN2(dev))
 		connector->interlace_allowed = 0;

Yeah, if you can't move the panel to the crtc 1 only cloning will be possible.

Yeah, both connectors use CRTC 0. Have you tried what happens if you:
- disable DVI1 first (--off)
- then enable it on crtc 1?

Cheers, Daniel

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Am 03.06.2014 16:45, schrieb Daniel Vetter:

Same difference, internal screen goes blank with --off, and stays blank after moving it to crtc 1 if I try to re-enable it with --auto or --mode.

I'll try the above patch and then report again my findings, thanks!

Greetings,
Thomas

The oddity in the config is that the LVDS is reported as disconnected. That should not be happening unless there is some sharing going on inside the DVO chip.
-Chris

Chris Wilson, Intel Open Source Technology Centre

Am 03.06.2014 17:14, schrieb Chris Wilson:

Please note that on this specific notebook, the internal screen is connected via DVI, not via LVDS. I don't know what they did with the LVDS output, it's probably - as said - just disconnected.

The R31 has its panel connected via LVDS, and here I can set resolutions independently just fine.

Currently compiling the patch, takes a while on a 1GHhz/1GB P-3 machine. (-;

Greetings,
Thomas

I should have said VGA. Thinking about it, it is likely a shared DDC line so that only a single EDID can be read.
-Chris

Chris Wilson, Intel Open Source Technology Centre

Am 03.06.2014 17:26, schrieb Chris Wilson:

Actually, it gets the EDID from the VGA panel just fine, also shows me the modes it supports. DVI1 has no edit, though it gets its allowable modes from the dvo_ds2501 module.

I now tried to relocate VGA1 to crtc 1, with Daniel's patch. Results are even weirder. I can *set* the resolution to 1280x1024 on VGA1, just that it does not deliver this resolution. My monitor claims (and my vision confirms) that this is still the same 1024x768 mode as on the internal panel.

I can again turn VGA off, relocate it to crtc 1, turn it on again, still says its a clone of DVI1 even though it's on a different crtc.

Chipset (lspci) says its a 82830M/MG graphics controller, PCI id 8086:3577. This *should* be a true 830MG (specs agree), thus I *believe* it should have two display pipes. The R31 is built around the very same chipset and has no problems with independent output. Looks like they shared the VGA and DVI output,and left the other output just dangling. Weird.

Screen 0: minimum 320 x 200, current 1280 x 1024, maximum 2048 x 2048
VGA1 connected 1280x1024+0+0 (0xa7) normal (normal left inverted right x axis y axis) 338mm x 270mm

	Identifier: 0x41
	Timestamp:  504191
	Subpixel:   unknown
	Gamma:      1.0:1.0:1.0
	Brightness: 1.0
	Clones:     DVI1
	CRTC:       1
	CRTCs:      0 1
	Transform:  1.000000 0.000000 0.000000
	            0.000000 1.000000 0.000000
	            0.000000 0.000000 1.000000
	           filter:
	EDID:
		00ffffffffffff004c2d1d0037314847
		1a0c01030f221b8cea6f8ba25a4d9424
		1a5156bfef8081806140454031400101
		010101010101302a009851002a403070
		1300520e1100001e000000fd0038551e
		510e000a202020202020000000fc0053
		796e634d61737465720a2020000000ff
		0048344c543630343930380a20200054
  1280x1024 (0xa7)  108.0MHz +HSync +VSync *current +preferred
        h: width  1280 start 1328 end 1440 total 1688 skew    0 clock 
 64.0KHz
        v: height 1024 start 1025 end 1028 total 1066           clock 
 60.0Hz
  1280x1024 (0xa8)  135.0MHz +HSync +VSync
        h: width  1280 start 1296 end 1440 total 1688 skew    0 clock 
 80.0KHz
        v: height 1024 start 1025 end 1028 total 1066           clock 
 75.0Hz
  1152x864 (0xa9)  108.0MHz +HSync +VSync
        h: width  1152 start 1216 end 1344 total 1600 skew    0 clock 
 67.5KHz
        v: height  864 start  865 end  868 total  900           clock 
 75.0Hz
  1024x768 (0xaa)   78.8MHz +HSync +VSync
        h: width  1024 start 1040 end 1136 total 1312 skew    0 clock 
 60.1KHz
        v: height  768 start  769 end  772 total  800           clock 
 75.1Hz
  1024x768 (0xab)   75.0MHz -HSync -VSync
        h: width  1024 start 1048 end 1184 total 1328 skew    0 clock 
 56.5KHz
        v: height  768 start  771 end  777 total  806           clock 
 70.1Hz
  1024x768 (0x43)   65.0MHz -HSync -VSync
        h: width  1024 start 1048 end 1184 total 1344 skew    0 clock 

48.4KHz
v: height 768 start 771 end 777 total 806 clock
60.0Hz
832x624 (0xac) 57.3MHz -HSync -VSync
h: width 832 start 864 end 928 total 1152 skew 0 clock
49.7KHz
v: height 624 start 625 end 628 total 667 clock
74.6Hz
800x600 (0xad) 50.0MHz +HSync +VSync
h: width 800 start 856 end 976 total 1040 skew 0 clock
48.1KHz
v: height 600 start 637 end 643 total 666 clock
72.2Hz
800x600 (0xae) 49.5MHz +HSync +VSync
h: width 800 start 816 end 896 total 1056 skew 0 clock
46.9KHz
v: height 600 start 601 end 604 total 625 clock
75.0Hz
800x600 (0x44) 40.0MHz +HSync +VSync
h: width 800 start 840 end 968 total 1056 skew 0 clock
37.9KHz
v: height 600 start 601 end 605 total 628 clock
60.3Hz
800x600 (0x45) 36.0MHz +HSync +VSync
h: width 800 start 824 end 896 total 1024 skew 0 clock
35.2KHz
v: height 600 start 601 end 603 total 625 clock
56.2Hz
640x480 (0xaf) 31.5MHz -HSync -VSync
h: width 640 start 656 end 720 total 840 skew 0 clock
37.5KHz
v: height 480 start 481 end 484 total 500 clock
75.0Hz
640x480 (0xb0) 31.5MHz -HSync -VSync
h: width 640 start 664 end 704 total 832 skew 0 clock
37.9KHz
v: height 480 start 489 end 491 total 520 clock
72.8Hz
640x480 (0xb1) 30.2MHz -HSync -VSync
h: width 640 start 704 end 768 total 864 skew 0 clock
35.0KHz
v: height 480 start 483 end 486 total 525 clock
66.7Hz
640x480 (0xb2) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock
31.5KHz
v: height 480 start 490 end 492 total 525 clock
60.0Hz
640x480 (0x47) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock
31.5KHz
v: height 480 start 489 end 492 total 525 clock
59.9Hz
720x400 (0xb3) 28.3MHz -HSync +VSync
h: width 720 start 738 end 846 total 900 skew 0 clock
31.5KHz
v: height 400 start 412 end 414 total 449 clock
70.1Hz
DVI1 connected 1280x1024+0+0 (0x43) normal (normal left inverted right x axis y axis) 0mm x 0mm panning 1280x1024+0+0

	Identifier: 0x42
	Timestamp:  504191
	Subpixel:   horizontal rgb
	Gamma:      1.0:1.0:1.0
	Brightness: 1.0
	Clones:     VGA1
	CRTC:       0
	CRTCs:      0 1
	Panning:    1280x1024+0+0
	Tracking:   0x0+0+0
	Border:     0/0/0/0
	Transform:  1.000000 0.000000 0.000000
	            0.000000 1.000000 0.000000
	            0.000000 0.000000 1.000000
	           filter:
  1024x768 (0x43)   65.0MHz -HSync -VSync *current
        h: width  1024 start 1048 end 1184 total 1344 skew    0 clock 

48.4KHz
v: height 768 start 771 end 777 total 806 clock
60.0Hz
800x600 (0x44) 40.0MHz +HSync +VSync
h: width 800 start 840 end 968 total 1056 skew 0 clock
37.9KHz
v: height 600 start 601 end 605 total 628 clock
60.3Hz
800x600 (0x45) 36.0MHz +HSync +VSync
h: width 800 start 824 end 896 total 1024 skew 0 clock
35.2KHz
v: height 600 start 601 end 603 total 625 clock
56.2Hz
640x480 (0x47) 25.2MHz -HSync -VSync
h: width 640 start 656 end 752 total 800 skew 0 clock
31.5KHz
v: height 480 start 489 end 492 total 525 clock
59.9Hz

Registers:

                DCC: 0x00000000 (`tbvqxd
x)
           CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh 
disabled, ch0 enh disabled, flex disabled, ep not present)
              C0DRB0: 0x00000000 (0x0000)
              C0DRB1: 0x00000000 (0x0000)
              C0DRB2: 0x00000000 (0x0000)
              C0DRB3: 0x00000000 (0x0000)
              C1DRB0: 0x00000000 (0x0000)
              C1DRB1: 0x00000000 (0x0000)
              C1DRB2: 0x00000000 (0x0000)
              C1DRB3: 0x00000000 (0x0000)
             C0DRA01: 0x00000000 (0x0000)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000000 (0x0000)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x3ff60001
   VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, 
p2 = 4)
           DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB 
input buffer disabled)
        CACHE_MODE_0: 0x00000000
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT)
      RENCLK_GATE_D1: 0x00000000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x80004084 (enabled, pipe A, stall disabled, 
detected)
               SDVOC: 0xd000409c (enabled, pipe B, stall disabled, 
detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00017e5f
              DSPFW1: 0x00000000
              DSPFW2: 0x00000000
              DSPFW3: 0x00000000
                ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, 
-vsync)
                DVOB: 0x80004084 (enabled, pipe A, no stall, -hsync, 
-vsync)
                DVOC: 0xd000409c (enabled, pipe B, stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x00000000
     PORT_HOTPLUG_EN: 0x00000000
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0x98000000 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x02ff03ff (1024, 768)
            DSPABASE: 0x04000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0x80000000 (enabled, single-wide)
            PIPEASRC: 0x03ff02ff (1024, 768)
           PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE 
VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x34d6c000
    CURSOR_A_CONTROL: 0x04000027
   CURSOR_A_POSITION: 0x00180050
                FPA0: 0x00051610 (n = 5, m1 = 22, m2 = 16)
                FPA1: 0x00051610 (n = 5, m1 = 22, m2 = 16)
              DPLL_A: 0x90810000 (enabled, non-dvo, default clock, 
DAC/serial mode, p1 = 3, p2 = 4)
           DPLL_A_MD: 0x00000000
            HTOTAL_A: 0x051f03ff (1024 active, 1312 total)
            HBLANK_A: 0x051f03ff (1024 start, 1312 end)
             HSYNC_A: 0x046f040f (1040 start, 1136 end)
            VTOTAL_A: 0x031f02ff (768 active, 800 total)
            VBLANK_A: 0x031f02ff (768 start, 800 end)
             VSYNC_A: 0x03030300 (769 start, 772 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x99000000 (enabled, pipe B)
          DSPBSTRIDE: 0x00002000 (8192 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x0257031f (800, 600)
            DSPBBASE: 0x04001000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0x80000000 (enabled, single-wide)
            PIPEBSRC: 0x031f0257 (800, 600)
           PIPEBSTAT: 0x10000206 (status: CRC_DONE_ENABLE 
VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x10000000
   CURSOR_B_POSITION: 0x00180050
                FPB0: 0x0002130d (n = 2, m1 = 19, m2 = 13)
                FPB1: 0x0002130d (n = 2, m1 = 19, m2 = 13)
              DPLL_B: 0xd0870000 (enabled, dvo, default clock, 
DAC/serial mode, p1 = 9, p2 = 4)
           DPLL_B_MD: 0x00000000
            HTOTAL_B: 0x041f031f (800 active, 1056 total)
            HBLANK_B: 0x041f031f (800 start, 1056 end)
             HSYNC_B: 0x03c70347 (840 start, 968 end)
            VTOTAL_B: 0x02730257 (600 active, 628 total)
            VBLANK_B: 0x02730257 (600 start, 628 end)
             VSYNC_B: 0x025c0258 (601 start, 605 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00021207
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x0000888b
            VGACNTRL: 0x80000000 (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0x00000000
         FBC_LL_BASE: 0x00000000
         FBC_CONTROL: 0x00000000
         FBC_COMMAND: 0x00000000
          FBC_STATUS: 0x00000000
        FBC_CONTROL2: 0x00000000
       FBC_FENCE_OFF: 0x00000000
         FBC_MOD_NUM: 0x00000000
             MI_MODE: 0x00000000
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000307
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x04000561 (enabled, X tiled, 32768 pitch, 
0x04000000 - 0x06000000 (32768kb))
            FENCE  1: 0x01000561 (enabled, X tiled, 32768 pitch, 
0x01000000 - 0x03000000 (32768kb))
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x03500131 (enabled, X tiled, 4096 pitch, 
0x03500000 - 0x03700000 (2048kb))
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x00000000 (disabled)
            FENCE  9: 0x00000000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000048 (disabled)
           FENCE  13: 0x00000002 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x00000000 (disabled)
         FENCE END 0: 0x00000000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000048 (disabled)
         FENCE END 2: 0x00000002 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000

pipe A dot 78857 n 5 m1 22 m2 16 p1 3 p2 4
pipe B dot 40000 n 2 m1 19 m2 13 p1 9 p2 4

        ^^^^^^^^^^^^^^^^^

This is short for "Allowed Clones:", not "Active Clones:".

It's even worse than you thought. Somewhere between userspace passing in the mode, and the kernel setting it, it got lost.

                 ^^^^^^^^^^^^^

This means you have configured the two outputs in a mirrored mode, both reading from the same portion of the framebuffer. So it just looks like a cloned setup, with upset displays.

At least this is sane.
-Chris

Chris Wilson, Intel Open Source Technology Centre

Hi folks,

when switching resolutions with xrandr (or otherwise) on the 830MG chipset, I usually get a "Pipe A underrun" error, sometimes resulting in a completely black screen. To my understanding, the internal screen is connected to pipe B on this laptop, thus I wonder why I get the error. Thus, something seems to be broken:

[  406.282457] WARNING: CPU: 0 PID: 2048 at drivers/gpu/drm/i915/intel_display.c:2148 intel_crtc_disable_planes+0x15f/0x170 [i915]()
[  406.282463] Modules linked in: michael_mic arc4 ecb lib80211_crypt_tkip lib80211_crypt_ccmp binfmt_misc fuse loop firewire_sbp2 hid_generic usbhid hid snd_intel8x0 snd_ac97_codec ac97_bus ipw2100 snd_pcm libipw sg cfg80211 i915 snd_seq snd_seq_device snd_timer snd mousedev sr_mod firewire_ohci rfkill cdrom i2c_algo_bit pcmcia firewire_core drm_kms_helper lib80211 soundcore crc_itu_t irda uhci_hcd apanel yenta_socket pcmcia_rsrc input_polldev usbcore drm i2c_i801 psmouse evdev 8139too pcspkr 8139cp mii pcmcia_core crc_ccitt 8250 fujitsu_laptop battery video lpc_ich serial_core mfd_core usb_common intel_agp i2c_core intel_gtt led_class agpgart ac button
[  406.282576] CPU: 0 PID: 2048 Comm: Xorg Tainted: G        W     3.15.0-rc7+ #3
[  406.282583] Hardware name: FUJITSU SIEMENS LIFEBOOK S Series/FJNB159, BIOS Version 1.07  10/28/2002
[  406.282589]  c1316e2e c103451f c13aa868 00000000 00000800 f9092e08 00000864 f9049bcf
[  406.282603]  f9049bcf 00070180 f4a90000 f6b20000 00000000 c1034569 00000009 00000000
[  406.282616]  f9049bcf f5884aa0 18000000 00003286 00000000 f5a9d000 f6b20178 f6b20000
[  406.282630] Call Trace:
[  406.282645]  [<c1316e2e>] ? dump_stack+0xa/0x13
[  406.282659]  [<c103451f>] ? warn_slowpath_common+0x7f/0xb0
[  406.282709]  [<f9049bcf>] ? intel_crtc_disable_planes+0x15f/0x170 [i915]
[  406.282757]  [<f9049bcf>] ? intel_crtc_disable_planes+0x15f/0x170 [i915]
[  406.282768]  [<c1034569>] ? warn_slowpath_null+0x19/0x20
[  406.282816]  [<f9049bcf>] ? intel_crtc_disable_planes+0x15f/0x170 [i915]
[  406.282863]  [<f9049c1a>] ? i9xx_crtc_disable+0x3a/0x620 [i915]
[  406.282877]  [<c10d8e20>] ? __pollwait+0xf0/0xf0
[  406.282887]  [<c10d8e20>] ? __pollwait+0xf0/0xf0
[  406.282934]  [<f903f78f>] ? intel_dump_pipe_config.isra.45+0x2f/0x3a0 [i915]
[  406.282983]  [<f904bbae>] ? __intel_set_mode+0x76e/0x14e0 [i915]
[  406.283032]  [<f904ef33>] ? intel_set_mode+0x23/0x40 [i915]
[  406.283079]  [<f904fcf3>] ? intel_crtc_set_config+0x863/0xc90 [i915]
[  406.283095]  [<c117a196>] ? idr_mark_full+0x46/0x50
[  406.283105]  [<c117a93e>] ? idr_alloc+0x7e/0xe0
[  406.283143]  [<f862c816>] ? drm_mode_set_config_internal+0x46/0xb0 [drm]
[  406.283169]  [<f862fc20>] ? drm_mode_setcrtc+0xc0/0x560 [drm]
[  406.283216]  [<f904723e>] ? intel_crtc_load_lut+0x10e/0x1a0 [i915]
[  406.283242]  [<f862fb60>] ? drm_mode_setplane+0x3f0/0x3f0 [drm]
[  406.283262]  [<f8622704>] ? drm_ioctl+0x1a4/0x5c0 [drm]
[  406.283289]  [<f862fb60>] ? drm_mode_setplane+0x3f0/0x3f0 [drm]
[  406.283311]  [<f8622560>] ? drm_copy_field+0x70/0x70 [drm]
[  406.283322]  [<c10d7fd0>] ? do_vfs_ioctl+0x70/0x540
[  406.283334]  [<c10c93c1>] ? vfs_read+0x101/0x140
[  406.283345]  [<c10d84e3>] ? SyS_ioctl+0x43/0x80
[  406.283360]  [<c131a72f>] ? sysenter_do_call+0x12/0x26
[  406.283367] ---[ end trace ea667942c60a2cf6 ]---
[  406.324991] [drm:i8xx_irq_handler] *ERROR* pipe A underrun
[  413.437244] [drm:i8xx_irq_handler] *ERROR* pipe A underrun

Note that I *also* get a PIPE A underrun error on the boot console, and occasionally a pipe B underrun error, again on the boot console. The errors in the boot console appear regardless of whether the pipe A quirk is enabled or not, thus the problem seems to be somewhere in the mode switching code. Would it be possible to switch a mode by
1) enabling pipe A, 2) switching, 3) disabling pipe A? Note again that turning on pipe A with the quirk mode breaks both the boot console and resume from ram, so that is not an alternative either...

Greetings,
Thomas

Dear intel experts,

just tried to debug the i830 resume on the S6010. With netconsole and netcat, I found that the kernel locks up when trying to load the i915 module on suspend. Here is the output of the kernel:

[ 1772.867519] hid-generic 0003:046D:C05F.002B: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:1d.0-2/input0
[ 1800.068074] INFO: task modprobe:3321 blocked for more than 120 seconds.
[ 1800.068130]       Not tainted 3.15.0-rc7+ #6
[ 1800.068150] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 1800.068177] modprobe        D f86d6600     0  3321   2855 0x00000000
[ 1800.068436]  f4102cb0 00000082 f41c88d4 f86d6600 00000000 f41c88d4 f41c8000 f6a27fec
[ 1800.069063]  f4102cb0 00000000 00000000 f84a5885 f41c88d4 f86d6600 00000000 fffffffa
[ 1800.069682]  f41c8000 f41c88d4 f86d66a8 00000000 f41c8ab0 f84a0038 00000000 00000000
[ 1800.070274] Call Trace:
[ 1800.070587]  [<f86d6600>] ? set_clock+0x50/0x60 [i915]
[ 1800.070664]  [<f84a5885>] ? bit_xfer+0x255/0x4c4 [i2c_algo_bit]
[ 1800.070772]  [<f86d6600>] ? set_clock+0x50/0x60 [i915]
[ 1800.070907]  [<f86d66a8>] ? intel_gpio_post_xfer+0x28/0x60 [i915]
[ 1800.070977]  [<c13199e5>] ? schedule_preempt_disabled+0x5/0x10
[ 1800.071005]  [<c131a640>] ? __ww_mutex_lock_slowpath+0x7c/0xec
[ 1800.071056]  [<f8246dfa>] ? drm_modeset_lock+0x2a/0xb0 [drm]
[ 1800.071185]  [<f86b6579>] ? intel_get_load_detect_pipe+0xa9/0x4b0 [i915]
[ 1800.071320]  [<f86b83b6>] ? intel_modeset_setup_hw_state+0xab6/0xd40 [i915]
[ 1800.071448]  [<f869ca90>] ? gen4_write64+0x50/0x50 [i915]
[ 1800.071513]  [<f8246dfa>] ? drm_modeset_lock+0x2a/0xb0 [drm]
[ 1800.071614]  [<f86b8dfd>] ? intel_modeset_init+0x7bd/0x12f0 [i915]
[ 1800.071676]  [<c10c43d1>] ? kmem_cache_alloc+0x31/0x100
[ 1800.071744]  [<f8232991>] ? drm_irq_install+0xa1/0x180 [drm]
[ 1800.071856]  [<f86e2e41>] ? i915_driver_load+0x9d1/0xee0 [i915]
[ 1800.072023]  [<f86e06e0>] ? i915_dma_init+0x2c0/0x2c0 [i915]
[ 1800.072157]  [<c117c17b>] ? kobject_uevent_env+0xeb/0x4f0
[ 1800.072184]  [<c117c17b>] ? kobject_uevent_env+0xeb/0x4f0
[ 1800.072239]  [<c117bff0>] ? add_uevent_var+0xc0/0xc0
[ 1800.072271]  [<c1224c1c>] ? get_device+0xc/0x20
[ 1800.072407]  [<c1312643>] ? klist_node_init+0x33/0x50
[ 1800.072489]  [<c13126f7>] ? klist_add_tail+0x17/0x40
[ 1800.072668]  [<f8237a41>] ? drm_sysfs_device_add+0xb1/0x110 [drm]
[ 1800.072708]  [<f823479e>] ? drm_dev_register+0x9e/0x100 [drm]
[ 1800.072803]  [<f8236c39>] ? drm_get_pci_dev+0x79/0x1f0 [drm]
[ 1800.072889]  [<c119db2f>] ? pci_device_probe+0x7f/0xd0
[ 1800.072976]  [<c111e4ad>] ? sysfs_create_link+0x1d/0x40
[ 1800.073114]  [<c12286ca>] ? driver_probe_device+0x6a/0x230
[ 1800.073202]  [<c117b5b0>] ? kobject_add_internal+0x150/0x2c0
[ 1800.073366]  [<c1228890>] ? driver_probe_device+0x230/0x230
[ 1800.073392]  [<c1228909>] ? __driver_attach+0x79/0x80
[ 1800.073527]  [<c12270c8>] ? bus_for_each_dev+0x38/0x70
[ 1800.073609]  [<c1228296>] ? driver_attach+0x16/0x20
[ 1800.073771]  [<c1228890>] ? driver_probe_device+0x230/0x230
[ 1800.073797]  [<c1227f41>] ? bus_add_driver+0xe1/0x1e0
[ 1800.073932]  [<c1228e61>] ? driver_register+0x51/0xd0
[ 1800.074020]  [<f80d2000>] ? 0xf80d1fff
[ 1800.074101]  [<f80d2000>] ? 0xf80d1fff
[ 1800.074235]  [<c1000472>] ? do_one_initcall+0xe2/0x130
[ 1800.074316]  [<c131a468>] ? mutex_lock+0x8/0x15
[ 1800.074400]  [<c1095335>] ? jump_label_module_notify+0x155/0x1a0
[ 1800.074487]  [<c104ecf0>] ? notifier_call_chain+0x40/0x60
[ 1800.074571]  [<c104ef3b>] ? __blocking_notifier_call_chain+0x4b/0x70
[ 1800.074738]  [<c107f082>] ? load_module+0x1a62/0x2180
[ 1800.074774]  [<c102d4c0>] ? vmalloc_sync_all+0xd0/0xd0
[ 1800.074911]  [<c107f831>] ? SyS_init_module+0x91/0xd0
[ 1800.075007]  [<c131bc2f>] ? sysenter_do_call+0x12/0x26

Maybe that helps to find the issue with the broken resume on the S6010.

Greetings,
Thomas