Skip to contentSkip to conversation

use documented cmpxchg api

PATCH In review Pranith Kumar 3 participants 5 messages Jun 5, 2014 – Jun 6, 2014 IOMMU

lore
Share & tools
lore

Pranith Kumar

author
#0 lore raw

PATCH 1/1 use documented cmpxchg api

use the documented atomic_cmpxchg instead of __cmpxchg64

This kills the last user of said API in drivers code.

Signed-off-by Pranith Kumar <[email protected]>
---
 drivers/iommu/intel-iommu.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +1 -1
index 6bb3277..270113f 100644
@@ -293,7 +293,7 @@ static inline u64 dma_pte_addr(struct dma_pte *pte)
 	return pte->val & VTD_PAGE_MASK;
 #else
 	/* Must have a full atomic 64-bit read */
-	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+	return  atomic_cmpxchg(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
 #endif
 }
Signature · 1 line
1.7.9.5
#1 lore raw
Quoted 15 lines · Pranith Kumar

use the documented atomic_cmpxchg instead of __cmpxchg64

This kills the last user of said API in drivers code.

Signed-off-by Pranith Kumar <[email protected]>
---
  drivers/iommu/intel-iommu.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +0 -0
index 6bb3277..270113f 100644

drivers/iommu/intel-iommu.c static inline u64 dma_pte_addr(struct dma_pte *pte) · line 296

Quoted 5 lines
drivers/iommu/intel-iommu.c +1 -1
@@ -293,7 +293,7 @@ static inline u64 dma_pte_addr(struct dma_pte *pte)
  	return pte->val & VTD_PAGE_MASK;
  #else
  	/* Must have a full atomic 64-bit read */
-	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+	return  atomic_cmpxchg(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;

This is not equivalent.

The __cmpxchg64() is specifically being used in this case when !CONFIG_64BIT for a full 64-bit RMW, whereas atomic_cmpxchg() uses ints which would be 32-bit RMW.

Regards,
Peter Hurley

#2 lore raw
Quoted 24 lines · Peter Hurley
Quoted 15 lines · Pranith Kumar

use the documented atomic_cmpxchg instead of __cmpxchg64

This kills the last user of said API in drivers code.

Signed-off-by Pranith Kumar <[email protected]>
---
  drivers/iommu/intel-iommu.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +0 -0
index 6bb3277..270113f 100644

drivers/iommu/intel-iommu.c static inline u64 dma_pte_addr(struct dma_pte *pte) · line 296

Quoted 5 lines
drivers/iommu/intel-iommu.c +1 -1
@@ -293,7 +293,7 @@ static inline u64 dma_pte_addr(struct dma_pte *pte)
      return pte->val & VTD_PAGE_MASK;
  #else
      /* Must have a full atomic 64-bit read */
-    return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+    return  atomic_cmpxchg(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;

This is not equivalent.

Quoted 4 lines

The __cmpxchg64() is specifically being used in this case when !CONFIG_64BIT for a full 64-bit RMW, whereas atomic_cmpxchg() uses ints which would be 32-bit RMW.

You are right! The previous patch is wrong in that atomic_cmpxchg needs an atomic_t argument. cmpxchg() handles the size internally using typeof() to figure out the width of RMW. There is also an explicit cmpxchg64() which does the same thing.

Fixed with the following v2:

use the documented cmpxchg instead of __cmpxchg64

This kills the last user of said API in drivers code.

Signed-off-by Pranith Kumar <[email protected]>
---
 drivers/iommu/intel-iommu.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +1 -1
index 6bb3277..270113f 100644
@@ -293,7 +293,7 @@ static inline u64 dma_pte_addr(struct dma_pte *pte)
 	return pte->val & VTD_PAGE_MASK;
 #else
 	/* Must have a full atomic 64-bit read */
-	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+	return  cmpxchg(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
 #endif
 }
Signature · 1 line
1.7.9.5
#3 lore raw
Quoted 31 lines · Pranith Kumar
Quoted 24 lines · Peter Hurley
Quoted 15 lines · Pranith Kumar

use the documented atomic_cmpxchg instead of __cmpxchg64

This kills the last user of said API in drivers code.

Signed-off-by Pranith Kumar <[email protected]>
---
   drivers/iommu/intel-iommu.c |    2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +0 -0
index 6bb3277..270113f 100644

drivers/iommu/intel-iommu.c static inline u64 dma_pte_addr(struct dma_pte *pte) · line 296

Quoted 5 lines
drivers/iommu/intel-iommu.c +1 -1
@@ -293,7 +293,7 @@ static inline u64 dma_pte_addr(struct dma_pte *pte)
       return pte->val & VTD_PAGE_MASK;
   #else
       /* Must have a full atomic 64-bit read */
-    return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+    return  atomic_cmpxchg(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;

This is not equivalent.

Quoted 4 lines

The __cmpxchg64() is specifically being used in this case when !CONFIG_64BIT for a full 64-bit RMW, whereas atomic_cmpxchg() uses ints which would be 32-bit RMW.

Quoted 3 lines

You are right! The previous patch is wrong in that atomic_cmpxchg needs an atomic_t argument. cmpxchg() handles the size internally using typeof() to figure out the width of RMW. There is also an explicit cmpxchg64() which does the same thing.

This won't work either, and should generate a compile or link error on CONFIG_X86_32.

The auto-sizing done by __cmpxchg() does not substitute the cmpxchg8b instruction for the cmpxchg instruction. __X86_CASE_Q is defined as -1 for CONFIG_X86_32 so the 8-byte size variant is dead-code, and calls __cmpxchg_wrong_size() instead.

Quoted 22 lines

Fixed with the following v2:

use the documented cmpxchg instead of __cmpxchg64

This kills the last user of said API in drivers code.

Signed-off-by Pranith Kumar <[email protected]>
---
  drivers/iommu/intel-iommu.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +1 -1
index 6bb3277..270113f 100644
@@ -293,7 +293,7 @@ static inline u64 dma_pte_addr(struct dma_pte *pte)
  	return pte->val & VTD_PAGE_MASK;
  #else
  	/* Must have a full atomic 64-bit read */
-	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+	return  cmpxchg(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
  #endif
  }
#4 lore raw
Quoted 10 lines · Peter Hurley

This won't work either, and should generate a compile or link error on CONFIG_X86_32.

The auto-sizing done by __cmpxchg() does not substitute the cmpxchg8b instruction for the cmpxchg instruction. __X86_CASE_Q is defined as -1 for CONFIG_X86_32 so the 8-byte size variant is dead-code, and calls __cmpxchg_wrong_size() instead.

Fixed with the following v3:

use the documented cmpxchg64 instead of __cmpxchg64.

This kills the last user of said API in drivers code.

Signed-off-by Pranith Kumar <[email protected]>
---
 drivers/iommu/intel-iommu.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +1 -1
index 6bb3277..270113f 100644
@@ -293,7 +293,7 @@ static inline u64 dma_pte_addr(struct dma_pte *pte)
 	return pte->val & VTD_PAGE_MASK;
 #else
 	/* Must have a full atomic 64-bit read */
-	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
+	return  cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
 #endif
 }

-- 1.7.9.5