sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements

index da7c9f0..1f0fbae 100644
@@ -77,7 +77,7 @@ int main(int argc, char *argv[])
 {
 	int fd_in, fd_out;
 	struct boot_img img;
-	unsigned file_size, load_size;
+	unsigned file_size;
 	int count;
 
 	if (argc < 2) {

@@ -101,8 +101,6 @@ int main(int argc, char *argv[])
 	if (file_size > SRAM_LOAD_MAX_SIZE) {
 		fprintf(stderr, "ERROR: File too large!\n");
 		return EXIT_FAILURE;
-	} else {
-		load_size = ALIGN(file_size, sizeof(int));
 	}
 
 	fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);

@@ -113,8 +111,8 @@ int main(int argc, char *argv[])
 
 	/* read file to buffer to calculate checksum */
 	lseek(fd_in, 0, SEEK_SET);
-	count = read(fd_in, img.code, load_size);
-	if (count != load_size) {
+	count = read(fd_in, img.code, file_size);
+	if (count != file_size) {
 		perror("Reading input image");
 		return EXIT_FAILURE;
 	}

@@ -126,7 +124,7 @@ int main(int argc, char *argv[])
 		 & 0x00FFFFFF);
 	memcpy(img.header.magic, BOOT0_MAGIC, 8);	/* no '0' termination */
 	img.header.length =
-		ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE);
+		ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
 	gen_check_sum(&img.header);
 
 	count = write(fd_out, &img, img.header.length);

index eb7b115..ae0cf1a 100644
@@ -16,28 +16,6 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/mmc.h>
 
-struct sunxi_mmc_des {
-	u32 reserved1_1:1;
-	u32 dic:1;		/* disable interrupt on completion */
-	u32 last_des:1;		/* 1-this data buffer is the last buffer */
-	u32 first_des:1;		/* 1-data buffer is the first buffer,
-				   0-data buffer contained in the next
-				   descriptor is 1st buffer */
-	u32 des_chain:1;	/* 1-the 2nd address in the descriptor is the
-				   next descriptor address */
-	u32 end_of_ring:1;	/* 1-last descriptor flag when using dual
-				   data buffer in descriptor */
-	u32 reserved1_2:24;
-	u32 card_err_sum:1;	/* transfer error flag */
-	u32 own:1;		/* des owner:1-idma owns it, 0-host owns it */
-#define SDXC_DES_NUM_SHIFT 16
-#define SDXC_DES_BUFFER_MAX_LEN	(1 << SDXC_DES_NUM_SHIFT)
-	u32 data_buf1_sz:16;
-	u32 data_buf2_sz:16;
-	u32 buf_addr_ptr1;
-	u32 buf_addr_ptr2;
-};
-
 struct sunxi_mmc_host {
 	unsigned mmc_no;
 	uint32_t *mclkreg;

@@ -189,6 +167,9 @@ static int mmc_core_init(struct mmc *mmc)
 
 	/* Reset controller */
 	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
+	udelay(1000);
+	/* Always read / write data through the CPU */
+	writel(SUNXI_MMC_GCTRL_ACCESS_BY_AHB, &mmchost->reg->gctrl);
 
 	return 0;
 }

@@ -220,85 +201,6 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 	return 0;
 }
 
-static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
-{
-	struct sunxi_mmc_host *mmchost = mmc->priv;
-	unsigned byte_cnt = data->blocksize * data->blocks;
-	unsigned char *buff;
-	unsigned des_idx = 0;
-	unsigned buff_frag_num =
-		(byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
-	unsigned remain;
-	unsigned i, rval;
-	ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
-
-	buff = data->flags & MMC_DATA_READ ?
-	    (unsigned char *)data->dest : (unsigned char *)data->src;
-	remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
-
-	flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
-	for (i = 0; i < buff_frag_num; i++, des_idx++) {
-		memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
-		pdes[des_idx].des_chain = 1;
-		pdes[des_idx].own = 1;
-		pdes[des_idx].dic = 1;
-		if (buff_frag_num > 1 && i != buff_frag_num - 1)
-			pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */
-		else
-			pdes[des_idx].data_buf1_sz = remain;
-
-		pdes[des_idx].buf_addr_ptr1 =
-		    (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
-		if (i == 0)
-			pdes[des_idx].first_des = 1;
-
-		if (i == buff_frag_num - 1) {
-			pdes[des_idx].dic = 0;
-			pdes[des_idx].last_des = 1;
-			pdes[des_idx].end_of_ring = 1;
-			pdes[des_idx].buf_addr_ptr2 = 0;
-		} else {
-			pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
-		}
-	}
-	flush_cache((unsigned long)pdes,
-		    sizeof(struct sunxi_mmc_des) * (des_idx + 1));
-
-	rval = readl(&mmchost->reg->gctrl);
-	/* Enable DMA */
-	writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE,
-	       &mmchost->reg->gctrl);
-	/* Reset iDMA */
-	writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac);
-	/* Enable iDMA */
-	writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE,
-	       &mmchost->reg->dmac);
-	rval = readl(&mmchost->reg->idie) &
-		~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ);
-	if (data->flags & MMC_DATA_WRITE)
-		rval |= SUNXI_MMC_IDIE_TXIRQ;
-	else
-		rval |= SUNXI_MMC_IDIE_RXIRQ;
-	writel(rval, &mmchost->reg->idie);
-	writel((u32) pdes, &mmchost->reg->dlba);
-	writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
-	       &mmchost->reg->ftrglevel);
-
-	return 0;
-}
-
-static void mmc_enable_dma_accesses(struct mmc *mmc, int dma)
-{
-	struct sunxi_mmc_host *mmchost = mmc->priv;
-
-	unsigned int gctrl = readl(&mmchost->reg->gctrl);
-	if (dma)
-		gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
-	else
-		gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
-	writel(gctrl, &mmchost->reg->gctrl);
-}
-
 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
 			 unsigned int done_bit, const char *what)
 {

@@ -327,7 +229,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	unsigned int timeout_msecs;
 	int error = 0;
 	unsigned int status = 0;
-	unsigned int usedma = 0;
 	unsigned int bytecnt = 0;
 
 	if (mmchost->fatal_err)

@@ -378,20 +279,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 
 		bytecnt = data->blocksize * data->blocks;
 		debug("trans data %d bytes\n", bytecnt);
-#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
-		if (bytecnt > 64) {
-#else
-		if (0) {
-#endif
-			usedma = 1;
-			mmc_enable_dma_accesses(mmc, 1);
-			ret = mmc_trans_data_by_dma(mmc, data);
-			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
-		} else {
-			mmc_enable_dma_accesses(mmc, 0);
-			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
-			ret = mmc_trans_data_by_cpu(mmc, data);
-		}
+		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+		ret = mmc_trans_data_by_cpu(mmc, data);
 		if (ret) {
 			error = readl(&mmchost->reg->rint) & \
 				SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;

@@ -405,7 +294,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		goto out;
 
 	if (data) {
-		timeout_msecs = usedma ? 120 * bytecnt : 120;
+		timeout_msecs = 120;
 		debug("cacl timeout %x msec\n", timeout_msecs);
 		error = mmc_rint_wait(mmc, timeout_msecs,
 				      data->blocks > 1 ?

@@ -442,23 +331,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		debug("mmc resp 0x%08x\n", cmd->response[0]);
 	}
 out:
-	if (data && usedma) {
-		/* IDMASTAREG
-		 * IDST[0] : idma tx int
-		 * IDST[1] : idma rx int
-		 * IDST[2] : idma fatal bus error
-		 * IDST[4] : idma descriptor invalid
-		 * IDST[5] : idma error summary
-		 * IDST[8] : idma normal interrupt sumary
-		 * IDST[9] : idma abnormal interrupt sumary
-		 */
-		status = readl(&mmchost->reg->idst);
-		writel(status, &mmchost->reg->idst);
-		writel(0, &mmchost->reg->idie);
-		writel(0, &mmchost->reg->dmac);
-		writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE,
-		       &mmchost->reg->gctrl);
-	}
 	if (error < 0) {
 		writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
 		mmc_update_clk(mmc);

index 5d72d62..fd02d0d 100644
@@ -70,7 +70,6 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_MMC_SUNXI
 #define CONFIG_MMC_SUNXI_SLOT		0
-#define CONFIG_MMC_SUNXI_USE_DMA
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
 

index 49c9448..c80b421 100644
@@ -56,6 +56,13 @@ int gpio_init(void)
 
 void reset_cpu(ulong addr)
 {
+	static const struct sunxi_wdog *wdog =
+		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+	/* Set the watchdog for its shortest interval (.5s) and wait */
+	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+	while (1);
 }
 
 /* do some early init */

index 6aacfd7..58e14fd 100644
@@ -11,6 +11,11 @@
 #ifndef _SUNXI_TIMER_H_
 #define _SUNXI_TIMER_H_
 
+#define WDT_CTRL_RESTART	(0x1 << 0)
+#define WDT_CTRL_KEY		(0x0a57 << 1)
+#define WDT_MODE_EN		(0x1 << 0)
+#define WDT_MODE_RESET_EN	(0x1 << 1)
+
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>

index b4c3d5c..b4b5089 100644
@@ -13,7 +13,14 @@
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
+#ifdef CONFIG_SUN4I
+	puts("CPU:   Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
+#else
+#warning Please update cpu_info.c with correct CPU information
+	puts("CPU:   SUNXI Family\n");
+#endif
 	return 0;
 }
 #endif

151 lines not on this page · raw message

new file mode 100644
index 0000000..399028c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 480,
+	.type = 3,
+	.rank_num = 1,
+	.density = 4096,
+	.io_width = 16,
+	.bus_width = 32,
+	.cas = 6,
+	.zq = 123,
+	.odt_en = 0,
+	.size = 1024,
+	.tpr0 = 0x30926692,
+	.tpr1 = 0x1090,
+	.tpr2 = 0x1a0c8,
+	.tpr3 = 0,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = 0,
+	.emr2 = 0,
+	.emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}

new file mode 100644
index 0000000..6560b65
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <[email protected]>
+ *
+ * Configuration settings for the Allwinner A10 (sun4i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A10 specific configuration
+ */
+#define CONFIG_SUN4I		/* sun4i SoC generation */
+
+#define CONFIG_SYS_PROMPT		"sun4i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */

index c80b421..0118f5b 100644
@@ -47,9 +47,21 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
+#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+#else
+#error Unsupported console port number. Please fix pin mux settings in board.c
+#endif
 
 	return 0;
 }

index b4b5089..5cf35ac 100644
@@ -15,6 +15,14 @@ int print_cpuinfo(void)
 {
 #ifdef CONFIG_SUN4I
 	puts("CPU:   Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_SUN5I
+	u32 val = readl(SUNXI_SID_BASE + 0x08);
+	switch ((val >> 12) & 0xf) {
+	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
+	case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
+	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
+	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
+	}
 #elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
 #else

index 1de7529..0f1ceec 100644
@@ -155,6 +155,16 @@ static void mctl_enable_dllx(u32 phase)
 }
 
 static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN5I
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0x1031, 0x1031, 0x0735, 0x1035,
+	0x1035, 0x0731, 0x1031, 0,
+	0x0301, 0x0301, 0x0301, 0x0301,
+	0x0301, 0x0301, 0x0301, 0
+#endif
 #ifdef CONFIG_SUN4I
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0, 0,

@@ -257,9 +267,15 @@ static void mctl_setup_dram_clock(u32 clk)
 #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	/* setup MBUS clock */
 	reg_val = CCM_MBUS_CTRL_GATE |
+#ifdef CONFIG_SUN7I
 		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
 		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
 		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#else /* defined(CONFIG_SUN5I) */
+		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#endif
 	writel(reg_val, &ccm->mbus_clk_cfg);
 #endif
 

@@ -468,6 +484,11 @@ unsigned long dramc_init(struct dram_para *para)
 	/* setup DRAM relative clock */
 	mctl_setup_dram_clock(para->clock);
 
+#ifdef CONFIG_SUN5I
+	/* Disable any pad power save control */
+	writel(0, &dram->ppwrsctl);
+#endif
+
 	/* reset external DRAM */
 #ifndef CONFIG_SUN7I
 	mctl_ddr3_reset();

new file mode 100644
index 0000000..8154ea2
@@ -0,0 +1,32 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 408,
+	.type = 3,
+	.rank_num = 1,
+	.density = 2048,
+	.io_width = 16,
+	.bus_width = 16,
+	.cas = 9,
+	.zq = 123,
+	.odt_en = 0,
+	.size = 256,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = 0,
+	.emr2 = 0x10,
+	.emr3 = 0,
+
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}

new file mode 100644
index 0000000..59343cb
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 384,
+	.type = 3,
+	.rank_num = 1,
+	.density = 2048,
+	.io_width = 8,
+	.bus_width = 32,
+	.cas = 9,
+	.zq = 123,
+	.odt_en = 0,
+	.size = 1024,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = 0x04,
+	.emr2 = 0x10,
+	.emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}

new file mode 100644
index 0000000..43f0d67
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <[email protected]>
+ *
+ * Configuration settings for the Allwinner A13 (sun5i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SUN5I		/* sun5i SoC generation */
+
+#define CONFIG_SYS_PROMPT		"sun5i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */

index fd02d0d..1d1c87d 100644
@@ -161,7 +161,9 @@
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 
+#ifndef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX              1       /* UART0 */
+#endif
 
 #ifdef CONFIG_SUNXI_GMAC
 #define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */

index 0118f5b..7d86409 100644
@@ -11,6 +11,7 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <serial.h>

@@ -91,11 +92,16 @@ void s_init(void)
 	clock_init();
 	timer_init();
 	gpio_init();
+	i2c_init_board();
 
 #ifdef CONFIG_SPL_BUILD
 	gd = &gdata;
 	preloader_console_init();
 
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	/* Needed early by sunxi_board_init if PMU is enabled */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
 	sunxi_board_init();
 #endif
 }

new file mode 100644
index 0000000..dc5406b
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2014 - Hans de Goede <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SUNXI_I2C_H_
+#define _SUNXI_I2C_H_
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_I2C_MVTWSI_BASE	SUNXI_TWI0_BASE
+/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
+#define CONFIG_SYS_TCLK		24000000
+
+#endif

index b05d0b9..543b809 100644
@@ -106,6 +106,13 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+void i2c_init_board(void)
+{
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+	clock_twi_onoff(0, 1);
+}
+
 #ifdef CONFIG_SPL_BUILD
 void sunxi_board_init(void)
 {

index 5ba0e03..e670515 100644
@@ -22,6 +22,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_SUNXI)
+#include <asm/arch/i2c.h>
 #else
 #error Driver mvtwsi not supported by SoC or board
 #endif

@@ -30,6 +32,20 @@
  * TWSI register structure
  */
 
+#ifdef CONFIG_SUNXI
+
+struct  mvtwsi_registers {
+	u32 slave_address;
+	u32 xtnd_slave_addr;
+	u32 data;
+	u32 control;
+	u32 status;
+	u32 baudrate;
+	u32 soft_reset;
+};
+
+#else
+
 struct  mvtwsi_registers {
 	u32 slave_address;
 	u32 data;

@@ -43,6 +59,8 @@ struct  mvtwsi_registers {
 	u32 soft_reset;
 };
 
+#endif
+
 /*
  * Control register fields
  */

index 1d1c87d..2db083c 100644
@@ -161,6 +161,15 @@
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 
+/* I2C */
+#define CONFIG_SPL_I2C_SUPPORT
+/* No CONFIG_SYS_I2C as we use the non converted mvtwsi driver */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SUNXI
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x7f
+#define CONFIG_CMD_I2C
+
 #ifndef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX              1       /* UART0 */
 #endif

index 543b809..8375711 100644
@@ -12,6 +12,9 @@
  */
 
 #include <common.h>
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
 #include <asm/arch/clock.h>
 #include <asm/arch/dram.h>
 #include <asm/arch/gpio.h>

@@ -116,12 +119,31 @@ void i2c_init_board(void)
 #ifdef CONFIG_SPL_BUILD
 void sunxi_board_init(void)
 {
+	int power_failed = 0;
 	unsigned long ramsize;
 
+#ifdef CONFIG_AXP209_POWER
+	power_failed |= axp209_init();
+	power_failed |= axp209_set_dcdc2(1400);
+	power_failed |= axp209_set_dcdc3(1250);
+	power_failed |= axp209_set_ldo2(3000);
+	power_failed |= axp209_set_ldo3(2800);
+	power_failed |= axp209_set_ldo4(2800);
+#endif
+
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
 	printf(" %lu MiB\n", ramsize >> 20);
 	if (!ramsize)
 		hang();
+
+	/*
+	 * Only clock up the CPU to full speed if we are reasonably
+	 * assured it's being powered with suitable core voltage
+	 */
+	if (!power_failed)
+		clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+	else
+		printf("Failed to set core voltage! Can't set CPU frequency\n");
 }
 #endif

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new file mode 100644
index 0000000..9edfa3f
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+extern int axp209_set_dcdc2(int mvolt);
+extern int axp209_set_dcdc3(int mvolt);
+extern int axp209_set_ldo2(int mvolt);
+extern int axp209_set_ldo3(int mvolt);
+extern int axp209_set_ldo4(int mvolt);
+extern void axp209_poweroff(void);
+extern int axp209_init(void);
+extern int axp209_poweron_by_dc(void);
+extern int axp209_power_button(void);

index 6560b65..037f995 100644
@@ -12,6 +12,7 @@
  * A10 specific configuration
  */
 #define CONFIG_SUN4I		/* sun4i SoC generation */
+#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #define CONFIG_SYS_PROMPT		"sun4i# "
 

index 43f0d67..c6138b7 100644
@@ -12,6 +12,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_SUN5I		/* sun5i SoC generation */
+#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #define CONFIG_SYS_PROMPT		"sun5i# "
 

index 9b693f7..d9be104 100644
@@ -13,6 +13,7 @@
  * A20 specific configuration
  */
 #define CONFIG_SUN7I		/* sun7i SoC generation */
+#define CONFIG_CLK_FULL_SPEED		912000000
 
 #define CONFIG_SYS_PROMPT		"sun7i# "
 

index 2db083c..b76227e 100644
@@ -170,6 +170,11 @@
 #define CONFIG_SYS_I2C_SLAVE		0x7f
 #define CONFIG_CMD_I2C
 
+/* PMU */
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
+#define CONFIG_SPL_POWER_SUPPORT
+#endif
+
 #ifndef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX              1       /* UART0 */
 #endif

index 8375711..8607eb3 100644
@@ -12,6 +12,9 @@
  */
 
 #include <common.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
 #ifdef CONFIG_AXP209_POWER
 #include <axp209.h>
 #endif

@@ -122,6 +125,13 @@ void sunxi_board_init(void)
 	int power_failed = 0;
 	unsigned long ramsize;
 
+#ifdef CONFIG_AXP152_POWER
+	power_failed = axp152_init();
+	power_failed |= axp152_set_dcdc2(1400);
+	power_failed |= axp152_set_dcdc3(1500);
+	power_failed |= axp152_set_dcdc4(1250);
+	power_failed |= axp152_set_ldo2(3000);
+#endif
 #ifdef CONFIG_AXP209_POWER
 	power_failed |= axp209_init();
 	power_failed |= axp209_set_dcdc2(1400);

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new file mode 100644
index 0000000..b34c194
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+int axp152_set_dcdc2(int mvolt);
+int axp152_set_dcdc3(int mvolt);
+int axp152_set_dcdc4(int mvolt);
+int axp152_set_ldo2(int mvolt);
+void axp152_poweroff(void);
+int axp152_init(void);

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525 lines not on this page · raw message

index 63481ec..e45dd7a 100644
@@ -78,8 +78,8 @@ int sh_eth_initialize(bd_t *bis);
 int skge_initialize(bd_t *bis);
 int smc91111_initialize(u8 dev_num, int base_addr);
 int smc911x_initialize(u8 dev_num, int base_addr);
+int sunxi_emac_initialize(bd_t *bis);
 int sunxi_gmac_initialize(bd_t *bis);
-int sunxi_wemac_initialize(bd_t *bis);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);

index 7d86409..024c8c1 100644
@@ -123,6 +123,14 @@ int cpu_eth_init(bd_t *bis)
 {
 	int rc;
 
+#ifdef CONFIG_SUNXI_EMAC
+	rc = sunxi_emac_initialize(bis);
+	if (rc < 0) {
+		printf("sunxi: failed to initialize emac\n");
+		return rc;
+	}
+#endif
+
 #ifdef CONFIG_SUNXI_GMAC
 	rc = sunxi_gmac_initialize(bis);
 	if (rc < 0) {

index b76227e..a9d104a 100644
@@ -179,6 +179,11 @@
 #define CONFIG_CONS_INDEX              1       /* UART0 */
 #endif
 
+/* Ethernet support */
+#ifdef CONFIG_SUNXI_EMAC
+#define CONFIG_MII			/* MII PHY management		*/
+#endif
+
 #ifdef CONFIG_SUNXI_GMAC
 #define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
 #define CONFIG_DW_AUTONEG

index e48328d..e7ff952 100644
@@ -16,17 +16,28 @@ int sunxi_gmac_initialize(bd_t *bis)
 	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
 
 	/* Set MII clock */
+#ifdef CONFIG_RGMII
 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
 		CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+		CCM_GMAC_CTRL_GPIT_MII);
+#endif
 
 	/* Configure pin mux settings for GMAC */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
 		/* skip unused pins in RGMII mode */
 		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
 			continue;
+#endif
 		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 
+#ifdef CONFIG_RGMII
 	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#else
+	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
 }