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SoC and board integration for RSPI on RZ/A1H

PATCH Superseded Geert Uytterhoeven 4 participants 17 messages Dec 27, 2013 – Jan 8, 2014

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures SPI +3 more subsystems

v2 of 3 Superseded Latest is v3 →

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Geert Uytterhoeven

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#0 lore raw

v2 cover SoC and board integration for RSPI on RZ/A1H

This patch series integrates Renesas RSPI on the RZ/A1H aka R7S72100 SoC, and the Genmai development board.

The series is based on renesas-devel-v3.13-rc5-20131226, with Magnus' pinctrl, Wolfram's riic, and Simon's sh_eth work applied on top.

It was tested on the Genmai development board (genmai-reference), using an in-kernel version of Documentation/spi/spidev_test.c, exercising loopback mode on rspi1, with the same outcome as the SDK reference code.

Notes:
1. The proposed DT bindings also talk about QSPI on the R8A779x, as those SoCs use the same driver.
2. As the actual spi-rspi driver doesn't use DT yet, platform devices and spi board info are still used from C to instantiate SPI buses and their children, while pinctrl is performed by DT.
3. It will not work with the non-reference version of genmai, due to missing pinmux configuration in setup-r7s72100.c.
4. Patches [4/8] and [5/8] are new.

[1/8] pinctrl: sh-pfc: r7s72100: Add RSPI support
[2/8] ARM: shmobile: r7s72100: Add RSPI clocks
[3/8] ARM: shmobile: r7s72100: Add RSPI platform devices [4/8] ARM: shmobile: genmai: Add RSPI children (NEW) [5/8] [RFC] ARM: shmobile: genmai: Add preliminary RSPI pinmux (NEW) [6/8] [RFC] Documentation: dt: Add Renesas RSPI/QSPI bindings [7/8] [RFC] ARM: shmobile: r7s72100 dtsi: Add RSPI nodes [8/8] [RFC] ARM: shmobile: genmai reference: Add RSPI nodes

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

author
#1 lore raw

PATCH v2 1/8 pinctrl: sh-pfc: r7s72100: Add RSPI support

From: Geert Uytterhoeven <[email protected]>

Signed-off-by Geert Uytterhoeven <[email protected]>
Cc Linus Walleij <[email protected]>

---
v2: No changes

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   94 +++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r7s72100.c +94 -0
index 267677c683c5..5e0f03c14fcc 100644
@@ -138,6 +138,70 @@ RIIC1(RZ_PIN_AND_MUX)
 RIIC2(RZ_PIN_AND_MUX)
 RIIC3(RZ_PIN_AND_MUX)
 
+#define RSPI0(fn)			\
+	fn(rspi0, rspck,  2, 12, 2)	\
+	fn(rspi0, ssl0,   2, 13, 2)	\
+	fn(rspi0, mosi,   2, 14, 2)	\
+	fn(rspi0, miso,   2, 15, 2)	\
+	fn(rspi0, rspck,  7, 15, 2)	\
+	fn(rspi0, ssl0,   8,  0, 2)	\
+	fn(rspi0, mosi,   8,  1, 2)	\
+	fn(rspi0, miso,   8,  2, 2)	\
+	fn(rspi0, rspck, 10, 12, 4)	\
+	fn(rspi0, ssl0,  10, 13, 4)	\
+	fn(rspi0, mosi,  10, 14, 4)	\
+	fn(rspi0, miso,  10, 15, 4)	\
+
+#define RSPI1(fn)			\
+	fn(rspi1, rspck,  4,  4, 2)	\
+	fn(rspi1, ssl0,   4,  5, 2)	\
+	fn(rspi1, mosi,   4,  6, 2)	\
+	fn(rspi1, miso,   4,  7, 2)	\
+	fn(rspi1, rspck,  6,  4, 7)	\
+	fn(rspi1, ssl0,   6,  5, 7)	\
+	fn(rspi1, mosi,   6,  6, 7)	\
+	fn(rspi1, miso,   6,  7, 7)	\
+	fn(rspi1, rspck, 11, 12, 2)	\
+	fn(rspi1, ssl0,  11, 13, 2)	\
+	fn(rspi1, mosi,  11, 14, 2)	\
+	fn(rspi1, miso,  11, 15, 2)	\
+
+#define RSPI2(fn)			\
+	fn(rspi2, rspck,  8,  3, 3)	\
+	fn(rspi2, ssl0,   8,  4, 3)	\
+	fn(rspi2, mosi,   8,  5, 3)	\
+	fn(rspi2, miso,   8,  6, 3)	\
+	fn(rspi2, rspck,  8, 14, 5)	\
+	fn(rspi2, ssl0,   8, 15, 5)	\
+	fn(rspi2, mosi,   9,  0, 5)	\
+	fn(rspi2, miso,   9,  1, 5)	\
+
+#define RSPI3(fn)			\
+	fn(rspi3, rspck,  3,  0, 8)	\
+	fn(rspi3, ssl0,   3,  1, 8)	\
+	fn(rspi3, mosi,   3,  2, 8)	\
+	fn(rspi3, miso,   3,  3, 8)	\
+	fn(rspi3, rspck,  5,  0, 8)	\
+	fn(rspi3, ssl0,   5,  1, 8)	\
+	fn(rspi3, mosi,   5,  2, 8)	\
+	fn(rspi3, miso,   5,  3, 8)	\
+
+#define RSPI4(fn)			\
+	fn(rspi4, rspck,  2,  8, 8)	\
+	fn(rspi4, ssl0,   2,  9, 8)	\
+	fn(rspi4, mosi,   2, 10, 8)	\
+	fn(rspi4, miso,   2, 11, 8)	\
+	fn(rspi4, rspck,  4,  0, 7)	\
+	fn(rspi4, ssl0,   4,  1, 7)	\
+	fn(rspi4, mosi,   4,  2, 7)	\
+	fn(rspi4, miso,   4,  3, 7)	\
+
+RSPI0(RZ_PIN_AND_MUX)
+RSPI1(RZ_PIN_AND_MUX)
+RSPI2(RZ_PIN_AND_MUX)
+RSPI3(RZ_PIN_AND_MUX)
+RSPI4(RZ_PIN_AND_MUX)
+
 #define SCIF0(fn)			\
 	fn(scif0, clk, 2, 13, 6)	\
 	fn(scif0, txd, 2, 14, 6)	\

@@ -312,6 +376,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	RIIC1(RZ_PMX_GROUP)
 	RIIC2(RZ_PMX_GROUP)
 	RIIC3(RZ_PMX_GROUP)
+	RSPI0(RZ_PMX_GROUP)
+	RSPI1(RZ_PMX_GROUP)
+	RSPI2(RZ_PMX_GROUP)
+	RSPI3(RZ_PMX_GROUP)
+	RSPI4(RZ_PMX_GROUP)
 	SCIF0(RZ_PMX_GROUP)
 	SCIF1(RZ_PMX_GROUP)
 	SCIF2(RZ_PMX_GROUP)

@@ -339,6 +408,26 @@ static const char * const riic3_groups[] = {
 	RIIC3(RZ_GROUPS)
 };
 
+static const char * const rspi0_groups[] = {
+	RSPI0(RZ_GROUPS)
+};
+
+static const char * const rspi1_groups[] = {
+	RSPI1(RZ_GROUPS)
+};
+
+static const char * const rspi2_groups[] = {
+	RSPI2(RZ_GROUPS)
+};
+
+static const char * const rspi3_groups[] = {
+	RSPI3(RZ_GROUPS)
+};
+
+static const char * const rspi4_groups[] = {
+	RSPI4(RZ_GROUPS)
+};
+
 static const char * const scif0_groups[] = {
 	SCIF0(RZ_GROUPS)
 };

@@ -380,6 +469,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(riic1),
 	SH_PFC_FUNCTION(riic2),
 	SH_PFC_FUNCTION(riic3),
+	SH_PFC_FUNCTION(rspi0),
+	SH_PFC_FUNCTION(rspi1),
+	SH_PFC_FUNCTION(rspi2),
+	SH_PFC_FUNCTION(rspi3),
+	SH_PFC_FUNCTION(rspi4),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif2),
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH v2 2/8 ARM: shmobile: r7s72100: Add RSPI clocks

In reply to Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v2: Correct platform device names ("rspi%u" -> "rspi.%u")

 arch/arm/mach-shmobile/clock-r7s72100.c |   21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)
arch/arm/mach-shmobile/clock-r7s72100.c +18 -3
index 0242ca5f499a..6ae341ca713c 100644
@@ -22,13 +22,15 @@
 #include <mach/common.h>
 #include <mach/r7s72100.h>
 
-/* registers */
+/* Frequency Control Registers */
 #define FRQCR		0xfcfe0010
 #define FRQCR2		0xfcfe0014
+/* Standby Control Registers */
 #define STBCR3		0xfcfe0420
 #define STBCR4		0xfcfe0424
 #define STBCR7		0xfcfe0430
 #define STBCR9		0xfcfe0438
+#define STBCR10		0xfcfe043c
 
 #define PLL_RATE 30
 

@@ -146,12 +148,20 @@ struct clk div4_clks[DIV4_NR] = {
 					| CLK_ENABLE_ON_INIT),
 };
 
-enum {	MSTP97, MSTP96, MSTP95, MSTP94,
+enum {
+	MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
+	MSTP97, MSTP96, MSTP95, MSTP94,
 	MSTP74,
 	MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
-	MSTP33,	MSTP_NR };
+	MSTP33,	MSTP_NR
+};
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
+	[MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
+	[MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
+	[MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
+	[MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
 	[MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
 	[MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
 	[MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */

@@ -179,6 +189,11 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 
 	/* MSTP clocks */
+	CLKDEV_DEV_ID("rspi.0", &mstp_clks[MSTP107]),
+	CLKDEV_DEV_ID("rspi.1", &mstp_clks[MSTP106]),
+	CLKDEV_DEV_ID("rspi.2", &mstp_clks[MSTP105]),
+	CLKDEV_DEV_ID("rspi.3", &mstp_clks[MSTP104]),
+	CLKDEV_DEV_ID("rspi.4", &mstp_clks[MSTP103]),
 	CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
 	CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
 	CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
Signature · 1 line
1.7.9.5
author
#3 lore raw

PATCH v2 3/8 ARM: shmobile: r7s72100: Add RSPI platform devices

In reply to Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v2:
- Correct platform device names ("rspi%u.0" -> "rspi.%u")
- Add missing platform data
- Correct summary (resources -> platform devices)

 arch/arm/mach-shmobile/setup-r7s72100.c |   34 +++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
arch/arm/mach-shmobile/setup-r7s72100.c +34 -0
index 9c0b3a9d5f7a..c353549cad03 100644
@@ -23,6 +23,7 @@
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
+#include <linux/spi/rspi.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r7s72100.h>

@@ -81,6 +82,34 @@ static struct resource mtu2_0_resources[] __initdata = {
 					  &mtu2_##idx##_platform_data,	\
 					  sizeof(struct sh_timer_config))
 
+/* RSPI */
+#define RSPI_RESOURCE(idx, baseaddr, irq)				\
+static const struct resource rspi##idx##_resources[] __initconst = {	\
+	DEFINE_RES_MEM(baseaddr, 0x24),					\
+	DEFINE_RES_IRQ(irq),		/* SPEI */			\
+	DEFINE_RES_IRQ(irq + 1),	/* SPRI */			\
+	DEFINE_RES_IRQ(irq + 2),	/* SPTI */			\
+}
+
+RSPI_RESOURCE(0, 0xe800c800, gic_iid(270));
+RSPI_RESOURCE(1, 0xe800d000, gic_iid(273));
+RSPI_RESOURCE(2, 0xe800d800, gic_iid(276));
+RSPI_RESOURCE(3, 0xe800e000, gic_iid(279));
+RSPI_RESOURCE(4, 0xe800e800, gic_iid(282));
+
+static const struct rspi_plat_data rspi_pdata __initconst = {
+	.data_width	= 8,
+	.txmode		= false,
+	.spcr2		= false,
+	.num_chipselect	= 1,
+};
+
+#define r7s72100_register_rspi(idx)					\
+	platform_device_register_resndata(&platform_bus, "rspi", idx,	\
+					rspi##idx##_resources,		\
+					ARRAY_SIZE(rspi##idx##_resources), \
+					&rspi_pdata, sizeof(rspi_pdata))
+
 void __init r7s72100_add_dt_devices(void)
 {
 	r7s72100_register_scif(0);

@@ -92,6 +121,11 @@ void __init r7s72100_add_dt_devices(void)
 	r7s72100_register_scif(6);
 	r7s72100_register_scif(7);
 	r7s72100_register_mtu2(0);
+	r7s72100_register_rspi(0);
+	r7s72100_register_rspi(1);
+	r7s72100_register_rspi(2);
+	r7s72100_register_rspi(3);
+	r7s72100_register_rspi(4);
 }
 
 void __init r7s72100_init_early(void)
Signature · 1 line
1.7.9.5
author
#4 lore raw

PATCH v2 4/8 ARM: shmobile: genmai: Add RSPI children

In reply to Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

On this board, only rspi4 is in use. Its bus contains a single device (a wm8978 audio codec).

As the RSPI driver itself doesn't use DT yet, we have to instantiate the SPI child device in C code, too, for both genmai and genmai-reference.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
New in v2

 arch/arm/mach-shmobile/board-genmai-reference.c |   11 +++++++++++
 arch/arm/mach-shmobile/board-genmai.c           |   11 +++++++++++
 2 files changed, 22 insertions(+)
arch/arm/mach-shmobile/board-genmai-reference.c +11 -0
index 7630c1053e32..2f8094b3add2 100644
@@ -21,11 +21,21 @@
 #include <linux/clk-provider.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/spi/spi.h>
 #include <mach/common.h>
 #include <mach/r7s72100.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+static const struct spi_board_info spi_info[] __initconst = {
+	{
+		.modalias               = "wm8978",
+		.max_speed_hz           = 5000000,
+		.bus_num                = 4,
+		.chip_select            = 0,
+	},
+};
+
 static void __init genmai_add_standard_devices(void)
 {
 #ifdef CONFIG_COMMON_CLK

@@ -34,6 +44,7 @@ static void __init genmai_add_standard_devices(void)
 	r7s72100_clock_init();
 #endif
 	r7s72100_add_dt_devices();
+	spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
arch/arm/mach-shmobile/board-genmai.c +11 -0
index a1f6fe1fb06f..7c912d337828 100644
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/sh_eth.h>
+#include <linux/spi/spi.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r7s72100.h>

@@ -41,11 +42,21 @@ static const struct resource ether_resources[] __initconst = {
 	DEFINE_RES_IRQ(gic_iid(359)),
 };
 
+static const struct spi_board_info spi_info[] __initconst = {
+	{
+		.modalias               = "wm8978",
+		.max_speed_hz           = 5000000,
+		.bus_num                = 4,
+		.chip_select            = 0,
+	},
+};
+
 static void __init genmai_add_standard_devices(void)
 {
 	r7s72100_clock_init();
 	r7s72100_add_dt_devices();
 
+	spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
 	platform_device_register_resndata(&platform_bus, "r7s72100-ether", -1,
 					  ether_resources,
 					  ARRAY_SIZE(ether_resources),
Signature · 1 line
1.7.9.5
author
#5 lore raw

RFC PATCH v2 5/8 ARM: shmobile: genmai: Add preliminary RSPI pinmux setup

In reply to Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

This does not work as there's no pinmux configuration in setup-r7s72100.c yet.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
New in v2

 arch/arm/mach-shmobile/board-genmai.c |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)
arch/arm/mach-shmobile/board-genmai.c +17 -0
index 7c912d337828..d89d87ac1c6f 100644
@@ -19,6 +19,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/sh_eth.h>
 #include <linux/spi/spi.h>

@@ -51,9 +52,25 @@ static const struct spi_board_info spi_info[] __initconst = {
 	},
 };
 
+static const struct pinctrl_map genmai_pinctrl_map[] = {
+	/* RSPI4 */
+	PIN_MAP_MUX_GROUP_DEFAULT("rspi.4", "pfc-r7s72100",
+				  "rspi4_rspck_p4_0", "rspi4"),
+	PIN_MAP_MUX_GROUP_DEFAULT("rspi.4", "pfc-r7s72100",
+				  "rspi4_ssl0_p4_1", "rspi4"),
+	PIN_MAP_MUX_GROUP_DEFAULT("rspi.4", "pfc-r7s72100",
+				  "rspi4_mosi_p4_2", "rspi4"),
+	PIN_MAP_MUX_GROUP_DEFAULT("rspi.4", "pfc-r7s72100",
+				  "rspi4_miso_p4_3", "rspi4"),
+};
+
 static void __init genmai_add_standard_devices(void)
 {
 	r7s72100_clock_init();
+	pinctrl_register_mappings(genmai_pinctrl_map,
+				  ARRAY_SIZE(genmai_pinctrl_map));
+	/* FIXME there's no pinmux configuration in setup-r7s72100.c yet */
+	/* r7s72100_pinmux_init(); */
 	r7s72100_add_dt_devices();
 
 	spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
Signature · 1 line
1.7.9.5
author
#6 lore raw

RFC PATCH v2 6/8 Documentation: dt: Add Renesas RSPI/QSPI bindings

In reply to Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

Signed-off-by Geert Uytterhoeven <[email protected]>
Cc devicetree at vger.kernel.org

---
v2:
- Clarify RSPI/QSPI
- Add interrupt-parent
- s/should/must/ for #address-cells and #size-cells

 Documentation/devicetree/bindings/spi/spi-rspi.txt |   31 ++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-rspi.txt
Documentation/devicetree/bindings/spi/spi-rspi.txt new file +31 -0
new file mode 100644
index 000000000000..504db8917927
@@ -0,0 +1,31 @@
+Device tree configuration for Renesas RSPI/QSPI driver
+
+Required properties:
+- compatible       : For Renesas Serial Peripheral Interface:
+                     "renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
+		     For Quad Serial Peripheral Interface:
+		     "renesas,qspi-<soctype>", "renesas,qspi-rcar" as fallback.
+- reg              : address start and address range size of device
+- interrupts       : 3 interrupts for RSPI (SPEI, SPRI, SPTI),
+		     1 interrupt for QSPI
+- interrupt-parent : the phandle for the interrupt controller that
+		     services interrupts for this device.
+- num-cs	   : Number of chip selects
+- #address-cells   : must be <1>
+- #size-cells      : must be <0>
+
+Pinctrl properties might be needed, too. See there.
+
+Example:
+
+	spi0: spi at e800c800 {
+		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+		reg = <0xe800c800 0x24>;
+		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 239 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 240 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
Signature · 1 line
1.7.9.5
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#7 lore raw

RFC PATCH v2 6/8 Documentation: dt: Add Renesas RSPI/QSPI bindings

Quoted 4 lines · Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

Signed-off-by Geert Uytterhoeven <[email protected]>
Cc devicetree at vger.kernel.org

You've not CCed any maintainers on any of this stuff so I'm assuming you don't want any review or the patches applying. You should in general always CC maintainers, things that only go to the list can easily be missed. However I did take a brief look...

Quoted 1 line

+- num-cs : Number of chip selects

Why is this variable and how does this map onto hardware?
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#8 lore raw

RFC PATCH v2 6/8 Documentation: dt: Add Renesas RSPI/QSPI bindings

Quoted 8 lines · Mark Brown
Quoted 4 lines · Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

Signed-off-by Geert Uytterhoeven <[email protected]>
Cc devicetree at vger.kernel.org

You've not CCed any maintainers on any of this stuff so I'm assuming you don't want any review or the patches applying. You should in general

Sorry, this was indeed not meant to be applied yet, hence the [RFC]. Will CC you explicitly next time.

Quoted 2 lines

always CC maintainers, things that only go to the list can easily be missed. However I did take a brief look...

Thanks!

Quoted 3 lines
Quoted 1 line

+- num-cs : Number of chip selects

Why is this variable and how does this map onto hardware?

It's my understanding that legacy RSPi on SH7757 has 2 chip selects, while other RSPI implementations have 1 chip select.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

maintainer
#9 lore raw

RFC PATCH v2 6/8 Documentation: dt: Add Renesas RSPI/QSPI bindings

Quoted 9 lines · Geert Uytterhoeven
Quoted 5 lines · Mark Brown
Quoted 1 line · Geert Uytterhoeven

+- num-cs : Number of chip selects

Why is this variable and how does this map onto hardware?

It's my understanding that legacy RSPi on SH7757 has 2 chip selects, while other RSPI implementations have 1 chip select.

So this should be documented in the binding document in a way that
allows someone reading the document and looking at the datasheet to
figure out how to pick the value (for example, refer to how the chip
selects are controlled in the hardware).
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author
#10 lore raw

RFC PATCH v2 7/8 ARM: shmobile: r7s72100 dtsi: Add RSPI nodes

In reply to Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

Signed-off-by Geert Uytterhoeven <[email protected]>
Cc devicetree at vger.kernel.org

---
v2: No changes

 arch/arm/boot/dts/r7s72100.dtsi |   65 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
arch/arm/boot/dts/r7s72100.dtsi +65 -0
index ff0bd6be454f..42e9b423476c 100644
@@ -34,6 +34,11 @@
 		gpio10 = &port10;
 		gpio11 = &port11;
 		gpio12 = &jtagport0;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+		spi4 = &spi4;
 	};
 
 	cpus {

@@ -289,4 +294,64 @@
 		clock-frequency = <100000>;
 		status = "disabled";
 	};
+
+	spi0: spi at e800c800 {
+		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+		reg = <0xe800c800 0x24>;
+		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 239 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 240 IRQ_TYPE_LEVEL_HIGH>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi1: spi at e800d000 {
+		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+		reg = <0xe800d000 0x24>;
+		interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 242 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 243 IRQ_TYPE_LEVEL_HIGH>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi2: spi at e800d800 {
+		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+		reg = <0xe800d800 0x24>;
+		interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 245 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 246 IRQ_TYPE_LEVEL_HIGH>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi3: spi at e800e000 {
+		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+		reg = <0xe800e000 0x24>;
+		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 248 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 249 IRQ_TYPE_LEVEL_HIGH>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi4: spi at e800e800 {
+		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+		reg = <0xe800e800 0x24>;
+		interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 251 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 252 IRQ_TYPE_LEVEL_HIGH>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
Signature · 1 line
1.7.9.5
author
#11 lore raw

RFC PATCH v2 8/8 ARM: shmobile: genmai reference: Add RSPI nodes

In reply to Geert Uytterhoeven

From: Geert Uytterhoeven <[email protected]>

Add pinctrl and SPI devices for RSPI on Genmai.

On this board, only rspi4 is in use. Its bus contains a single device (a wm8978 audio codec), for which no bindings are defined yet.

Signed-off-by Geert Uytterhoeven <[email protected]>
Cc devicetree at vger.kernel.org

---
v2: Use generic "codec" instead of specific "wm8978" node name.

 arch/arm/boot/dts/r7s72100-genmai-reference.dts |   18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)
arch/arm/boot/dts/r7s72100-genmai-reference.dts +17 -1
index 367af5c133e0..c2cc4bd5a470 100644
@@ -43,7 +43,7 @@
 };
 
 &pfc {
-	pinctrl-0 = <&scif2_pins &ethernet_pins>;
+	pinctrl-0 = <&scif2_pins &ethernet_pins &rspi4_pins>;
 	pinctrl-names = "default";
 
 	scif2_pins: serial2 {

@@ -73,6 +73,12 @@
 				 "ethernet_int_p1_15";
 		renesas,function = "ethernet";
 	};
+
+	rspi4_pins: spi4 {
+		renesas,groups = "rspi4_rspck_p4_0", "rspi4_ssl0_p4_1",
+				 "rspi4_mosi_p4_2", "rspi4_miso_p4_3";
+		renesas,function = "rspi4";
+	};
 };
 
 &i2c2 {

@@ -85,3 +91,13 @@
 		pagesize = <64>;
 	};
 };
+
+&spi4 {
+	status = "okay";
+
+	codec: codec at 0 {
+		compatible = "wlf,wm8978";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+	};
+};
Signature · 1 line
1.7.9.5
#12 lore raw

v2 cover SoC and board integration for RSPI on RZ/A1H

In reply to Geert Uytterhoeven
Quoted 20 lines · Geert Uytterhoeven

This patch series integrates Renesas RSPI on the RZ/A1H aka R7S72100 SoC, and the Genmai development board.

The series is based on renesas-devel-v3.13-rc5-20131226, with Magnus' pinctrl, Wolfram's riic, and Simon's sh_eth work applied on top.

It was tested on the Genmai development board (genmai-reference), using an in-kernel version of Documentation/spi/spidev_test.c, exercising loopback mode on rspi1, with the same outcome as the SDK reference code.

Notes:
1. The proposed DT bindings also talk about QSPI on the R8A779x, as those SoCs use the same driver.
2. As the actual spi-rspi driver doesn't use DT yet, platform devices and spi board info are still used from C to instantiate SPI buses and their children, while pinctrl is performed by DT.
3. It will not work with the non-reference version of genmai, due to missing pinmux configuration in setup-r7s72100.c.
4. Patches [4/8] and [5/8] are new.

Quoted 1 line
    [1/8] pinctrl: sh-pfc: r7s72100: Add RSPI support

I believe that Laurent should handle this.

Quoted 1 line
    [2/8] ARM: shmobile: r7s72100: Add RSPI clocks

This seems fine and independent of the other patches. But unfortunately it no longer applies.

Feel free to rebase it if you would like me to queue it up sooner than later.

Quoted 1 line

[3/8] ARM: shmobile: r7s72100: Add RSPI platform devices

I assume this depends on 1/3.

Please add a patch to update the koelsch defconfig.

Quoted 1 line

[4/8] ARM: shmobile: genmai: Add RSPI children (NEW)

This seems reasonable but I assume it depends on earlier patches.

Please add a patch to update the koelsch defconfig or Kconfig.

Quoted 20 lines

[5/8] [RFC] ARM: shmobile: genmai: Add preliminary RSPI pinmux (NEW) [6/8] [RFC] Documentation: dt: Add Renesas RSPI/QSPI bindings [7/8] [RFC] ARM: shmobile: r7s72100 dtsi: Add RSPI nodes [8/8] [RFC] ARM: shmobile: genmai reference: Add RSPI nodes

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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author
#13 lore raw

v2 cover SoC and board integration for RSPI on RZ/A1H

Quoted 3 lines · Simon Horman
Quoted 1 line
    [1/8] pinctrl: sh-pfc: r7s72100: Add RSPI support

I believe that Laurent should handle this.

Don't you mean Magnus? This is RZ/A1H, not R-Car.

Quoted 7 lines
Quoted 1 line
    [2/8] ARM: shmobile: r7s72100: Add RSPI clocks

This seems fine and independent of the other patches. But unfortunately it no longer applies.

Feel free to rebase it if you would like me to queue it up sooner than later.

Will do.

Quoted 3 lines
Quoted 1 line

[3/8] ARM: shmobile: r7s72100: Add RSPI platform devices

I assume this depends on 1/3.

1/8? Or are you mixing up with 1/3 for Koelsch?

Nevertheless, this just adds platform devices, so it should be fairly independent.

Quoted 1 line

Please add a patch to update the koelsch defconfig.

Genmai defconfig, not koelsch.

Quoted 3 lines
Quoted 1 line

[4/8] ARM: shmobile: genmai: Add RSPI children (NEW)

This seems reasonable but I assume it depends on earlier patches.

Yes, it's useless without 3/8. But I guess it will just fail to find the SPI bus.

Quoted 1 line

Please add a patch to update the koelsch defconfig or Kconfig.

Genmai ;-) Will do.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#14 lore raw

v2 cover SoC and board integration for RSPI on RZ/A1H

Quoted 15 lines · Geert Uytterhoeven
Quoted 3 lines · Simon Horman
Quoted 1 line
    [1/8] pinctrl: sh-pfc: r7s72100: Add RSPI support

I believe that Laurent should handle this.

Don't you mean Magnus? This is RZ/A1H, not R-Car.

Quoted 7 lines
Quoted 1 line
    [2/8] ARM: shmobile: r7s72100: Add RSPI clocks

This seems fine and independent of the other patches. But unfortunately it no longer applies.

Feel free to rebase it if you would like me to queue it up sooner than later.

Quoted 7 lines

Will do.

Quoted 3 lines
Quoted 1 line

[3/8] ARM: shmobile: r7s72100: Add RSPI platform devices

I assume this depends on 1/3.

1/8? Or are you mixing up with 1/3 for Koelsch?

1/8

Quoted 2 lines

Nevertheless, this just adds platform devices, so it should be fairly independent.

Ok, thanks. It sounds like I will be able to queue it up once you repost the series.

Quoted 11 lines
Quoted 2 lines

Please add a patch to update the koelsch defconfig.

Genmai defconfig, not koelsch.

Quoted 3 lines
Quoted 1 line

[4/8] ARM: shmobile: genmai: Add RSPI children (NEW)

This seems reasonable but I assume it depends on earlier patches.

Yes, it's useless without 3/8. But I guess it will just fail to find the SPI bus.

Useless is ok. Its just breakage that I'm concerned about these days :^)

Quoted 3 lines
Quoted 1 line

Please add a patch to update the koelsch defconfig or Kconfig.

Genmai ;-) Will do.

Yes, Genmai :)

#15 lore raw

v2 cover SoC and board integration for RSPI on RZ/A1H

In reply to Simon Horman

Hi Simon,

Quoted 19 lines · On Tuesday 07 January 2014 10:26:28 Simon Horman wrote:
Quoted 18 lines · Geert Uytterhoeven

This patch series integrates Renesas RSPI on the RZ/A1H aka R7S72100 SoC, and the Genmai development board.

The series is based on renesas-devel-v3.13-rc5-20131226, with Magnus' pinctrl, Wolfram's riic, and Simon's sh_eth work applied on top.

It was tested on the Genmai development board (genmai-reference), using an in-kernel version of Documentation/spi/spidev_test.c, exercising loopback mode on rspi1, with the same outcome as the SDK reference code.

Notes:
1. The proposed DT bindings also talk about QSPI on the R8A779x, as those SoCs use the same driver.

2. As the actual spi-rspi driver doesn't use DT yet, platform devices and spi board info are still used from C to instantiate SPI buses and their children, while pinctrl is performed by DT.

Quoted 8 lines
Quoted 6 lines

3. It will not work with the non-reference version of genmai, due to missing pinmux configuration in setup-r7s72100.c.

4. Patches [4/8] and [5/8] are new.

    [1/8] pinctrl: sh-pfc: r7s72100: Add RSPI support

I believe that Laurent should handle this.

I will, but I'm waiting for Magnus to resubmit the base r7s72100 pinctrl patch series.

Quoted 24 lines
Quoted 1 line
    [2/8] ARM: shmobile: r7s72100: Add RSPI clocks

This seems fine and independent of the other patches. But unfortunately it no longer applies.

Feel free to rebase it if you would like me to queue it up sooner than later.

Quoted 1 line

[3/8] ARM: shmobile: r7s72100: Add RSPI platform devices

I assume this depends on 1/3.

Please add a patch to update the koelsch defconfig.

Quoted 1 line

[4/8] ARM: shmobile: genmai: Add RSPI children (NEW)

This seems reasonable but I assume it depends on earlier patches.

Please add a patch to update the koelsch defconfig or Kconfig.

Quoted 4 lines

[5/8] [RFC] ARM: shmobile: genmai: Add preliminary RSPI pinmux (NEW) [6/8] [RFC] Documentation: dt: Add Renesas RSPI/QSPI bindings [7/8] [RFC] ARM: shmobile: r7s72100 dtsi: Add RSPI nodes [8/8] [RFC] ARM: shmobile: genmai reference: Add RSPI nodes

Signature · 3 lines
Regards,

Laurent Pinchart
#16 lore raw

v2 cover SoC and board integration for RSPI on RZ/A1H

Quoted 25 lines · Laurent Pinchart

Hi Simon,

Quoted 22 lines · On Tuesday 07 January 2014 10:26:28 Simon Horman wrote:
Quoted 21 lines · Geert Uytterhoeven

This patch series integrates Renesas RSPI on the RZ/A1H aka R7S72100 SoC, and the Genmai development board.

The series is based on renesas-devel-v3.13-rc5-20131226, with Magnus' pinctrl, Wolfram's riic, and Simon's sh_eth work applied on top.

It was tested on the Genmai development board (genmai-reference), using an in-kernel version of Documentation/spi/spidev_test.c, exercising loopback mode on rspi1, with the same outcome as the SDK reference code.

Notes:
1. The proposed DT bindings also talk about QSPI on the R8A779x, as those SoCs use the same driver.

2. As the actual spi-rspi driver doesn't use DT yet, platform devices and spi board info are still used from C to instantiate SPI buses and their children, while pinctrl is performed by DT.

3. It will not work with the non-reference version of genmai, due to missing pinmux configuration in setup-r7s72100.c.

Quoted 8 lines
Quoted 5 lines
Quoted 3 lines

4. Patches [4/8] and [5/8] are new.

    [1/8] pinctrl: sh-pfc: r7s72100: Add RSPI support

I believe that Laurent should handle this.

I will, but I'm waiting for Magnus to resubmit the base r7s72100 pinctrl patch series.

Got it.

Quoted 35 lines
Quoted 24 lines
Quoted 1 line
    [2/8] ARM: shmobile: r7s72100: Add RSPI clocks

This seems fine and independent of the other patches. But unfortunately it no longer applies.

Feel free to rebase it if you would like me to queue it up sooner than later.

Quoted 1 line

[3/8] ARM: shmobile: r7s72100: Add RSPI platform devices

I assume this depends on 1/3.

Please add a patch to update the koelsch defconfig.

Quoted 1 line

[4/8] ARM: shmobile: genmai: Add RSPI children (NEW)

This seems reasonable but I assume it depends on earlier patches.

Please add a patch to update the koelsch defconfig or Kconfig.

Quoted 4 lines

[5/8] [RFC] ARM: shmobile: genmai: Add preliminary RSPI pinmux (NEW) [6/8] [RFC] Documentation: dt: Add Renesas RSPI/QSPI bindings [7/8] [RFC] ARM: shmobile: r7s72100 dtsi: Add RSPI nodes [8/8] [RFC] ARM: shmobile: genmai reference: Add RSPI nodes

Signature · 8 lines
Regards,

Laurent Pinchart

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