powerpc/serdes: Add the workaround for erratum A-007186
PATCH 1/1 powerpc/serdes: Add the workaround for erratum A-007186
SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock.
This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.
This workaround is valid for B4, T4 and T2 platforms, so added in their config.
Signed-off-by Shaveta Leekha <[email protected]>
Signed-off-by Poonam Aggrwal <[email protected]>
--- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 147 ++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 6 + arch/powerpc/include/asm/immap_85xx.h | 33 +++++- 4 files changed, 187 insertions(+), 2 deletions(-)
arch/powerpc/cpu/mpc85xx/cmd_errata.c +3 -0
@@ -266,6 +266,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])#ifdef CONFIG_SYS_FSL_ERRATUM_USB14 puts ("Work-around for Erratum USB14 enabled\n" );#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +puts ("Work-around for Erratum A007186 enabled\n" ); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts ("Work-around for Erratum A006593 enabled\n" );#endif
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +147 -0
165 lines not on this page · raw message
arch/powerpc/include/asm/config_mpc85xx.h +6 -0
@@ -657,8 +657,10 @@#define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_PPC_B4860 ) || defined(CONFIG_PPC_B4420 )
@@ -684,12 +686,14 @@#define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
@@ -809,8 +813,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_PPC_C29X )
arch/powerpc/include/asm/immap_85xx.h +31 -2
@@ -2521,14 +2521,17 @@ typedef struct serdes_corenet {#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_PLL_LCK 0x00800000#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 -#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 -#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 +#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000 +#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4u32 pllcr1;/* PLL Control Register 1 */
@@ -2863,6 +2866,21 @@ struct ccsr_pman { u8 res_f4[0xf0c]; };#endif +#ifdef CONFIG_SYS_FSL_SFP_VER_3_0 +typedef struct ccsr_sfp_regs { +u32 ospr;/* 0x200 */ +u32 reserved0[14 ]; +u32 srk_hash[8 ];/* 0x23c Super Root Key Hash */ +u32 oem_uid;/* 0x9c OEM Unique ID */ +u8 reserved2[0x04 ]; +u32 ovpr;/* 0xA4 Intent To Secure */ +u8 reserved4[0x08 ]; +u32 fsl_uid;/* 0xB0 FSL Unique ID */ +u8 reserved5[0x04 ]; +u32 fsl_spfr0;/* Scratch Pad Fuse Register 0 */ +u32 fsl_spfr1;/* Scratch Pad Fuse Register 1 */ +}ccsr_sfp_regs_t ; +#endif #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
@@ -2876,6 +2894,14 @@ struct ccsr_pman {#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#ifdef CONFIG_SYS_FSL_SFP_VER_3_0 +/* In SFPv3, OSPR register is now at offset 0x200. +* * So directly mapping sfp register map to this address */ +#define CONFIG_SYS_OSPR_OFFSET 0x200 +#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) +#else +#define CONFIG_SYS_SFP_OFFSET 0xE8000 +#endif #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
@@ -3094,6 +3120,9 @@ struct ccsr_pman {#define CONFIG_SYS_PCIE4_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) +#define CONFIG_SYS_SFP_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
Signature · 1 line
1.7.6.GIT
PATCH 1/1 powerpc/serdes: Add the workaround for erratum A-007186
Quoted 8 lines · Shaveta Leekha
SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock.
This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.
Quoted 6 lines
This workaround is valid for B4, T4 and T2 platforms, so added in their config.
Signed-off-by Shaveta Leekha <[email protected]>Signed-off-by Poonam Aggrwal <[email protected]>---
Applied to u-boot-mpc85xx. Sorry for the late notice.
York