Add support for TQMa6 modules

186 lines not on this page · raw message

new file mode 100644
index 0000000..9d072d2
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2013, 2014 TQ Systems
+ * Author: Markus Niebel <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TQMA6_BB__
+#define __TQMA6_BB
+
+#include <common.h>
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
+int tqma6_bb_board_mmc_init(bd_t *bis);
+
+int tqma6_bb_board_early_init_f(void);
+int tqma6_bb_board_init(void);
+int tqma6_bb_board_late_init(void);
+int tqma6_bb_checkboard(void);
+
+const char *tqma6_bb_get_boardname(void);
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, bd_t *bd);
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+#endif

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index 8679db8..c30f379 100644
@@ -20,7 +20,11 @@
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <libfdt.h>
+#include <malloc.h>
+#include <micrel.h>
+#include <miiphy.h>
 #include <mmc.h>
+#include <netdev.h>
 
 #include "tqma6_bb.h"
 

@@ -41,6 +45,87 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#if defined(CONFIG_MX6Q)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0790
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e07ac
+
+#elif defined(CONFIG_MX6S)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0768
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e0788
+
+#else
+
+#error "need to define target CPU"
+
+#endif
+
+#define ENET_RX_PAD_CTRL	(PAD_CTL_DSE_34ohm)
+#define ENET_TX_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
+#define ENET_CLK_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+				 PAD_CTL_DSE_34ohm)
+#define ENET_MDIO_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+				 PAD_CTL_DSE_60ohm)
+
+/* disable on die termination for RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE	0x00000000
+/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V	0x00080000
+/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V	0x000C0000
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
+
+static iomux_v3_cfg_t const mba6_enet_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO,		ENET_MDIO_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC,		ENET_MDIO_PAD_CTRL),
+
+	NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC,		ENET_TX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0,		ENET_TX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1,		ENET_TX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2,		ENET_TX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3,		ENET_TX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,	ENET_TX_PAD_CTRL),
+
+	NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK,		ENET_CLK_PAD_CTRL),
+	/*
+	 * these pins are also used for config strapping by phy
+	 */
+	NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0,		ENET_RX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1,		ENET_RX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2,		ENET_RX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3,		ENET_RX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC,		ENET_RX_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,	ENET_RX_PAD_CTRL),
+	/* KSZ9031 PHY Reset */
+	NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25,		GPIO_OUT_PAD_CTRL),
+};
+
+static void mba6_setup_iomuxc_enet(void)
+{
+	__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
+		     (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
+	__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
+		     (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
+
+	imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
+					 ARRAY_SIZE(mba6_enet_pads));
+
+	/* Reset PHY */
+	gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+	/* Need delay 10ms after power on according to KSZ9031 spec */
+	udelay(1000 * 10);
+	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+	/*
+	 * KSZ9031 manual: 100 usec wait time after reset before communication
+	 * over MDIO
+	 * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
+	 * reset before the phy sees a high level
+	 */
+	udelay(200);
+}
+
 static iomux_v3_cfg_t const mba6_uart2_pads[] = {
 	NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
 	NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),

@@ -115,6 +200,76 @@ int tqma6_bb_board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+int board_phy_config(struct phy_device *phydev)
+{
+#if defined(CONFIG_MX6Q)
+#define MBA6X_KSZ9031_CTRL_SKEW	0x0032
+#define MBA6X_KSZ9031_CLK_SKEW	0x03ff
+#define MBA6X_KSZ9031_RX_SKEW	0x3333
+#define MBA6X_KSZ9031_TX_SKEW	0x2036
+#elif defined(CONFIG_MX6S)
+#define MBA6X_KSZ9031_CTRL_SKEW	0x0030
+#define MBA6X_KSZ9031_CLK_SKEW	0x03ff
+#define MBA6X_KSZ9031_RX_SKEW	0x3333
+#define MBA6X_KSZ9031_TX_SKEW	0x2052
+#else
+#error
+#endif
+	/* min rx/tx ctrl delay */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_CTRL_SKEW);
+	/* min rx delay */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_RX_SKEW);
+	/* max tx delay */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_TX_SKEW);
+	/* rx/tx clk skew */
+	ksz9031_phy_extended_write(phydev, 2,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   MBA6X_KSZ9031_CLK_SKEW);
+
+	phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return 0;
+	/* scan phy */
+	phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
+					PHY_INTERFACE_MODE_RGMII);
+
+	if (!phydev) {
+		free(bus);
+		printf("No phy found\n");
+		return 0;
+	}
+	ret  = fec_probe(bis, -1, base, bus, phydev);
+	if (ret) {
+		printf("FEC MXC: %s:failed\n", __func__);
+		free(phydev);
+		free(bus);
+	}
+
+	return 0;
+}
+
 int tqma6_bb_board_early_init_f(void)
 {
 	mba6_setup_iomuxc_uart();

@@ -124,6 +279,9 @@ int tqma6_bb_board_early_init_f(void)
 
 int tqma6_bb_board_init(void)
 {
+	/* do it here - to have reset completed */
+	mba6_setup_iomuxc_enet();
+
 	return 0;
 }
 

114 lines not on this page · raw message

index 66fbc06..7c737d1 100644
@@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

@@ -118,6 +121,28 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
+	/* SS1 */
+	NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+};
+
+static unsigned const tqma6_ecspi1_cs[] = {
+	IMX_GPIO_NR(3, 19),
+};
+
+static void tqma6_iomuxc_spi(void)
+{
+	unsigned i;
+
+	for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
+		gpio_direction_output(tqma6_ecspi1_cs[i], 1);
+	imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
+					 ARRAY_SIZE(tqma6_ecspi1_pads));
+}
+
 int board_early_init_f(void)
 {
 	return tqma6_bb_board_early_init_f();

@@ -128,6 +153,8 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	tqma6_iomuxc_spi();
+
 	tqma6_bb_board_init();
 
 	return 0;

index c30f379..94df68f 100644
@@ -45,6 +45,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
 #if defined(CONFIG_MX6Q)
 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0790

@@ -200,6 +203,26 @@ int tqma6_bb_board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
+	NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
+	NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
+};
+
+static unsigned const mba6_ecspi1_cs[] = {
+	IMX_GPIO_NR(3, 24),
+	IMX_GPIO_NR(3, 25),
+};
+
+static void mba6_setup_iomuxc_spi(void)
+{
+	unsigned i;
+
+	for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
+		gpio_direction_output(mba6_ecspi1_cs[i], 1);
+	imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
+					 ARRAY_SIZE(mba6_ecspi1_pads));
+}
+
 int board_phy_config(struct phy_device *phydev)
 {
 #if defined(CONFIG_MX6Q)

@@ -279,6 +302,7 @@ int tqma6_bb_board_early_init_f(void)
 
 int tqma6_bb_board_init(void)
 {
+	mba6_setup_iomuxc_spi();
 	/* do it here - to have reset completed */
 	mba6_setup_iomuxc_enet();
 

index 055675e..2c5016d 100644
@@ -47,6 +47,20 @@
 #define CONFIG_MXC_GPIO
 #define CONFIG_MXC_UART
 
+/* SPI */
+#define CONFIG_CMD_SPI
+#define CONFIG_MXC_SPI
+
+/* SPI Flash */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_BUS	0
+#define CONFIG_SF_DEFAULT_CS	(0 | (IMX_GPIO_NR(3, 19) << 8))
+#define CONFIG_SF_DEFAULT_SPEED	50000000
+#define CONFIG_SF_DEFAULT_MODE	(SPI_MODE_0)
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC

109 lines not on this page · raw message

index 94df68f..4082e05 100644
@@ -293,6 +293,13 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+#endif
+
 int tqma6_bb_board_early_init_f(void)
 {
 	mba6_setup_iomuxc_uart();

index d2b12c3..115f45a 100644
@@ -71,6 +71,17 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
 /* Fuses */
 #define CONFIG_MXC_OCOTP
 #define CONFIG_CMD_FUSE

index 7c737d1..556a70d 100644
@@ -16,9 +16,11 @@
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <libfdt.h>
+#include <i2c.h>
 #include <mmc.h>
 
 #include "tqma6_bb.h"

@@ -40,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

@@ -143,6 +149,26 @@ static void tqma6_iomuxc_spi(void)
 					 ARRAY_SIZE(tqma6_ecspi1_pads));
 }
 
+static struct i2c_pads_info tqma6_i2c3_pads = {
+	/* I2C3: on board LM75, M24C64,  */
+	.scl = {
+		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL, I2C_PAD_CTRL),
+		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05, I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
+		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+static void tqma6_setup_i2c(void)
+{
+	/* use logical index for bus, e.g. I2C1 -> 0 */
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
+}
+
 int board_early_init_f(void)
 {
 	return tqma6_bb_board_early_init_f();

@@ -154,6 +180,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 	tqma6_iomuxc_spi();
+	tqma6_setup_i2c();
 
 	tqma6_bb_board_init();
 

index 4082e05..276ffe5 100644
@@ -16,11 +16,13 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
 
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <libfdt.h>
 #include <malloc.h>
+#include <i2c.h>
 #include <micrel.h>
 #include <miiphy.h>
 #include <mmc.h>

@@ -48,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 #if defined(CONFIG_MX6Q)
 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0790

@@ -203,6 +209,27 @@ int tqma6_bb_board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+static struct i2c_pads_info mba6_i2c1_pads = {
+/* I2C1: MBa6x */
+	.scl = {
+		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27, I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26, I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(5, 26)
+	}
+};
+
+static void mba6_setup_i2c(void)
+{
+	/* use logical index for bus, e.g. I2C1 -> 0 */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
+}
+
+
 static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
 	NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
 	NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),

@@ -293,13 +320,6 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#ifdef CONFIG_USB_EHCI_MX6
-int board_ehci_hcd_init(int port)
-{
-	return 0;
-}
-#endif
-
 int tqma6_bb_board_early_init_f(void)
 {
 	mba6_setup_iomuxc_uart();

@@ -309,6 +329,7 @@ int tqma6_bb_board_early_init_f(void)
 
 int tqma6_bb_board_init(void)
 {
+	mba6_setup_i2c();
 	mba6_setup_iomuxc_spi();
 	/* do it here - to have reset completed */
 	mba6_setup_iomuxc_enet();

index 115f45a..df7395d 100644
@@ -61,6 +61,33 @@
 #define CONFIG_SF_DEFAULT_SPEED	50000000
 #define CONFIG_SF_DEFAULT_MODE	(SPI_MODE_0)
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_I2C_MULTI_BUS
+/* #define CONFIG_I2C_MXC */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75
+#if defined(CONFIG_MBA6)
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+#else
+#define CONFIG_DTT_SENSORS		{ 0 }
+#endif
+#define CONFIG_DTT_MAX_TEMP		70
+#define CONFIG_DTT_MIN_TEMP		-30
+#define CONFIG_DTT_HYSTERESIS	3
+#define CONFIG_CMD_DTT
+
+/* I2C EEPROM (M24C64) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR			0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN			2
+#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS		5 /* 32 Bytes */
+#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_CMD_EEPROM
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC

index 556a70d..ba8ff07 100644
@@ -22,6 +22,8 @@
 #include <libfdt.h>
 #include <i2c.h>
 #include <mmc.h>
+#include <power/pfuze100_pmic.h>
+#include <power/pmic.h>
 
 #include "tqma6_bb.h"
 

@@ -169,6 +171,22 @@ static void tqma6_setup_i2c(void)
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
 }
 
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+	u32 reg;
+
+	/* configure PFUZE100 PMIC */
+	power_pfuze100_init(2);
+	p = pmic_get("PFUZE100_PMIC");
+	if (p && !pmic_probe(p)) {
+		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+		printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+	}
+	return 0;
+}
+
 int board_early_init_f(void)
 {
 	return tqma6_bb_board_early_init_f();

index df7395d..b33a9fb 100644
@@ -88,6 +88,11 @@
 #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS	20
 #define CONFIG_CMD_EEPROM
 
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC