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ARM: tegra: Disable VPR

PATCH Superseded Alexandre Courbot 2 participants 5 messages Jun 19, 2014 – Jun 24, 2014

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v1 of 3 Superseded Latest is v3 →

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PATCH 1/1 ARM: tegra: Disable VPR

From: Bryan Wu <[email protected]>

On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project.

[acourbot: ensure write went through, vpr.c style changes]
Cc Tom Warren <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Terje Bergstrom <[email protected]>
---
 arch/arm/cpu/tegra-common/Makefile   |  1 +
 arch/arm/cpu/tegra-common/ap.c       |  3 +++
 arch/arm/cpu/tegra-common/vpr.c      | 43 ++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra/ap.h |  3 +++
 arch/arm/include/asm/arch-tegra/mc.h | 45 ++++++++++++++++++++++++++++++++++++
 5 files changed, 95 insertions(+)
 create mode 100644 arch/arm/cpu/tegra-common/vpr.c
 create mode 100644 arch/arm/include/asm/arch-tegra/mc.h
arch/arm/cpu/tegra-common/Makefile +1 -0
index 892556e64451..5c541bef557e 100644
@@ -14,3 +14,4 @@ obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-y += vpr.o
arch/arm/cpu/tegra-common/ap.c +3 -0
index 91d70da65661..a17dfd1e225e 100644
@@ -163,4 +163,7 @@ void s_init(void)
 
 	/* init the cache */
 	config_cache();
+
+	/* init vpr */
+	config_vpr();
 }
arch/arm/cpu/tegra-common/vpr.c new file +43 -0

43 lines not on this page · raw message

arch/arm/include/asm/arch-tegra/ap.h +3 -0
index bc5851c1d045..908407aeded0 100644
@@ -65,3 +65,6 @@ int tegra_get_sku_info(void);
 
 /* Do any chip-specific cache config */
 void config_cache(void);
+
+/* Do chip-specific vpr config */
+void config_vpr(void);
arch/arm/include/asm/arch-tegra/mc.h new file +45 -0

45 lines not on this page · raw message

Signature · 1 line
2.0.0
#1 lore raw

PATCH 1/1 ARM: tegra: Disable VPR

Quoted 8 lines · Alexandre Courbot

From: Bryan Wu <[email protected]>

On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed.

arch/arm/cpu/tegra-common/vpr.c line 36

Quoted 6 lines
arch/arm/cpu/tegra-common/vpr.c +4 -0
 
+void config_vpr(void)
 
+		/* Turn off VPR */
+		writel(0x00000000, &mc->mc_video_protect_size_mb);
+		writel(0x00000001, &mc->mc_video_protect_reg_ctrl);

Can we use a #define rather than "1" there, so we know what the bit means. Also "0" is as good as "0x00000000" and same for "1".

arch/arm/include/asm/arch-tegra/mc.h line 25

Quoted 8 lines
arch/arm/include/asm/arch-tegra/mc.h +6 -0
 
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */

...

Is this entire layout valid for Tegra20/30 too, and identical for Tegra114/124? If not, I'd prefer that we:

- Define the structure in arch/arm/include/asm/arch-tegraNNN/mc.h, so it's obvious that it's not identical on all SoCs (or if the differences are small, then ifdef the fields in the struct without moving the file to avoid duplicating the identical parts).

- ifdef out the body of config_vpr() except on SoCs where struct mc_ctrl is defined.

(actually, ifdefing the body might be useful anyway to remove the code from builds for older SoCs)

#2 lore raw

PATCH v2 1/1 ARM: tegra: Disable VPR

In reply to Alexandre Courbot

From: Bryan Wu <[email protected]>

On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project.

[acourbot: ensure write went through, vpr.c style changes]
Cc Tom Warren <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Terje Bergstrom <[email protected]>

---
Changes since v1:
- Use proper defines for fields values
- Move MC layout to T124 arch as it is exclusive to it
- Only compile VPR support if T124 is enabled

 arch/arm/cpu/tegra-common/Makefile      |  1 +
 arch/arm/cpu/tegra-common/ap.c          |  3 ++
 arch/arm/cpu/tegra-common/vpr.c         | 45 ++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra/ap.h    |  9 ++++++
 arch/arm/include/asm/arch-tegra124/mc.h | 49 +++++++++++++++++++++++++++++++++
 5 files changed, 107 insertions(+)
 create mode 100644 arch/arm/cpu/tegra-common/vpr.c
 create mode 100644 arch/arm/include/asm/arch-tegra124/mc.h
arch/arm/cpu/tegra-common/Makefile +1 -0
index 892556e64451..a18c318739fa 100644
@@ -14,3 +14,4 @@ obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-$(CONFIG_TEGRA124) += vpr.o
arch/arm/cpu/tegra-common/ap.c +3 -0
index 91d70da65661..a17dfd1e225e 100644
@@ -163,4 +163,7 @@ void s_init(void)
 
 	/* init the cache */
 	config_cache();
+
+	/* init vpr */
+	config_vpr();
 }
arch/arm/cpu/tegra-common/vpr.c new file +45 -0

45 lines not on this page · raw message

arch/arm/include/asm/arch-tegra/ap.h +9 -0
index bc5851c1d045..5c8be94d9772 100644
@@ -65,3 +65,12 @@ int tegra_get_sku_info(void);
 
 /* Do any chip-specific cache config */
 void config_cache(void);
+
+#if defined(CONFIG_TEGRA124)
+/* Do chip-specific vpr config */
+void config_vpr(void);
+#else
+static inline void config_vpr(void)
+{
+}
+#endif
arch/arm/include/asm/arch-tegra124/mc.h new file +49 -0

49 lines not on this page · raw message

Signature · 1 line
2.0.0
#3 lore raw

PATCH v2 1/1 ARM: tegra: Disable VPR

Quoted 11 lines · Alexandre Courbot

From: Bryan Wu <[email protected]>

On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project.

arch/arm/cpu/tegra-common/vpr.c line 34

Quoted 9 lines
arch/arm/cpu/tegra-common/vpr.c +8 -0
 
+void config_vpr(void)
+{
+	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+	/* VPR is only in T114 and T124 */
+	switch (tegra_get_chip()) {
+	case CHIPID_TEGRA114:
+	case CHIPID_TEGRA124:

You can drop the switch() and call to tegra_get_chip() since this is all done at compile-time now.

Other than that,

#4 lore raw

PATCH v2 1/1 ARM: tegra: Disable VPR

Quoted 13 lines · Stephen Warren
Quoted 11 lines · Alexandre Courbot

From: Bryan Wu <[email protected]>

On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed.

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project.

arch/arm/cpu/tegra-common/vpr.c +0 -0
Quoted 11 lines

arch/arm/cpu/tegra-common/vpr.c line 34

Quoted 8 lines
arch/arm/cpu/tegra-common/vpr.c +8 -0
+void config_vpr(void)
+{
+	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+	/* VPR is only in T114 and T124 */
+	switch (tegra_get_chip()) {
+	case CHIPID_TEGRA114:
+	case CHIPID_TEGRA124:

You can drop the switch() and call to tegra_get_chip() since this is all done at compile-time now.

Of course. What was I thinking...

Quoted 3 lines

Other than that,

Thanks!