peach_pit: Add support for FIMD, DP and parade chip

Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.

Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file.

Signed-off-by Ajay Kumar <[email protected]>

RPLL is needed to drive the LCD panel on Exynos5420 based boards.

Signed-off-by Ajay Kumar <[email protected]>

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by Ajay Kumar <[email protected]>

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by Ajay Kumar <[email protected]>

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by Ajay Kumar <[email protected]>

---
 arch/arm/cpu/armv7/exynos/clock.c         | 74 +++++++++++++++++++++++++++++--
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
 arch/arm/include/asm/arch-exynos/clk.h    |  1 +
 3 files changed, 73 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +66 -1

index 400d134..c29b12d 100644
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 	 * VPLL_CON: MIDV [24:16]
 	 * BPLL_CON: MIDV [25:16]: Exynos5
 	 */
-	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+	    pllreg == SPLL)
 		mask = 0x3ff;
 	else
 		mask = 0x1ff;

@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
 		r = readl(&clk->rpll_con0);
 		k = readl(&clk->rpll_con1);
 		break;
+	case SPLL:
+		r = readl(&clk->spll_con0);
+		break;
 	default:
 		printf("Unsupported PLL (%d)\n", pllreg);
 		return 0;

@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
 	return pclk;
 }
 
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * FIMD1_SEL [4]
+	 * 0: SCLK_RPLL
+	 * 1: SCLK_SPLL
+	 */
+	sel = readl(&clk->src_disp10);
+	sel &= (1 << 4);
+
+	if (sel)
+		sclk = get_pll_clk(SPLL);
+	else
+		sclk = get_pll_clk(RPLL);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_disp10);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
 void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =

@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
 	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
+void exynos5420_set_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int cfg;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * FIMD1_SEL [4]
+	 * 0: SCLK_RPLL
+	 * 1: SCLK_SPLL
+	 */
+	cfg = readl(&clk->src_disp10);
+	cfg &= ~(0x1 << 4);
+	cfg |= (0 << 4);
+	writel(cfg, &clk->src_disp10);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO		[3:0]
+	 */
+	cfg = readl(&clk->div_disp10);
+	cfg &= ~(0xf << 0);
+	cfg |= (0 << 0);
+	writel(cfg, &clk->div_disp10);
+}
+
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =

arch/arm/cpu/armv7/exynos/clock.c +0 -0

 	else
 		exynos5_set_lcd_clk();
 }

arch/arm/cpu/armv7/exynos/exynos5_setup.h +1 -1

index db8ea86..5eac9cf 100644
@@ -779,7 +779,7 @@
 #define CLK_SRC_TOP2_VAL	0x11101000
 #define CLK_SRC_TOP3_VAL	0x11111111
 #define CLK_SRC_TOP4_VAL	0x11110111
-#define CLK_SRC_TOP5_VAL	0x11111100
+#define CLK_SRC_TOP5_VAL	0x11111101
 #define CLK_SRC_TOP6_VAL	0x11110111
 #define CLK_SRC_TOP7_VAL	0x00022200
 

arch/arm/include/asm/arch-exynos/clk.h +0 -0

index ffbc07e..db24dc0 100644

Quoted 114 lines · Ajay Kumar

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by Ajay Kumar <[email protected]>

---
 arch/arm/cpu/armv7/exynos/clock.c         | 74 +++++++++++++++++++++++++++++--
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
 arch/arm/include/asm/arch-exynos/clk.h    |  1 +
 3 files changed, 73 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +66 -1

index 400d134..c29b12d 100644
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
       * VPLL_CON: MIDV [24:16]
       * BPLL_CON: MIDV [25:16]: Exynos5
       */
-     if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+     if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+         pllreg == SPLL)
              mask = 0x3ff;
      else
              mask = 0x1ff;

@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
              r = readl(&clk->rpll_con0);
              k = readl(&clk->rpll_con1);
              break;
+     case SPLL:
+             r = readl(&clk->spll_con0);
+             break;
      default:
              printf("Unsupported PLL (%d)\n", pllreg);
              return 0;

@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
      return pclk;
 }
 
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+     struct exynos5420_clock *clk =
+             (struct exynos5420_clock *)samsung_get_base_clock();
+     unsigned long pclk, sclk;
+     unsigned int sel;
+     unsigned int ratio;
+
+     /*
+      * CLK_SRC_DISP10
+      * FIMD1_SEL [4]
+      * 0: SCLK_RPLL
+      * 1: SCLK_SPLL
+      */
+     sel = readl(&clk->src_disp10);
+     sel &= (1 << 4);
+
+     if (sel)
+             sclk = get_pll_clk(SPLL);
+     else
+             sclk = get_pll_clk(RPLL);
+
+     /*
+      * CLK_DIV_DISP10
+      * FIMD1_RATIO [3:0]
+      */
+     ratio = readl(&clk->div_disp10);
+     ratio = ratio & 0xf;
+
+     pclk = sclk / (ratio + 1);
+
+     return pclk;
+}
+
 void exynos4_set_lcd_clk(void)
 {
      struct exynos4_clock *clk =

@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
      clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
+void exynos5420_set_lcd_clk(void)
+{
+     struct exynos5420_clock *clk =
+             (struct exynos5420_clock *)samsung_get_base_clock();
+     unsigned int cfg;
+
+     /*
+      * CLK_SRC_DISP10
+      * FIMD1_SEL [4]
+      * 0: SCLK_RPLL
+      * 1: SCLK_SPLL
+      */
+     cfg = readl(&clk->src_disp10);
+     cfg &= ~(0x1 << 4);
+     cfg |= (0 << 4);
+     writel(cfg, &clk->src_disp10);
+
+     /*
+      * CLK_DIV_DISP10
+      * FIMD1_RATIO          [3:0]
+      */
+     cfg = readl(&clk->div_disp10);
+     cfg &= ~(0xf << 0);
+     cfg |= (0 << 0);
+     writel(cfg, &clk->div_disp10);
+}
+
 void exynos4_set_mipi_clk(void)
 {
      struct exynos4_clock *clk =

@@ -1602,14 +1667,17 @@ unsigned long get_lcd_clk(void)
 {
      if (cpu_is_exynos4())
              return exynos4_get_lcd_clk();

arch/arm/cpu/armv7/exynos/clock.c unsigned long get_lcd_clk(void) · line 1672

Quoted 5 lines

arch/arm/cpu/armv7/exynos/clock.c +3 -2

-     else
-             return exynos5_get_lcd_clk();
+     else if (proid_is_exynos5420())
+             return exynos5420_get_lcd_clk();
+     return exynos5_get_lcd_clk();

No. Please don't mix cpu_is... and proid_is....
You can refer to other functions.

arch/arm/cpu/armv7/exynos/clock.c unsigned long get_lcd_clk(void) · line 1680

Quoted 8 lines

arch/arm/cpu/armv7/exynos/clock.c +2 -0

 }
 
 void set_lcd_clk(void)
 {
      if (cpu_is_exynos4())
              exynos4_set_lcd_clk();
+     else if (proid_is_exynos5420())
+             exynos5420_set_lcd_clk();

ditto.

Quoted 22 lines

arch/arm/cpu/armv7/exynos/clock.c +0 -0

      else
              exynos5_set_lcd_clk();
 }

arch/arm/cpu/armv7/exynos/exynos5_setup.h +1 -1

index db8ea86..5eac9cf 100644
@@ -779,7 +779,7 @@
 #define CLK_SRC_TOP2_VAL     0x11101000
 #define CLK_SRC_TOP3_VAL     0x11111111
 #define CLK_SRC_TOP4_VAL     0x11110111
-#define CLK_SRC_TOP5_VAL     0x11111100
+#define CLK_SRC_TOP5_VAL     0x11111101
 #define CLK_SRC_TOP6_VAL     0x11110111
 #define CLK_SRC_TOP7_VAL     0x00022200
 

arch/arm/include/asm/arch-exynos/clk.h +0 -0

index ffbc07e..db24dc0 100644

arch/arm/include/asm/arch-exynos/clk.h line 21

Quoted 7 lines

arch/arm/include/asm/arch-exynos/clk.h +1 -0

@@ -15,6 +15,7 @@
 #define VPLL 4
 #define BPLL 5
 #define RPLL 6
+#define SPLL 7
 
 #define MASK_PRE_RATIO(x)    (0xff << ((x << 4) + 8))
 #define MASK_RATIO(x)                (0xf << (x << 4))

Thanks,
Minkyu Kang.
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Hi Minkyu,

Quoted 115 lines · Minkyu Kang

Quoted 114 lines · Ajay Kumar

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by Ajay Kumar <[email protected]>

---
 arch/arm/cpu/armv7/exynos/clock.c         | 74 +++++++++++++++++++++++++++++--
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
 arch/arm/include/asm/arch-exynos/clk.h    |  1 +
 3 files changed, 73 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +66 -1

index 400d134..c29b12d 100644
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
       * VPLL_CON: MIDV [24:16]
       * BPLL_CON: MIDV [25:16]: Exynos5
       */
-     if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+     if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+         pllreg == SPLL)
              mask = 0x3ff;
      else
              mask = 0x1ff;

@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
              r = readl(&clk->rpll_con0);
              k = readl(&clk->rpll_con1);
              break;
+     case SPLL:
+             r = readl(&clk->spll_con0);
+             break;
      default:
              printf("Unsupported PLL (%d)\n", pllreg);
              return 0;

@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
      return pclk;
 }
 
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+     struct exynos5420_clock *clk =
+             (struct exynos5420_clock *)samsung_get_base_clock();
+     unsigned long pclk, sclk;
+     unsigned int sel;
+     unsigned int ratio;
+
+     /*
+      * CLK_SRC_DISP10
+      * FIMD1_SEL [4]
+      * 0: SCLK_RPLL
+      * 1: SCLK_SPLL
+      */
+     sel = readl(&clk->src_disp10);
+     sel &= (1 << 4);
+
+     if (sel)
+             sclk = get_pll_clk(SPLL);
+     else
+             sclk = get_pll_clk(RPLL);
+
+     /*
+      * CLK_DIV_DISP10
+      * FIMD1_RATIO [3:0]
+      */
+     ratio = readl(&clk->div_disp10);
+     ratio = ratio & 0xf;
+
+     pclk = sclk / (ratio + 1);
+
+     return pclk;
+}
+
 void exynos4_set_lcd_clk(void)
 {
      struct exynos4_clock *clk =

@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
      clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
+void exynos5420_set_lcd_clk(void)
+{
+     struct exynos5420_clock *clk =
+             (struct exynos5420_clock *)samsung_get_base_clock();
+     unsigned int cfg;
+
+     /*
+      * CLK_SRC_DISP10
+      * FIMD1_SEL [4]
+      * 0: SCLK_RPLL
+      * 1: SCLK_SPLL
+      */
+     cfg = readl(&clk->src_disp10);
+     cfg &= ~(0x1 << 4);
+     cfg |= (0 << 4);
+     writel(cfg, &clk->src_disp10);
+
+     /*
+      * CLK_DIV_DISP10
+      * FIMD1_RATIO          [3:0]
+      */
+     cfg = readl(&clk->div_disp10);
+     cfg &= ~(0xf << 0);
+     cfg |= (0 << 0);
+     writel(cfg, &clk->div_disp10);
+}
+
 void exynos4_set_mipi_clk(void)
 {
      struct exynos4_clock *clk =

@@ -1602,14 +1667,17 @@ unsigned long get_lcd_clk(void)
 {
      if (cpu_is_exynos4())
              return exynos4_get_lcd_clk();

Quoted 8 lines

arch/arm/cpu/armv7/exynos/clock.c unsigned long get_lcd_clk(void) · line 1672

Quoted 5 lines

arch/arm/cpu/armv7/exynos/clock.c +3 -2

-     else
-             return exynos5_get_lcd_clk();
+     else if (proid_is_exynos5420())
+             return exynos5420_get_lcd_clk();
+     return exynos5_get_lcd_clk();

No. Please don't mix cpu_is... and proid_is....
You can refer to other functions.

Actually, only "cpu_is_exynos4" and "cpu_is_exynos5" are defined in cpu.h. And, I need different clock setting for 5250 and 5420.
The only way to achieve this is by calling appropriate functions based on check to proid_is_exynos5420().
Let me know if these is some other way!

Quoted 126 lines · Ajay kumar

Hi Minkyu,

Quoted 115 lines · Minkyu Kang

Quoted 114 lines · Ajay Kumar

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by Ajay Kumar <[email protected]>

---
 arch/arm/cpu/armv7/exynos/clock.c         | 74 +++++++++++++++++++++++++++++--
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
 arch/arm/include/asm/arch-exynos/clk.h    |  1 +
 3 files changed, 73 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +66 -1

index 400d134..c29b12d 100644
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
       * VPLL_CON: MIDV [24:16]
       * BPLL_CON: MIDV [25:16]: Exynos5
       */
-     if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+     if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+         pllreg == SPLL)
              mask = 0x3ff;
      else
              mask = 0x1ff;

@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
              r = readl(&clk->rpll_con0);
              k = readl(&clk->rpll_con1);
              break;
+     case SPLL:
+             r = readl(&clk->spll_con0);
+             break;
      default:
              printf("Unsupported PLL (%d)\n", pllreg);
              return 0;

@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
      return pclk;
 }
 
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+     struct exynos5420_clock *clk =
+             (struct exynos5420_clock *)samsung_get_base_clock();
+     unsigned long pclk, sclk;
+     unsigned int sel;
+     unsigned int ratio;
+
+     /*
+      * CLK_SRC_DISP10
+      * FIMD1_SEL [4]
+      * 0: SCLK_RPLL
+      * 1: SCLK_SPLL
+      */
+     sel = readl(&clk->src_disp10);
+     sel &= (1 << 4);
+
+     if (sel)
+             sclk = get_pll_clk(SPLL);
+     else
+             sclk = get_pll_clk(RPLL);
+
+     /*
+      * CLK_DIV_DISP10
+      * FIMD1_RATIO [3:0]
+      */
+     ratio = readl(&clk->div_disp10);
+     ratio = ratio & 0xf;
+
+     pclk = sclk / (ratio + 1);
+
+     return pclk;
+}
+
 void exynos4_set_lcd_clk(void)
 {
      struct exynos4_clock *clk =

@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
      clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
+void exynos5420_set_lcd_clk(void)
+{
+     struct exynos5420_clock *clk =
+             (struct exynos5420_clock *)samsung_get_base_clock();
+     unsigned int cfg;
+
+     /*
+      * CLK_SRC_DISP10
+      * FIMD1_SEL [4]
+      * 0: SCLK_RPLL
+      * 1: SCLK_SPLL
+      */
+     cfg = readl(&clk->src_disp10);
+     cfg &= ~(0x1 << 4);
+     cfg |= (0 << 4);
+     writel(cfg, &clk->src_disp10);
+
+     /*
+      * CLK_DIV_DISP10
+      * FIMD1_RATIO          [3:0]
+      */
+     cfg = readl(&clk->div_disp10);
+     cfg &= ~(0xf << 0);
+     cfg |= (0 << 0);
+     writel(cfg, &clk->div_disp10);
+}
+
 void exynos4_set_mipi_clk(void)
 {
      struct exynos4_clock *clk =

@@ -1602,14 +1667,17 @@ unsigned long get_lcd_clk(void)
 {
      if (cpu_is_exynos4())
              return exynos4_get_lcd_clk();

Quoted 8 lines

arch/arm/cpu/armv7/exynos/clock.c unsigned long get_lcd_clk(void) · line 1672

Quoted 5 lines

arch/arm/cpu/armv7/exynos/clock.c +3 -2

-     else
-             return exynos5_get_lcd_clk();
+     else if (proid_is_exynos5420())
+             return exynos5420_get_lcd_clk();
+     return exynos5_get_lcd_clk();

No. Please don't mix cpu_is... and proid_is....
You can refer to other functions.

Quoted 5 lines

Actually, only "cpu_is_exynos4" and "cpu_is_exynos5" are defined in cpu.h. And, I need different clock setting for 5250 and 5420.
The only way to achieve this is by calling appropriate functions based on check to proid_is_exynos5420().
Let me know if these is some other way!

unsigned long get_lcd_clk(void)

{
        if (cpu_is_exynos4()) {
                return exynos4_get_lcd_clk();
        } else {
                if (proid_is_exynos5420())
                        return exynos5420_get_lcd_clk();
                else
                        return exynos5_get_lcd_clk();
        }
}

Quoted 38 lines · Minkyu Kang

Quoted 30 lines · Ajay kumar

Hi Minkyu,

Quoted 12 lines · Minkyu Kang

Quoted 11 lines · Ajay Kumar

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by Ajay Kumar <[email protected]>

---
 arch/arm/cpu/armv7/exynos/clock.c         | 74 +++++++++++++++++++++++++++++--
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |  2 +-
 arch/arm/include/asm/arch-exynos/clk.h    |  1 +
 3 files changed, 73 insertions(+), 4 deletions(-)

Quoted 15 lines

arch/arm/cpu/armv7/exynos/clock.c unsigned long get_lcd_clk(void) · line 1672

Quoted 12 lines

void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =

arch/arm/cpu/armv7/exynos/clock.c +3 -2

@@ -1602,14 +1667,17 @@ unsigned long get_lcd_clk(void)
 {
      if (cpu_is_exynos4())
              return exynos4_get_lcd_clk();
-     else
-             return exynos5_get_lcd_clk();
+     else if (proid_is_exynos5420())
+             return exynos5420_get_lcd_clk();
+     return exynos5_get_lcd_clk();

No. Please don't mix cpu_is... and proid_is....
You can refer to other functions.

Quoted 5 lines

Actually, only "cpu_is_exynos4" and "cpu_is_exynos5" are defined in cpu.h. And, I need different clock setting for 5250 and 5420.
The only way to achieve this is by calling appropriate functions based on check to proid_is_exynos5420().
Let me know if these is some other way!

unsigned long get_lcd_clk(void)

Quoted 10 lines

{
        if (cpu_is_exynos4()) {
                return exynos4_get_lcd_clk();
        } else {
                if (proid_is_exynos5420())
                        return exynos5420_get_lcd_clk();
                else
                        return exynos5_get_lcd_clk();
        }
}

Actually, both the ways, functionality is the same. Its just that, in your case readability is fine, and in my case the code takes fewer number of lines. ^^

Quoted 4 lines · Ajay kumar

Hi Minkyu,

Quoted 1 line · Minkyu Kang

On 17/06/14 18:06, Ajay Kumar wrote:

Quoted 8 lines

Quoted 3 lines

No. Please don't mix cpu_is... and proid_is....
You can refer to other functions.

Actually, only "cpu_is_exynos4" and "cpu_is_exynos5" are defined in cpu.h. And, I need different clock setting for 5250 and 5420.
The only way to achieve this is by calling appropriate functions based on check to proid_is_exynos5420().
Let me know if these is some other way!

unsigned long get_lcd_clk(void)

{
        if (cpu_is_exynos4()) {
                return exynos4_get_lcd_clk();
        } else {
                if (proid_is_exynos5420())
                        return exynos5420_get_lcd_clk();
                else
                        return exynos5_get_lcd_clk();
        }
}

On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default.
We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420.

Signed-off-by Ajay Kumar <[email protected]>

Quoted 6 lines · Ajay Kumar

On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default.
We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420.

Quoted 1 line

Signed-off-by Ajay Kumar <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

(I assume this is the same device tree binding as Linux?)

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Hi Simon,

Quoted 12 lines · Simon Glass

Quoted 7 lines · Ajay Kumar

On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default.
We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420.

Signed-off-by Ajay Kumar <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

Quoted 1 line

(I assume this is the same device tree binding as Linux?)

Actually, No!
Kernel has a generic binding named "samsung,sysmmu-v3.3", and it is common for all sysmmu nodes. There is a seperate IOMMU driver to handle the same. We can port the device probing part from kernel to u-boot, but we would need to add seperate driver(since the name is generic) to handle the same. That driver, even though being generic, will be used only by FIMD sysmmus(that too, just to turn them off).

Hi Ajay,

Quoted 16 lines · Ajay kumar

Hi Simon,

Quoted 12 lines · Simon Glass

Quoted 7 lines · Ajay Kumar

On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default.
We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420.

Signed-off-by Ajay Kumar <[email protected]>

Acked-by Simon Glass <[email protected]>

Tested-by Simon Glass <[email protected]>

Quoted 8 lines

Quoted 1 line

(I assume this is the same device tree binding as Linux?)

Actually, No!
Kernel has a generic binding named "samsung,sysmmu-v3.3", and it is common for all sysmmu nodes. There is a seperate IOMMU driver to handle the same. We can port the device probing part from kernel to u-boot, but we would need to add seperate driver(since the name is generic) to handle the same. That driver, even though being generic, will be used only by FIMD sysmmus(that too, just to turn them off).

OK. I suppose you could add a very short new C file with a function which finds the device tree node by its compatible string or whatever, and then updates the hardware.

Regards,
Simon

On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default.
We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420.

Signed-off-by Ajay Kumar <[email protected]>

From: Vadim Bendebury <[email protected]>

The initialization table comes from the "Illustration of I2C command for initialing PS8625" document supplied by Parade.

Signed-off-by Vadim Bendebury <[email protected]>

Signed-off-by Ajay Kumar <[email protected]>

From: Vadim Bendebury <[email protected]>

The initialization table comes from the "Illustration of I2C command for initialing PS8625" document supplied by Parade.

Signed-off-by Vadim Bendebury <[email protected]>

Signed-off-by Ajay Kumar <[email protected]>

This patch adds missing declaration for gpio_direction_input function, thereby helps in resolving compilation warnings.

Signed-off-by Ajay Kumar <[email protected]>

---
 arch/arm/include/asm/arch-exynos/gpio.h | 1 +
 1 file changed, 1 insertion(+)

arch/arm/include/asm/arch-exynos/gpio.h +1 -1

index be5113f..8fb5c23 100644
@@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table exynos5420_gpio_table[] = {
 void gpio_cfg_pin(int gpio, int cfg);
 void gpio_set_pull(int gpio, int mode);
 void gpio_set_drv(int gpio, int mode);
+int gpio_direction_input(unsigned gpio);
 int gpio_direction_output(unsigned gpio, int value);
 int gpio_set_value(unsigned gpio, int value);
 int gpio_get_value(unsigned gpio);
--

1.8.1.2

Add initialization code for peach_pit panel, parade bridge chip, and backlight.

Signed-off-by Ajay Kumar <[email protected]>

This patch adds DT properties for fimd and the parade bridge chip present on peach_pit. The panel supports 1366x768 resolution.

Signed-off-by Ajay Kumar <[email protected]>

Enable drivers for FIMD, DP and parade bridge chip.

Signed-off-by Ajay Kumar <[email protected]>

---
 include/configs/peach-pit.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

include/configs/peach-pit.h +1 -0

index 76b8d7a..88c093f 100644
@@ -22,4 +22,14 @@
 #define CONFIG_SYS_PROMPT      "Peach # "
 #define CONFIG_IDENT_STRING    " for Peach"
 
+#define CONFIG_VIDEO_PARADE

Hi Ajay,

Quoted 15 lines · Ajay Kumar

Enable drivers for FIMD, DP and parade bridge chip.

Signed-off-by Ajay Kumar <[email protected]>

---
 include/configs/peach-pit.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

include/configs/peach-pit.h +0 -0

index 76b8d7a..88c093f 100644
@@ -22,4 +22,14 @@
 #define CONFIG_SYS_PROMPT      "Peach # "
 #define CONFIG_IDENT_STRING    " for Peach"
 

include/configs/peach-pit.h line 35

Quoted 11 lines

include/configs/peach-pit.h +10 -0

+#define CONFIG_VIDEO_PARADE
+
+/* Display */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_BPP                        LCD_COLOR16
+#endif
+
 #endif /* __CONFIG_PEACH_PIT_H */

Can this go in exynos5420.h? It seems to be common except for the PARADE bit.

Regards,
Simon
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Simon,

Quoted 18 lines · Simon Glass

Hi Ajay,

Quoted 15 lines · Ajay Kumar

Enable drivers for FIMD, DP and parade bridge chip.

Signed-off-by Ajay Kumar <[email protected]>

---
 include/configs/peach-pit.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

include/configs/peach-pit.h +0 -0

index 76b8d7a..88c093f 100644
@@ -22,4 +22,14 @@
 #define CONFIG_SYS_PROMPT      "Peach # "
 #define CONFIG_IDENT_STRING    " for Peach"
 

Quoted 13 lines

include/configs/peach-pit.h line 35

Quoted 11 lines

include/configs/peach-pit.h +10 -0

+#define CONFIG_VIDEO_PARADE
+
+/* Display */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_BPP                        LCD_COLOR16
+#endif
+
 #endif /* __CONFIG_PEACH_PIT_H */

Can this go in exynos5420.h? It seems to be common except for the PARADE bit.

No. This patchset enables display only for peach_pit. So, we cannot move this to exynos5420.h.

From: Simon Glass <[email protected]>

WIP patch to enable cros-ec on peach_pit.

Signed-off-by Simon Glass <[email protected]>

---
 drivers/misc/cros_ec_spi.c            |   4 +-
 drivers/power/pmic/Makefile           |   3 +-
 drivers/power/pmic/pmic_tps65090_ec.c | 212 ++++++++++++++++++++++++++++++++++
 drivers/spi/exynos_spi.c              |   9 +-
 drivers/spi/spi.c                     |   2 +
 include/configs/exynos5-dt.h          |   2 +-
 include/configs/peach-pit.h           |   2 +
 include/power/tps65090_pmic.h         |   6 +
 8 files changed, 232 insertions(+), 8 deletions(-)
 create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c