clk/exynos5250: fix bit number for tv sysmmu clock
Subsystems (3)
PATCH 1/1 clk/exynos5250: fix bit number for tv sysmmu clock
Change bit from 2 to 9 for tv (mixer) sysmmu clock.
---
Based on Kukjin's for-next branch.
drivers/clk/samsung/clk-exynos5250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5250.c +1 -1
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {GATE (CLK_RTC ,"rtc" ,"div_aclk66" ,GATE_IP_PERIS ,20 ,0 ,0 ),GATE (CLK_TMU ,"tmu" ,"div_aclk66" ,GATE_IP_PERIS ,21 ,0 ,0 ),GATE (CLK_SMMU_TV ,"smmu_tv" ,"mout_aclk200_disp1_sub" , -GATE_IP_DISP1 ,2 ,0 ,0 ), +GATE_IP_DISP1 ,9 ,0 ,0 ),GATE (CLK_SMMU_FIMD1 ,"smmu_fimd1" ,"mout_aclk200_disp1_sub" ,GATE_IP_DISP1 ,8 ,0 ,0 ), GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
Signature · 1 line
1.7.9.5
PATCH 1/1 clk/exynos5250: fix bit number for tv sysmmu clock
Quoted 14 lines · Rahul Sharma
Change bit from 2 to 9 for tv (mixer) sysmmu clock.
Signed-off-by Rahul Sharma <[email protected]>---
Based on Kukjin's for-next branch.drivers/clk/samsung/clk-exynos5250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/samsung/clk-exynos5250.c +0
-0
drivers/clk/samsung/clk-exynos5250.c static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { · line 664
Quoted 5 lines
drivers/clk/samsung/clk-exynos5250.c +1
-1@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {GATE (CLK_RTC ,"rtc" ,"div_aclk66" ,GATE_IP_PERIS ,20 ,0 ,0 ),GATE (CLK_TMU ,"tmu" ,"div_aclk66" ,GATE_IP_PERIS ,21 ,0 ,0 ),GATE (CLK_SMMU_TV ,"smmu_tv" ,"mout_aclk200_disp1_sub" , - GATE_IP_DISP1, 2, 0, 0), + GATE_IP_DISP1, 9, 0, 0),
SysMMU TV corresponds to bit 9 as per user manual of 5250.
PATCH 1/1 clk/exynos5250: fix bit number for tv sysmmu clock
Hi Kukjin,
Please take this fix in your tree.
Regards,
Rahul Sharma
Quoted 23 lines · Sachin Kamat
Quoted 14 lines · Rahul Sharma
Change bit from 2 to 9 for tv (mixer) sysmmu clock.
Signed-off-by Rahul Sharma <[email protected]>---
Based on Kukjin's for-next branch.drivers/clk/samsung/clk-exynos5250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/samsung/clk-exynos5250.c +0
-0drivers/clk/samsung/clk-exynos5250.c static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { · line 664
Quoted 5 lines
drivers/clk/samsung/clk-exynos5250.c +1
-1@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {GATE (CLK_RTC ,"rtc" ,"div_aclk66" ,GATE_IP_PERIS ,20 ,0 ,0 ),GATE (CLK_TMU ,"tmu" ,"div_aclk66" ,GATE_IP_PERIS ,21 ,0 ,0 ),GATE (CLK_SMMU_TV ,"smmu_tv" ,"mout_aclk200_disp1_sub" , - GATE_IP_DISP1, 2, 0, 0), + GATE_IP_DISP1, 9, 0, 0),SysMMU TV corresponds to bit 9 as per user manual of 5250.
Reviewed-by Sachin Kamat <[email protected]>
PATCH 1/1 clk/exynos5250: fix bit number for tv sysmmu clock
Hi Rahul,
Quoted 3 lines · Rahul Sharma
Hi Kukjin,
Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about to send fixes pull request to Mike.
Best regards,
Tomasz
PATCH 1/1 clk/exynos5250: fix bit number for tv sysmmu clock
Quoted 11 lines · Tomasz Figa
Hi Rahul,
Quoted 3 lines · Rahul Sharma
Hi Kukjin,
Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about to send fixes pull request to Mike.
Yes, I also checked the datasheet and this change is correct.
If you want, please add my ack on the patch.
Thanks,
Kukjin
PATCH 1/1 clk/exynos5250: fix bit number for tv sysmmu clock
Sure Tomasz, Kukjin.
Thanks for the update.
Regards.
Quoted 24 lines · Kukjin Kim
Quoted 11 lines · Tomasz Figa
Hi Rahul,
Quoted 3 lines · Rahul Sharma
Hi Kukjin,
Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about to send fixes pull request to Mike.
Yes, I also checked the datasheet and this change is correct.
If you want, please add my ack on the patch.
Thanks,
Kukjin_______________________________________________
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Tomasz Figa
AppliedPATCH 1/1 clk/exynos5250: fix bit number for tv sysmmu clock
In reply to Rahul SharmaQuoted 15 lines · Rahul Sharma
Change bit from 2 to 9 for tv (mixer) sysmmu clock.
Signed-off-by Rahul Sharma <[email protected]>---
Based on Kukjin's for-next branch.drivers/clk/samsung/clk-exynos5250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/samsung/clk-exynos5250.c +0
-0
drivers/clk/samsung/clk-exynos5250.c static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { · line 667
Quoted 8 lines
drivers/clk/samsung/clk-exynos5250.c +1
-1@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {GATE (CLK_RTC ,"rtc" ,"div_aclk66" ,GATE_IP_PERIS ,20 ,0 ,0 ),GATE (CLK_TMU ,"tmu" ,"div_aclk66" ,GATE_IP_PERIS ,21 ,0 ,0 ),GATE (CLK_SMMU_TV ,"smmu_tv" ,"mout_aclk200_disp1_sub" , -GATE_IP_DISP1 ,2 ,0 ,0 ), +GATE_IP_DISP1 ,9 ,0 ,0 ),GATE (CLK_SMMU_FIMD1 ,"smmu_fimd1" ,"mout_aclk200_disp1_sub" ,GATE_IP_DISP1 ,8 ,0 ,0 ), GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
Applied as a fix for 3.16.
Best regards,
Tomasz