x86/pmc_atom: disable a few S0ix wake up events for S0ix residency
PATCH RESEND 2/3 x86/pmc_atom: disable a few S0ix wake up events for S0ix residency
Disable PMC S0IX_WAKE_EN events coming from LPC block(unused) and also from GPIO_SUS ored dedicated IRQs (must be disabled as per PMC programming rule), GPIOSCORE ored dedicated IRQs (must be disabled as per PMC programming rule), GPIO_SUS shared IRQ (not necessary since the IOAPIC_DS wake event will still work), GPIO_SCORE shared IRQ (not necessary since the IOAPIC_DS wake event will still work).
--- arch/x86/include/asm/pmc_atom.h | 21 ++++++++++++++++++++ arch/x86/kernel/pmc_atom.c | 42 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)
arch/x86/include/asm/pmc_atom.h +21 -0
@@ -19,6 +19,27 @@/* ValleyView Power Control Unit PCI Device ID */ #define PCI_DEVICE_ID_VLV_PMC 0x0F1C +/* PMC Memory mapped IO registers */ +#define PMC_BASE_ADDR_OFFSET 0x44 +#define PMC_BASE_ADDR_MASK 0xFFFFFE00 +#define PMC_MMIO_REG_LEN 0x100 +#define PMC_REG_BIT_WIDTH 32 + +/* S0ix wake event control */ +#define PMC_S0IX_WAKE_EN 0x3C + +#define BIT_LPC_CLOCK_RUN BIT(4) +#define BIT_SHARED_IRQ_GPSC BIT(5) +#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18) +#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19) +#define BIT_SHARED_IRQ_GPSS BIT(20) + +#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \ + BIT_SHARED_IRQ_GPSC | \ + BIT_ORED_DEDICATED_IRQ_GPSS | \ + BIT_ORED_DEDICATED_IRQ_GPSC | \ + BIT_SHARED_IRQ_GPSS) +/* PMC I/O Registers */ #define ACPI_BASE_ADDR_OFFSET 0x40#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
arch/x86/kernel/pmc_atom.c +42 -0
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1.7.10.4
tip-bot for Li, Aubrey
merge bot[tip:x86/platform] x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency
x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency
Commit-ID: b00055cade45379fb6a51798b70ef520d7555c5f Gitweb: http://git.kernel.org/tip/b00055cade45379fb6a51798b70ef520d7555c5f Author: Li, Aubrey <[email protected]> AuthorDate: Mon, 30 Jun 2014 14:09:38 +0800 Committer: H. Peter Anvin <[email protected]> CommitDate: Fri, 25 Jul 2014 14:11:58 -0700
x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency
Disable PMC S0IX_WAKE_EN events coming from LPC block(unused) and also from GPIO_SUS ored dedicated IRQs (must be disabled as per PMC programming rule), GPIOSCORE ored dedicated IRQs (must be disabled as per PMC programming rule), GPIO_SUS shared IRQ (not necessary since the IOAPIC_DS wake event will still work), GPIO_SCORE shared IRQ (not necessary since the IOAPIC_DS wake event will still work).
--- arch/x86/include/asm/pmc_atom.h | 21 +++++++++++++++++++++ arch/x86/kernel/pmc_atom.c | 42 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)
arch/x86/include/asm/pmc_atom.h +21 -0
@@ -19,6 +19,27 @@/* ValleyView Power Control Unit PCI Device ID */ #define PCI_DEVICE_ID_VLV_PMC 0x0F1C +/* PMC Memory mapped IO registers */ +#define PMC_BASE_ADDR_OFFSET 0x44 +#define PMC_BASE_ADDR_MASK 0xFFFFFE00 +#define PMC_MMIO_REG_LEN 0x100 +#define PMC_REG_BIT_WIDTH 32 + +/* S0ix wake event control */ +#define PMC_S0IX_WAKE_EN 0x3C + +#define BIT_LPC_CLOCK_RUN BIT(4) +#define BIT_SHARED_IRQ_GPSC BIT(5) +#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18) +#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19) +#define BIT_SHARED_IRQ_GPSS BIT(20) + +#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \ + BIT_SHARED_IRQ_GPSC | \ + BIT_ORED_DEDICATED_IRQ_GPSS | \ + BIT_ORED_DEDICATED_IRQ_GPSC | \ + BIT_SHARED_IRQ_GPSS) +/* PMC I/O Registers */ #define ACPI_BASE_ADDR_OFFSET 0x40#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
arch/x86/kernel/pmc_atom.c +42 -0
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