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TI: armv7: add parallel NAND support

PATCH New Pekon Gupta 4 participants 20 messages Jul 4, 2014 – Jul 21, 2014 Arm (32-bit)

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Pekon Gupta

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#0 lore raw

cover TI: armv7: add parallel NAND support

This patch series adds support for parallel NAND devices support connected via GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms. This series also moves some board specific CONFIG_NAND_xx from generic files to individual files.

Tested using: ./MAKEALL -s am33xx -s omap3 -s oamp4 -s omap5
works fine except for am335x_boneblack_vboot
build breaks for am335x_boneblack_vboot for un-related reasons
u-boot/scripts/dtc-version.sh: line 17: dtc: command not found

Pekon Gupta (7):
TI: armv7: move board specific NAND configs out from ti_armv7_common.h

    and ti_am335x_common.h

board/ti/am335x: add support for beaglebone NAND cape
arm: lib: continue board_init_r even if valid flash device is not
detected
board/ti/am335x: add support for beaglebone NOR Cape board/ti/am335x: update configs for parallel NAND board/ti/am43xx: add support for parallel NAND board/ti/dra7xx: add support for parallel NAND

 arch/arm/lib/board.c               |   7 +-
 board/ti/am335x/mux.c              | 149 ++++++++++++++++++-------------------
 board/ti/am43xx/board.c            |   1 +
 board/ti/am43xx/mux.c              |  42 +++++++++++
 board/ti/dra7xx/mux_data.h         |  30 ++++++++
 boards.cfg                         |   4 +-
 doc/README.nand                    |  12 +++
 include/configs/am335x_evm.h       |  64 +++++++++-------
 include/configs/am43xx_evm.h       |  70 +++++++++++++++++
 include/configs/cm_t335.h          |  10 +++
 include/configs/dra7xx_evm.h       |  58 ++++++++++++++-
 include/configs/omap3_beagle.h     |   6 ++
 include/configs/omap3_igep00x0.h   |   9 +++
 include/configs/omap3_overo.h      |   8 ++
 include/configs/omap3_zoom1.h      |   7 ++
 include/configs/pengwyn.h          |   7 ++
 include/configs/ti_am335x_common.h |   4 -
 include/configs/ti_armv7_common.h  |   9 ---
 18 files changed, 369 insertions(+), 128 deletions(-)
Signature · 1 line
1.8.5.1.163.gd7aced9
author
#1 lore raw

PATCH 1/7 TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h

This patch moves some board specific NAND configs:
- FROM: generic config files like 'ti_armv7_common.h' and 'ti_am335x_common.h'
- TO: individual board config files using these configs.
So that each board can independently set the value as per its design.

Following configs are affected in this patch:
CONFIG_NAND_OMAP_GPMC: <refer doc/README.nand>
CONFIG_NAND_OMAP_ELM: <refer doc/README.nand> CONFIG_SPL_NAND_AM33XX_BCH: <refer doc/README.nand> CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon> CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>

This patch also updates documentation for few of above NAND configs.

Signed-off-by Pekon Gupta <[email protected]>
---
 doc/README.nand                    | 12 ++++++++++++
 include/configs/am335x_evm.h       |  7 +++++++
 include/configs/cm_t335.h          | 10 ++++++++++
 include/configs/omap3_beagle.h     |  6 ++++++
 include/configs/omap3_igep00x0.h   |  9 +++++++++
 include/configs/omap3_overo.h      |  8 ++++++++
 include/configs/omap3_zoom1.h      |  7 +++++++
 include/configs/pengwyn.h          |  7 +++++++
 include/configs/ti_am335x_common.h |  4 ----
 include/configs/ti_armv7_common.h  |  9 ---------
 10 files changed, 66 insertions(+), 13 deletions(-)
doc/README.nand +12 -0
index 70cf768..e29188f 100644
@@ -89,6 +89,10 @@ Commands:
 
 Configuration Options:
 
+   CONFIG_SYS_NAND_U_BOOT_OFFS
+	NAND Offset from where SPL will read u-boot image. This is the starting
+	address of u-boot MTD partition in NAND.
+
    CONFIG_CMD_NAND
       Enables NAND support and commmands.
 

@@ -226,6 +230,14 @@ Platform specific options
 	detection. However ECC calculation on such plaforms would still be
 	done by GPMC controller.
 
+   CONFIG_SPL_NAND_AM33XX_BCH
+	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
+        hardware ECC correction. This is useful for platforms which have ELM
+	hardware engine and use NAND boot mode.
+	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
+        SPL-NAND driver with software ECC correction support.
+
    CONFIG_NAND_OMAP_ECCSCHEME
 	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
 	It can take following values:
include/configs/am335x_evm.h +7 -0
index a48b386..57a6cab 100644
@@ -233,6 +233,8 @@
 #ifdef CONFIG_NAND
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SPL_NAND_AM33XX_BCH
+/* NAND: device related configs */
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)

@@ -254,6 +256,11 @@
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#ifdef CONFIG_SPL_OS_BOOT
+  #define CONFIG_CMD_SPL_NAND_OFS	0x00080000 /* os parameters */
+  #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+  #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 #endif
 #endif
include/configs/cm_t335.h +10 -0
index 4d1dd28..70b6e90 100644
@@ -150,6 +150,16 @@
 #define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* SPL-NAND driver with ELM support */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+  #define CONFIG_CMD_SPL_NAND_OFS	0x400000 /* un-assigned: (using dtb) */
+  #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x500000
+  #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 
 /* GPIO pin + bank to pin ID mapping */
 #define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
include/configs/omap3_beagle.h +6 -0
index c023483..7878765 100644
@@ -126,6 +126,12 @@
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x80200000\0" \
include/configs/omap3_igep00x0.h +9 -0
index 79daabd..7daaef5 100644
@@ -187,6 +187,15 @@
 
 /* NAND boot config */
 #ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+  #define CONFIG_CMD_SPL_NAND_OFS	0x240000
+  #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+  #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+/* NAND: device related configs */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT	16
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
include/configs/omap3_overo.h +8 -0
index f7483a0..a879d72 100644
@@ -206,6 +206,14 @@
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* NAND boot config */
+#define CONFIG_NAND_OMAP_GPMC
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+  #define CONFIG_CMD_SPL_NAND_OFS	0x240000
+  #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+  #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
+/* NAND: device related configs */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT	16
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
include/configs/omap3_zoom1.h +7 -0
index 3efe4cf..409be31 100644
@@ -69,6 +69,13 @@
 					"1920k(u-boot),128k(u-boot-env),"\
 					"4m(kernel),-(fs)"
 
+#define CONFIG_NAND_OMAP_GPMC
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+  #define CONFIG_CMD_SPL_NAND_OFS	0x240000
+  #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+  #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
 #endif
include/configs/pengwyn.h +7 -0
index 8510405..f758cf9 100644
@@ -127,6 +127,7 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SPL_NAND_AM33XX_BCH
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)

@@ -159,6 +160,12 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+  #define CONFIG_CMD_SPL_NAND_OFS	0x240000 /* un-assigned */
+  #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+  #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 
 /*
  * USB configuration.  We enable MUSB support, both for host and for
include/configs/ti_am335x_common.h +0 -4
index 80976e7..12fceb7 100644
@@ -84,10 +84,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #endif
 
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
-#endif
-
 /* Now bring in the rest of the common code. */
 #include <configs/ti_armv7_common.h>
include/configs/ti_armv7_common.h +0 -9
index 6e0bf09..c901522 100644
@@ -110,7 +110,6 @@
  * access CS0 at is 0x8000000.
  */
 #ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
 #ifndef CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE		0x8000000
 #endif

@@ -243,13 +242,6 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
 
-/* NAND */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_SPL_NAND_OFS			0x240000 /* end of u-boot */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x280000
-#define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
-#endif
-
 /* spl export command */
 #define CONFIG_CMD_SPL
 #endif

@@ -275,7 +267,6 @@
 #define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_MTD_SUPPORT
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #endif
 #endif /* !CONFIG_NOR_BOOT */
Signature · 1 line
1.8.5.1.163.gd7aced9
#2 lore raw

PATCH 1/7 TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h

Quoted 4 lines · Pekon Gupta

This patch moves some board specific NAND configs:
- FROM: generic config files like 'ti_armv7_common.h' and 'ti_am335x_common.h'
- TO: individual board config files using these configs.
So that each board can independently set the value as per its design.

I don't know. I intentionally merged these as they were all the same based on the reference layout. Maybe it should be in the ti_soc_common.h file rather than ti_armv7_common.h

include/configs/am335x_evm.h line 263

Quoted 9 lines
include/configs/am335x_evm.h +5 -0
@@ -254,6 +256,11 @@
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#ifdef CONFIG_SPL_OS_BOOT
+  #define CONFIG_CMD_SPL_NAND_OFS	0x00080000 /* os parameters */
+  #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+  #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif

No leading spaces please.

include/configs/ti_am335x_common.h line 89

Quoted 11 lines
include/configs/ti_am335x_common.h +0 -3
index 80976e7..12fceb7 100644
@@ -84,10 +84,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #endif
 
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
-#endif

This highlights a problem, this _is_ a SoC feature not a board feature.

include/configs/ti_armv7_common.h line 115

Quoted 12 lines
include/configs/ti_armv7_common.h +0 -1
index 6e0bf09..c901522 100644
@@ -110,7 +110,6 @@
  * access CS0 at is 0x8000000.
  */
 #ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
 #ifndef CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE		0x8000000
 #endif

And given keystone this should move to ti_{am335x,omap*}_common.h again as a SoC feature.

Signature · 8 lines
Tom
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author
#3 lore raw

PATCH 2/7 board/ti/am335x: add support for beaglebone NAND cape

In reply to Pekon Gupta

Beaglebone Board can be connected to expansion boards to add devices to them. These expansion boards are called 'capes'. This patch adds support for following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 Further information and datasheets can be found at [1] and [2]

* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any setting on SW2 (DIP switch), disconnect and reconnect all board power supply (including mini-USB console port) to POR the beaglebone.

- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme for NAND cape(b), ROM code expects BCH16_HW ecc-scheme

- Selction of boot modes can be controlled via DIP switch(SW2) present on Memory Expander cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC-> SPI -> UART -> USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
So to flash NAND, first boot via MMC or other sources and then switch to SW2[SWITCH_BOOT]=ON to boot from NAND Cape.

- For NAND boot following switch settings need to be followed

   SW2[ 1] = OFF  (SYSBOOT[ 0]==1: NAND boot mode selected )
   SW2[ 2] = OFF  (SYSBOOT[ 1]==1:       -- do --          )
   SW2[ 3] = ON   (SYSBOOT[ 2]==0:       -- do --          )
   SW2[ 4] = ON   (SYSBOOT[ 3]==0:       -- do --          )
   SW2[ 5] = OFF  (SYSBOOT[ 4]==1:       -- do --          )
   SW2[ 6] = OFF  (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
   SW2[ 7] = ON   (SYSBOOT[ 9]==0: ECC done by ROM  )
   SW2[ 8] = ON   (SYSBOOT[10]==0: Non Muxed device )
   SW2[ 9] = ON   (SYSBOOT[11]==0:    -- do --      )

[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2] http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module

Signed-off-by Pekon Gupta <[email protected]>
---
 board/ti/am335x/mux.c | 58 +++++++++++++++++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 20 deletions(-)
board/ti/am335x/mux.c +38 -20
index b2bfda5..439da4b 100644
@@ -171,25 +171,36 @@ static struct module_pin_mux mii1_pin_mux[] = {
 	{-1},
 };
 
+#ifdef CONFIG_NAND
 static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
+	{OFFSET(gpmc_ad1),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1  */
+	{OFFSET(gpmc_ad2),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2  */
+	{OFFSET(gpmc_ad3),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3  */
+	{OFFSET(gpmc_ad4),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4  */
+	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5  */
+	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6  */
+	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7  */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
+	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
+	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+	{OFFSET(gpmc_ad11),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+	{OFFSET(gpmc_ad12),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+	{OFFSET(gpmc_ad13),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+	{OFFSET(gpmc_ad14),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+	{OFFSET(gpmc_ad15),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+	{OFFSET(gpmc_wait0),	(MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
+	{OFFSET(gpmc_wpn),	(MODE(7) | PULLUP_EN)},		   /* nWP */
+	{OFFSET(gpmc_csn0),	(MODE(0) | PULLUP_EN)},		   /* nCS */
+	{OFFSET(gpmc_wen),	(MODE(0) | PULLDOWN_EN)},	   /* WEN */
+	{OFFSET(gpmc_oen_ren),	(MODE(0) | PULLDOWN_EN)},	   /* OE */
+	{OFFSET(gpmc_advn_ale),	(MODE(0) | PULLDOWN_EN)},	   /* ADV_ALE */
+	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},	   /* BE_CLE */
 	{-1},
 };
-
+#endif
 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
 	{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */

@@ -336,11 +347,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
-#ifndef CONFIG_NOR
-		configure_module_pin_mux(mmc1_pin_mux);
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#if defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
 		configure_module_pin_mux(bone_norcape_pin_mux);
+#else
+		configure_module_pin_mux(mmc1_pin_mux);
 #endif
 	} else if (board_is_gp_evm(header)) {
 		/* General Purpose EVM */

@@ -351,8 +363,10 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		if (profile & ~PROFILE_2)
 			configure_module_pin_mux(i2c1_pin_mux);
 		/* Profiles 2 & 3 don't have NAND */
+#ifdef CONFIG_NAND
 		if (profile & ~(PROFILE_2 | PROFILE_3))
 			configure_module_pin_mux(nand_pin_mux);
+#endif
 		else if (profile == PROFILE_2) {
 			configure_module_pin_mux(mmc1_pin_mux);
 			configure_module_pin_mux(spi0_pin_mux);

@@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#else
 		configure_module_pin_mux(mmc1_pin_mux);
+#endif
 	} else {
 		puts("Unknown board, cannot configure pinmux.");
 		hang();
Signature · 1 line
1.8.5.1.163.gd7aced9
#4 lore raw

PATCH 2/7 board/ti/am335x: add support for beaglebone NAND cape

Quoted 6 lines · Pekon Gupta

Beaglebone Board can be connected to expansion boards to add devices to them. These expansion boards are called 'capes'. This patch adds support for following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 Further information and datasheets can be found at [1] and [2]

[snip]

board/ti/am335x/mux.c void enable_board_pin_mux(struct am335x_baseboard_id *header) · line 398

Quoted 9 lines
board/ti/am335x/mux.c +4 -0
@@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#else
 		configure_module_pin_mux(mmc1_pin_mux);
+#endif

The above is the case for Beaglebone Black. Did you test the capes there as well? AFAIK the eMMC makes it a bit more tricky (or impossible?) to use some of the memory capes.

Signature · 8 lines
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#5 lore raw

PATCH 2/7 board/ti/am335x: add support for beaglebone NAND cape

Quoted 10 lines

From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom

Quoted 8 lines · Pekon Gupta

Beaglebone Board can be connected to expansion boards to add devices to them. These expansion boards are called 'capes'. This patch adds support for following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 Further information and datasheets can be found at [1] and [2]

[snip]

Quoted 14 lines

board/ti/am335x/mux.c void enable_board_pin_mux(struct am335x_baseboard_id *header) · line 398

Quoted 9 lines
board/ti/am335x/mux.c +4 -0
@@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#else
 		configure_module_pin_mux(mmc1_pin_mux);
+#endif

The above is the case for Beaglebone Black. Did you test the capes there as well? AFAIK the eMMC makes it a bit more tricky (or impossible?) to use some of the memory capes.

Yes, slightly tricky, but not impossible :-)
On Beaglebone all storage devices (NAND, NOR and eMMC) share GPMC pins. So this patch gives priority based on configs enabled in board-profile:

#ifdef CONFIG_NAND
	/* define NAND pin-mux */
#elseif CONFIG_NOR
	/* configure NOR pin-mux */
#else
	/* config eMMC pin-mux (default, if no NAND | NOR cape is present) */

#endif

Please refer to following log from beaglebone Black booting from NAND. U-boot was flashed on NAND using following commands:

	/* Flash MLO to NAND */
	fatload mmc 0 0x82000000 mlo
	nand write 0x82000000 0x0 0x20000
	/* Flash u-boot.img to NAND */
	fatload mmc 0 0x82000000 u-boot.img
	nand write 0x82000000 0xc0000 0x80000

-----------------
U-Boot 2014.07-00013-g838a657-dirty (Jul 21 2014 - 10:27:34)

I2C:   ready
DRAM:  512 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1

*** Warning - bad CRC, using default environment
Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 1  0
U-Boot#
------------------

*IMPORTANT NOTE*
As Beaglebone board shares the same config as AM335x EVM, so following changes are required in addition to this patch for Beaglebone NAND cape.
Therefore above image has a 'dirty commit'.
(1) Enable NAND in am335x_beaglebone board profile
(2) Add CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config because:
- AM335x EVM has NAND device with datawidth=8, whereas
- Beaglebone NAND cape has NAND device with data-width=16

diff --git a/boards.cfg b/boards.cfg
-Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL
+Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT

with regards, pekon

author
#6 lore raw

PATCH 3/7 arm: lib: continue board_init_r even if valid flash device is not detected

In reply to Pekon Gupta

Most platforms have fall-back boot sources, if their primary boot fails. This patch allows board_init to continue scanning through other secondary boot sources like NAND, MMC, etc if valid FLASH device is not detected.

Signed-off-by Pekon Gupta <[email protected]>
---
 arch/arm/lib/board.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)
arch/arm/lib/board.c +1 -6
index 76adaf3..413ee60 100644
@@ -460,10 +460,6 @@ void board_init_f(ulong bootflag)
 	memcpy(id, (void *)gd, sizeof(gd_t));
 }
 
-#if !defined(CONFIG_SYS_NO_FLASH)
-static char *failed = "*** failed ***\n";
-#endif
-
 /*
  * Tell if it's OK to load the environment early in boot.
  *

@@ -574,8 +570,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 		print_size(flash_size, "\n");
 # endif /* CONFIG_SYS_FLASH_CHECKSUM */
 	} else {
-		puts(failed);
-		hang();
+		puts("unable to detect valid flash device\n");
 	}
 #endif
Signature · 1 line
1.8.5.1.163.gd7aced9
#7 lore raw

PATCH 3/7 arm: lib: continue board_init_r even if valid flash device is not detected

Quoted 25 lines · Pekon Gupta

Most platforms have fall-back boot sources, if their primary boot fails. This patch allows board_init to continue scanning through other secondary boot sources like NAND, MMC, etc if valid FLASH device is not detected.

Signed-off-by Pekon Gupta <[email protected]>
---
 arch/arm/lib/board.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)
arch/arm/lib/board.c +0 -4
index 76adaf3..413ee60 100644
@@ -460,10 +460,6 @@ void board_init_f(ulong bootflag)
 	memcpy(id, (void *)gd, sizeof(gd_t));
 }
 
-#if !defined(CONFIG_SYS_NO_FLASH)
-static char *failed = "*** failed ***\n";
-#endif
-
 /*
  * Tell if it's OK to load the environment early in boot.
  *

arch/arm/lib/board.c void board_init_r(gd_t *id, ulong dest_addr) · line 575

Quoted 8 lines
arch/arm/lib/board.c +1 -2
@@ -574,8 +570,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 		print_size(flash_size, "\n");
 # endif /* CONFIG_SYS_FLASH_CHECKSUM */
 	} else {
-		puts(failed);
-		hang();
+		puts("unable to detect valid flash device\n");
 	}
 #endif

Albert?

Signature · 8 lines
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author
#8 lore raw

PATCH 4/7 board/ti/am335x: add support for beaglebone NOR Cape

In reply to Pekon Gupta

This patch updates pin-mux for beaglebone NOR cape [1]
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.

On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes, so only one of them can be enabled at a time from board profile configs.

[1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module

Signed-off-by Pekon Gupta <[email protected]>
---
 board/ti/am335x/mux.c | 95 +++++++++++++++++++--------------------------------
 1 file changed, 35 insertions(+), 60 deletions(-)
board/ti/am335x/mux.c +35 -60
index 439da4b..f6a9b29 100644
@@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},	   /* BE_CLE */
 	{-1},
 };
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
-	{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
-	{OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A1 */
-	{OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A2 */
-	{OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A3 */
-	{OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A4 */
-	{OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A5 */
-	{OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A6 */
-	{OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A7 */
-	{OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A8 */
-	{OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A9 */
-	{OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE},       /* NOR_A10 */
-	{OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
-	{OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A12 */
-	{OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A13 */
-	{OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A14 */
-	{OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A15 */
-	{OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A16 */
-	{OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A17 */
-	{OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A18 */
-	{OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A19 */
-	{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD0 */
-	{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD1 */
-	{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD2 */
-	{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD3 */
-	{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD4 */
-	{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD5 */
-	{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD6 */
-	{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD7 */
-	{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD8 */
-	{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD9 */
-	{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD10 */
-	{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD11 */
-	{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD12 */
-	{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD13 */
-	{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD14 */
-	{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD15 */
-
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE},   /* NOR_CE */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)},    /* NOR_WEN */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
+	{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD0 */
+	{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD1 */
+	{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD2 */
+	{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD3 */
+	{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD4 */
+	{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD5 */
+	{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD6 */
+	{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD7 */
+	{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD8 */
+	{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD9 */
+	{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD10 */
+	{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD11 */
+	{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD12 */
+	{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD13 */
+	{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD14 */
+	{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE},	/* AD15 */
+	{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS},			/* A0 */
+	{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS},			/* A1 */
+	{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS},			/* A2 */
+	{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS},			/* A3 */
+	{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS},			/* A4 */
+	{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS},			/* A5 */
+	{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS},			/* A6 */
+	{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS},			/* A7 */
+	{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN},     /* CE */
+	{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
+	{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
+	{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
+	{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN},    /* WEN */
+	{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
 	{-1},
 };
 #endif
 
 #if defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux norboot_pin_mux[] = {
-	{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
-	{-1},
-};
-
 void enable_norboot_pin_mux(void)
 {
-	configure_module_pin_mux(norboot_pin_mux);
+	configure_module_pin_mux(bone_norcape_pin_mux);
 }
 #endif
 

@@ -349,7 +322,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(mmc0_pin_mux);
 #if defined(CONFIG_NAND)
 		configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
 		configure_module_pin_mux(bone_norcape_pin_mux);
 #else
 		configure_module_pin_mux(mmc1_pin_mux);

@@ -393,6 +366,8 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(mmc0_pin_mux);
 #if defined(CONFIG_NAND)
 		configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR)
+		configure_module_pin_mux(bone_norcape_pin_mux);
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
 #endif
Signature · 1 line
1.8.5.1.163.gd7aced9
#9 lore raw

PATCH 4/7 board/ti/am335x: add support for beaglebone NOR Cape

Quoted 7 lines · Pekon Gupta

This patch updates pin-mux for beaglebone NOR cape [1]
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.

On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes, so only one of them can be enabled at a time from board profile configs.

[1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module

[snip]

board/ti/am335x/mux.c static struct module_pin_mux nand_pin_mux[] = { · line 206

Quoted 9 lines
board/ti/am335x/mux.c +1 -3
@@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},	   /* BE_CLE */
 	{-1},
 };
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
-	{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */

It _looks_ like this is jsut whitespace only. Since that doesn't match the rest of the file, please don't do that.

[snip]

Quoted 10 lines
board/ti/am335x/mux.c +0 -7
 #endif
 
 #if defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux norboot_pin_mux[] = {
-	{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},

board/ti/am335x/mux.c static struct module_pin_mux nand_pin_mux[] = { · line 242

Quoted 10 lines
board/ti/am335x/mux.c +1 -7
-	{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
-	{-1},
-};
-
 void enable_norboot_pin_mux(void)
 {
-	configure_module_pin_mux(norboot_pin_mux);
+	configure_module_pin_mux(bone_norcape_pin_mux);

Did you boot test this? The system requirements here are a bit strict and I don't know if we can just do what you're doing here...

Signature · 8 lines
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#10 lore raw

PATCH 4/7 board/ti/am335x: add support for beaglebone NOR Cape

Quoted 11 lines

From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom

Quoted 9 lines · Pekon Gupta

This patch updates pin-mux for beaglebone NOR cape [1]
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.

On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes, so only one of them can be enabled at a time from board profile configs.

[1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module

[snip]

Quoted 13 lines

Review static struct module_pin_mux nand_pin_mux[] = { · line 206

Quoted 9 lines
(quoted diff) +1 -3
@@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_be0n_cle),	(MODE(0) | PULLDOWN_EN)},	   /* BE_CLE */
 	{-1},
 };
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
-	{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */

It _looks_ like this is jsut whitespace only. Since that doesn't match the rest of the file, please don't do that.

Will be fixed in next version of this patch.

Quoted 16 lines

[snip]

Quoted 15 lines

#endif

#if defined(CONFIG_NOR_BOOT)

(quoted diff) +0 -12
-static struct module_pin_mux norboot_pin_mux[] = {
-	{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
-	{-1},
-};
Quoted 9 lines

Review

Quoted 5 lines
(quoted diff) +1 -2
-
 void enable_norboot_pin_mux(void)
 {
-	configure_module_pin_mux(norboot_pin_mux);
+	configure_module_pin_mux(bone_norcape_pin_mux);

Did you boot test this? The system requirements here are a bit strict and I don't know if we can just do what you're doing here...

Yes, this one is also tested on Beaglebone-Black with following change in boards.cfg to enable NOR on Beaglebone-Black

boards.cfg +0 -0
-Active  arm         armv7          am33xx      ti              am335x              am335x_boneblack                      am335x_evm:SERIAL1,CO
+Active  arm         armv7          am33xx      ti              am335x              am335x_boneblack                      am335x_evm:SERIAL1,CO

---------------------
U-Boot SPL 2014.07-00012-g0e5512a-dirty (Jul 21 2014 - 15:38:26) reading u-boot.img
reading u-boot.img

U-Boot 2014.07-00012-g0e5512a-dirty (Jul 21 2014 - 15:38:26)

I2C:   ready
DRAM:  512 MiB
Flash: 16 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1

Using default environment

Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 1  0
U-Boot#
U-Boot# flinfo

Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 128 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x227E2100 Advanced Sector Protection (PPB) enabled
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 1 ms, buffer size: 64 bytes

Sector Start Addresses:

  08000000   RO   08020000   RO   08040000   RO   08060000   RO   08080000   RO 
  080A0000   RO   080C0000   RO   080E0000   RO   08100000   RO   08120000   RO 
...
  08E60000   RO   08E80000   RO   08EA0000   RO   08EC0000   RO   08EE0000   RO 
  08F00000   RO   08F20000   RO   08F40000   RO   08F60000   RO   08F80000   RO 
  08FA0000   RO   08FC0000   RO   08FE0000   RO

U-Boot#
---------------------

with regards, pekon

author
#11 lore raw

PATCH 5/7 board/ti/am335x: update configs for parallel NAND

In reply to Pekon Gupta

This patch
- consolidate CONFIG_SYS_NAND_xx and CONFIG_SPL_NAND_xx from various configuration files into single file.
- update MTD Partition table to match AM335x_EVM DT in linux-kernel
- segregate CONFIGs based on different boot modes (like SPL and U-Boot)

Signed-off-by Pekon Gupta <[email protected]>
---
 include/configs/am335x_evm.h | 61 ++++++++++++++++++++++----------------------
 1 file changed, 31 insertions(+), 30 deletions(-)
include/configs/am335x_evm.h +31 -30
index 57a6cab..4f8ed2f 100644
@@ -61,7 +61,7 @@
 		"${optargs} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype}\0" \
-	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
 	"nandrootfstype=ubifs rootwait=1\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \

@@ -229,18 +229,23 @@
 #define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
 
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+#endif
 
+/* NAND support */
 #ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_NAND_OMAP_ELM
-#define CONFIG_SPL_NAND_AM33XX_BCH
 /* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
-					 CONFIG_SYS_NAND_PAGE_SIZE)
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
 #define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \

@@ -252,17 +257,30 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define MTDIDS_DEFAULT			"nand0=nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
+					"128k(NAND.SPL)," \
+					"128k(NAND.SPL.backup1)," \
+					"128k(NAND.SPL.backup2)," \
+					"128k(NAND.SPL.backup3)," \
+					"256k(NAND.u-boot-spl-os)," \
+					"1m(NAND.u-boot)," \
+					"128k(NAND.u-boot-env)," \
+					"128k(NAND.u-boot-env.backup1)," \
+					"8m(NAND.kernel)," \
+					"-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
 #ifdef CONFIG_SPL_OS_BOOT
   #define CONFIG_CMD_SPL_NAND_OFS	0x00080000 /* os parameters */
   #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
   #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
 #endif
-#endif
-#endif
+#endif /* !CONFIG_NAND */
 
 /*
  * For NOR boot, we must set this to the start of where NOR is mapped

@@ -419,23 +437,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
-/* NAND support */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_NAND
-#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
-#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \
-					"128k(SPL.backup1)," \
-					"128k(SPL.backup2)," \
-					"128k(SPL.backup3),1792k(u-boot)," \
-					"128k(u-boot-spl-os)," \
-					"128k(u-boot-env),5m(kernel),-(rootfs)"
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#endif
-#endif
-
 /*
  * NOR Size = 16 MiB
  * Number of Sectors/Blocks = 128
Signature · 1 line
1.8.5.1.163.gd7aced9
author
#12 lore raw

PATCH 6/7 board/ti/am43xx: add support for parallel NAND

In reply to Pekon Gupta

This patch adds support for NAND device connected to GPMC chip-select on following AM43xx EVM boards.

am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
time either eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled by:
(a) Statically using Jumper on connecter (J89) present on board.
(a) If Jumper on J89 is NOT used, then selection can be dynamically controlled

      by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
      SPI2_CS0 == 0: NAND (default)
      SPI2_CS0 == 1: eMMC

am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
Thus only one of the two can be used at a time. Selection is controlled by:
(a) Dynamically driving following GPIO pin from software

      GPMC_A0(GPIO) == 0 NAND is selected (default)

NAND device (MT29F4G08AB) on these boards has:
- data-width=8bits
- blocksize=256KB
- pagesize=4KB
- oobsize=224 bytes
For above NAND device, ROM code expects the boot-loader to be flashed in BCH16 ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.

Signed-off-by Pekon Gupta <[email protected]>
---
 board/ti/am43xx/board.c      |  1 +
 board/ti/am43xx/mux.c        | 42 ++++++++++++++++++++++++++
 boards.cfg                   |  2 +-
 include/configs/am43xx_evm.h | 70 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 114 insertions(+), 1 deletion(-)
board/ti/am43xx/board.c +1 -0
index 054a452..2c3a290 100644
@@ -487,6 +487,7 @@ void sdram_init(void)
 int board_init(void)
 {
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
 
 	return 0;
 }
board/ti/am43xx/mux.c +42 -0

66 lines not on this page · raw message

boards.cfg +1 -1
index 8e2db82..52aeb7f 100644
@@ -274,7 +274,7 @@ Active  arm         armv7          am33xx      ti              am335x
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                      am335x_evm:SERIAL5,CONS_INDEX=5,NAND                                                                                              Tom Rini <[email protected]>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                      am335x_evm:SERIAL6,CONS_INDEX=6,NAND                                                                                              Tom Rini <[email protected]>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_usbspl                     am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT                                                                           Tom Rini <[email protected]>
-Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                            am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   Lokesh Vutla <[email protected]>
+Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                            am43xx_evm:SERIAL1,CONS_INDEX=1,NAND                                                                                              Lokesh Vutla <[email protected]>
 Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm_qspiboot                   am43xx_evm:SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT                                                                                    Lokesh Vutla <[email protected]>
 Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                            -                                                                                                                                 Matt Porter <[email protected]>
 Active  arm         armv7          am33xx      ti              ti816x              ti816x_evm                            -                                                                                                                                 -
include/configs/am43xx_evm.h +70 -0

74 lines not on this page · raw message

Signature · 1 line
1.8.5.1.163.gd7aced9
#13 lore raw

PATCH 6/7 board/ti/am43xx: add support for parallel NAND

Quoted 2 lines · Pekon Gupta

This patch adds support for NAND device connected to GPMC chip-select on following AM43xx EVM boards.

[snip]

Quoted 4 lines
board/ti/am43xx/mux.c +0 -0
index 50967e1..172adcd 100644

[snip]

Quoted 4 lines
board/ti/am43xx/mux.c +0 -0
@@ -97,12 +128,23 @@ void enable_board_pin_mux(void)
 	if (board_is_gpevm()) {
 		configure_module_pin_mux(gpio5_7_pin_mux);
 		configure_module_pin_mux(rgmii1_pin_mux);

board/ti/am43xx/mux.c void enable_board_pin_mux(void) · line 140

Quoted 10 lines
board/ti/am43xx/mux.c +7 -0
+#if defined(CONFIG_NAND)
+		configure_module_pin_mux(nand_pin_mux);
+#endif
 	} else if (board_is_sk()) {
 		configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+		pr_err("NAND flash is not present on this board\n");
+#else
 		configure_module_pin_mux(qspi_pin_mux);
+#endif

No, this breaks EVM-SK booting now in the normal case.

boards.cfg Active arm armv7 am33xx ti am335x · line 280

Quoted 13 lines
boards.cfg +1 -1
index 8e2db82..52aeb7f 100644
@@ -274,7 +274,7 @@ Active  arm         armv7          am33xx      ti              am335x
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                      am335x_evm:SERIAL5,CONS_INDEX=5,NAND                                                                                              Tom Rini <[email protected]>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                      am335x_evm:SERIAL6,CONS_INDEX=6,NAND                                                                                              Tom Rini <[email protected]>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_usbspl                     am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT                                                                           Tom Rini <[email protected]>
-Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                            am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   Lokesh Vutla <[email protected]>
+Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                            am43xx_evm:SERIAL1,CONS_INDEX=1,NAND                                                                                              Lokesh Vutla <[email protected]>
 Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm_qspiboot                   am43xx_evm:SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT                                                                                    Lokesh Vutla <[email protected]>
 Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                            -                                                                                                                                 Matt Porter <[email protected]>
 Active  arm         armv7          am33xx      ti              ti816x              ti816x_evm                            -                                                                                                                                 -

I don't like this. We're making the normal build only work on boards with NAND, and defaulting to NAND being there, which is not the most common case.

Quoted 4 lines
include/configs/am43xx_evm.h +0 -0
index 974ce98..22c9019 100644

[snip]

include/configs/am43xx_evm.h line 323

Quoted 2 lines
include/configs/am43xx_evm.h +2 -0
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND

NAK. I'd like to see us default to environment being a file in the FAT filesystem on SD card and specific boot builds going elsewhere (_qspiboot in QSPI, adding in a _nand build that assumes / requires NAND, puts env there).

include/configs/am43xx_evm.h line 334

Quoted 11 lines
include/configs/am43xx_evm.h +11 -0
+/* NAND: SPL related configs */
+#if defined(CONFIG_SPL_NAND_SUPPORT)
+  /* NAND: SPL falcon mode configs */
+  #ifdef CONFIG_SPL_OS_BOOT
+    #undef CONFIG_SPL_OS_BOOT
+    #define CONFIG_CMD_SPL_NAND_OFS		0x00100000 /* os parameters */
+    #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00300000 /* kernel offset */
+    #define CONFIG_CMD_SPL_WRITE_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+  #endif
+#endif
+#endif /* !CONFIG_NAND */

No extra spacing, thanks.

Signature · 8 lines
Tom
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author
#14 lore raw

PATCH 7/7 board/ti/dra7xx: add support for parallel NAND

In reply to Pekon Gupta

This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch, So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH

Signed-off-by Pekon Gupta <[email protected]>
---
 board/ti/dra7xx/mux_data.h   | 30 +++++++++++++++++++++++
 boards.cfg                   |  2 +-
 include/configs/dra7xx_evm.h | 58 +++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 88 insertions(+), 2 deletions(-)
board/ti/dra7xx/mux_data.h +30 -0
index 38de9d5..697e9e4 100644
@@ -51,6 +51,35 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RGMII0_RXD2, (IEN | M0) },
 	{RGMII0_RXD1, (IEN | M0) },
 	{RGMII0_RXD0, (IEN | M0) },
+#ifdef CONFIG_NAND
+	/* NAND / NOR pin-mux */
+	{GPMC_AD0 , M0 | IEN | PDIS}, /* AD0  */
+	{GPMC_AD1 , M0 | IEN | PDIS}, /* AD1  */
+	{GPMC_AD2 , M0 | IEN | PDIS}, /* AD2  */
+	{GPMC_AD3 , M0 | IEN | PDIS}, /* AD3  */
+	{GPMC_AD4 , M0 | IEN | PDIS}, /* AD4  */
+	{GPMC_AD5 , M0 | IEN | PDIS}, /* AD5  */
+	{GPMC_AD6 , M0 | IEN | PDIS}, /* AD6  */
+	{GPMC_AD7 , M0 | IEN | PDIS}, /* AD7  */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+	{GPMC_AD8 , M0 | IEN | PDIS}, /* AD8  */
+	{GPMC_AD9 , M0 | IEN | PDIS}, /* AD9  */
+	{GPMC_AD10, M0 | IEN | PDIS}, /* AD10 */
+	{GPMC_AD11, M0 | IEN | PDIS}, /* AD11 */
+	{GPMC_AD12, M0 | IEN | PDIS}, /* AD12 */
+	{GPMC_AD13, M0 | IEN | PDIS}, /* AD13 */
+	{GPMC_AD14, M0 | IEN | PDIS}, /* AD14 */
+	{GPMC_AD15, M0 | IEN | PDIS}, /* AD15 */
+#endif
+	{GPMC_CS0,	M0 | IDIS | PEN | PTU}, /* chip-select */
+	{GPMC_ADVN_ALE,	M0 | IDIS | PEN | PTD}, /* Addr latch */
+	{GPMC_OEN_REN,	M0 | IDIS | PEN | PTD}, /* Read enable */
+	{GPMC_WEN,	M0 | IDIS | PEN | PTU}, /* Write enable_n */
+	{GPMC_BEN0,	M0 | IDIS | PEN | PTD}, /* Byte/Column En */
+	{GPMC_WAIT0,	M0 | IEN  | PEN | PTU}, /* Wait/Ready */
+	/* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
+#else
+	/* QSPI pin-mux */
 	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
 	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
 	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */

@@ -61,6 +90,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
 	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
 	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
+#endif /* CONFIG_NAND */
 	{USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
boards.cfg +1 -1
index 52aeb7f..1cc0e94 100644
@@ -361,7 +361,7 @@ Active  arm         armv7          omap4       gumstix         duovero
 Active  arm         armv7          omap4       ti              panda               omap4_panda                           -                                                                                                                                 Sricharan R <[email protected]>
 Active  arm         armv7          omap4       ti              sdp4430             omap4_sdp4430                         -                                                                                                                                 Sricharan R <[email protected]>
 Active  arm         armv7          omap5       compulab        cm_t54              cm_t54                                -                                                                                                                                 Dmitry Lifshitz <[email protected]>
-Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                            dra7xx_evm:CONS_INDEX=1                                                                                                           Lokesh Vutla <[email protected]>
+Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                            dra7xx_evm:CONS_INDEX=1,NAND                                                                                                      Lokesh Vutla <[email protected]>
 Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm_qspiboot                   dra7xx_evm:CONS_INDEX=1,QSPI_BOOT                                                                                                 Lokesh Vutla <[email protected]>
 Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm_uart3                      dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT                                                                                        Lokesh Vutla <[email protected]>
 Active  arm         armv7          omap5       ti              omap5_uevm          omap5_uevm                            -                                                                                                                                 -
include/configs/dra7xx_evm.h +57 -1

68 lines not on this page · raw message

Signature · 1 line
1.8.5.1.163.gd7aced9
#15 lore raw

PATCH 7/7 board/ti/dra7xx: add support for parallel NAND

Quoted 6 lines · Pekon Gupta

This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch, So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH

First, again, I don't like moving towards NAND being the default assumed present storage and making QSPI harder to use. Second, I forgot about this earlier but for the record and per later emails, we should just use CONFIG_CMD_NAND rather than CONFIG_NAND.

include/configs/dra7xx_evm.h line 19

Quoted 11 lines

index 8d0a0eb..9e6a565 100644

include/configs/dra7xx_evm.h +1 -1
@@ -14,7 +14,7 @@
 
 #define CONFIG_DRA7XX
 
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_NAND)
 /* MMC ENV related defines */
 #define CONFIG_ENV_IS_IN_MMC

We want to keep the default env location to be on the eMMC.

include/configs/dra7xx_evm.h line 199

Quoted 9 lines
include/configs/dra7xx_evm.h +9 -0
+/* NAND: SPL related configs */
+#if defined(CONFIG_SPL_NAND_SUPPORT)
+  /* NAND: SPL falcon mode configs */
+  #ifdef CONFIG_SPL_OS_BOOT
+    #define CONFIG_CMD_SPL_NAND_OFS		0x00080000 /* os-boot params*/
+    #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+    #define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
+  #endif
+#endif

No leading spaces.

Thanks.

Signature · 8 lines
Tom
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#16 lore raw

PATCH 7/7 board/ti/dra7xx: add support for parallel NAND

Quoted 10 lines

From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom

Quoted 8 lines · Pekon Gupta

This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch, So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH

Quoted 5 lines

First, again, I don't like moving towards NAND being the default assumed present storage and making QSPI harder to use. Second, I forgot about this earlier but for the record and per later emails, we should just use CONFIG_CMD_NAND rather than CONFIG_NAND.

All your feedbacks taken, except below one which is bit trivial ..

Converting CONFIG_NAND to CONFIG_CMD_NAND need review because:
(1) CONFIG_NAND has spread to so many files, and is also part of include/configs/ti_armv7_common.h arch/arm/cpu/armv7/omap-common/mem.c
And many more places..

(2) CONFIG_CMD_NAND is not synonymous with other CONFIG_xx which used for enabling complete subsystem like CONFIG_NOR, CONFIG_MMC.

So, for now I'll continue using CONFIG_NAND, and may be later if CONFIG_NAND needs to be deprecated, then it can come as separate patch series. Hope that is fine?

with regards, pekon

#17 lore raw

PATCH 7/7 board/ti/dra7xx: add support for parallel NAND

Quoted 23 lines · Pekon
Quoted 10 lines

From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom

Quoted 8 lines · Pekon Gupta

This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch, So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH

Quoted 5 lines

First, again, I don't like moving towards NAND being the default assumed present storage and making QSPI harder to use. Second, I forgot about this earlier but for the record and per later emails, we should just use CONFIG_CMD_NAND rather than CONFIG_NAND.

All your feedbacks taken, except below one which is bit trivial ..

Converting CONFIG_NAND to CONFIG_CMD_NAND need review because:
(1) CONFIG_NAND has spread to so many files, and is also part of include/configs/ti_armv7_common.h arch/arm/cpu/armv7/omap-common/mem.c
And many more places..

Quoted 6 lines

(2) CONFIG_CMD_NAND is not synonymous with other CONFIG_xx which used for enabling complete subsystem like CONFIG_NOR, CONFIG_MMC.

So, for now I'll continue using CONFIG_NAND, and may be later if CONFIG_NAND needs to be deprecated, then it can come as separate patch series. Hope that is fine?

OK, I can live with that for now, thanks.

Signature · 8 lines
Tom
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#18 lore raw

cover TI: armv7: add parallel NAND support

In reply to Pekon Gupta

Hi Pekon,

Quoted 9 lines · Pekon Gupta

This patch series adds support for parallel NAND devices support connected via GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms. This series also moves some board specific CONFIG_NAND_xx from generic files to individual files.

Tested using: ./MAKEALL -s am33xx -s omap3 -s oamp4 -s omap5
works fine except for am335x_boneblack_vboot
build breaks for am335x_boneblack_vboot for un-related reasons
u-boot/scripts/dtc-version.sh: line 17: dtc: command not found

This is obvious, apparently beagle bone black wants to use the DT for U-Boot and you don't have dtc installed or it is not in your PATH.

Quoted 33 lines

Pekon Gupta (7):
TI: armv7: move board specific NAND configs out from ti_armv7_common.h

    and ti_am335x_common.h

board/ti/am335x: add support for beaglebone NAND cape
arm: lib: continue board_init_r even if valid flash device is not
detected
board/ti/am335x: add support for beaglebone NOR Cape board/ti/am335x: update configs for parallel NAND board/ti/am43xx: add support for parallel NAND board/ti/dra7xx: add support for parallel NAND

 arch/arm/lib/board.c               |   7 +-
 board/ti/am335x/mux.c              | 149 ++++++++++++++++++-------------------
 board/ti/am43xx/board.c            |   1 +
 board/ti/am43xx/mux.c              |  42 +++++++++++
 board/ti/dra7xx/mux_data.h         |  30 ++++++++
 boards.cfg                         |   4 +-
 doc/README.nand                    |  12 +++
 include/configs/am335x_evm.h       |  64 +++++++++-------
 include/configs/am43xx_evm.h       |  70 +++++++++++++++++
 include/configs/cm_t335.h          |  10 +++
 include/configs/dra7xx_evm.h       |  58 ++++++++++++++-
 include/configs/omap3_beagle.h     |   6 ++
 include/configs/omap3_igep00x0.h   |   9 +++
 include/configs/omap3_overo.h      |   8 ++
 include/configs/omap3_zoom1.h      |   7 ++
 include/configs/pengwyn.h          |   7 ++
 include/configs/ti_am335x_common.h |   4 -
 include/configs/ti_armv7_common.h  |   9 ---
 18 files changed, 369 insertions(+), 128 deletions(-)
Signature · 2 lines
Regards,
Igor.
#19 lore raw

cover TI: armv7: add parallel NAND support

Quoted 9 lines

From: Igor Grinberg [mailto:grinberg at compulab.co.il] Hi Pekon,

Quoted 5 lines · Pekon Gupta

This patch series adds support for parallel NAND devices support connected via GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms. This series also moves some board specific CONFIG_NAND_xx from generic files to individual files.

Quoted 8 lines
Quoted 4 lines

Tested using: ./MAKEALL -s am33xx -s omap3 -s oamp4 -s omap5
works fine except for am335x_boneblack_vboot
build breaks for am335x_boneblack_vboot for un-related reasons
u-boot/scripts/dtc-version.sh: line 17: dtc: command not found

This is obvious, apparently beagle bone black wants to use the DT for U-Boot and you don't have dtc installed or it is not in your PATH.

Yes, my bad. I was expecting dtc to be part of $UBOOT/scripts/... as in linux.
' am335x_boneblack_vboot' builds cleanly after I fix my $PATH to point to linux kernel dtc.
------------------
Configuring for am335x_boneblack_vboot - Board: am335x_evm, Options: SERIAL1,CONS_INDEX=1,EMMC_BOOT,ENABLE_VBOOT
text data bss dec hex filename
367622 12722 8693820 9074164 8a75f4 ./u-boot
72795 3084 198024 273903 42def ./spl/u-boot-spl
------------------

One request, as [PATCH 1/7] touches some non-TI board configs,
So some tested-by would help here to confirm that this patch isn't breaking anything.

with regards, pekon