arm, imx6: add aristainetos board support
v4 cover arm, imx6: add aristainetos board support
add support for the imx6 based aristainetos board.
- changes for v2:
- added comments from Jagan Teki and Stefano Babic
- remove patch http://patchwork.ozlabs.org/patch/353324/
- new patches in v2
imx6: add gpr2 usb_otg_id iomux select control define (as patch http://patchwork.ozlabs.org/patch/353324/
is removed in v2)
i.MX6: define struct pwm_regs and PWMCR_* defines (as splash screen support added for this board)
- changes for v3
- remove patch
http://patchwork.ozlabs.org/patch/369530/
from this patchserie, as Jagannadha Sutradharudu Teki applied it to u-boot-spi/master
- new patch:
spi: add config option to enable the WP pin function on st micron flashes as Stefano Babic suggested to move this to common code
- new patch:
pwm, imx6: add support for pwm modul on imx6 as Stefano Babic suggested to move this to common code
- changes for v4:
- pwm, imx6: add support for pwm modul on imx6 patch
- add Acked-by from Stefano Babic
- add in the commit message the commit ID from linux on which pieces of the code is based.
- add comment from Wolfgang Denk:
- move code which is based from linux into a seperate new file drivers/pwm/pwm-imx-util.c, so this can be with the GPL-2.0 license, and the code not taken from linux can be in GPL-2.0+
- arm-imx6-add-aristainetos-board.patch
- add comment from Stefano Babic:
- remove board_late_init()
- remove unnecessary ifdef in board config file
Heiko Schocher (6):
imx6: add gpr2 usb_otg_id iomux select control define i.MX6: define struct pwm_regs and PWMCR_* defines
pwm, imx6: add support for pwm modul on imx6
i.MX6: add enable_spi_clk()
spi: add config option to enable the WP pin function on st micron
flashes
arm, imx6: add aristainetos board
README | 15 + arch/arm/cpu/armv7/mx6/clock.c | 18 ++ arch/arm/include/asm/arch-mx6/clock.h | 1 + arch/arm/include/asm/arch-mx6/imx-regs.h | 19 ++ board/aristainetos/Makefile | 9 + board/aristainetos/aristainetos.c | 519 +++++++++++++++++++++++++++++++ board/aristainetos/aristainetos.cfg | 33 ++ board/aristainetos/clocks.cfg | 24 ++ board/aristainetos/ddr-setup.cfg | 61 ++++ board/aristainetos/mt41j128M.cfg | 70 +++++ boards.cfg | 1 + drivers/Makefile | 1 + drivers/mtd/spi/sf_internal.h | 4 + drivers/mtd/spi/sf_probe.c | 30 ++ drivers/pwm/Makefile | 13 + drivers/pwm/pwm-imx-util.c | 73 +++++ drivers/pwm/pwm-imx-util.h | 16 + drivers/pwm/pwm-imx.c | 59 ++++ include/configs/aristainetos.h | 325 +++++++++++++++++++ 19 files changed, 1291 insertions(+) create mode 100644 board/aristainetos/Makefile create mode 100644 board/aristainetos/aristainetos.c create mode 100644 board/aristainetos/aristainetos.cfg create mode 100644 board/aristainetos/clocks.cfg create mode 100644 board/aristainetos/ddr-setup.cfg create mode 100644 board/aristainetos/mt41j128M.cfg create mode 100644 drivers/pwm/Makefile create mode 100644 drivers/pwm/pwm-imx-util.c create mode 100644 drivers/pwm/pwm-imx-util.h create mode 100644 drivers/pwm/pwm-imx.c create mode 100644 include/configs/aristainetos.h
Signature · 1 line
1.8.3.1
PATCH v4 1/6 imx6: add gpr2 usb_otg_id iomux select control define
add IOMUXC_GPR1_USB_OTG_ID_OFFSET and IOMUXC_GPR1_USB_OTG_ID_SEL_MASK define for the USB_OTG_ID_SEL bit.
---
- changes for v2:
- new
- changes for v3:
add Acked-by from Stefano Babic
- changes for v4:
none
arch/arm/include/asm/arch-mx6/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/include/asm/arch-mx6/imx-regs.h +2 -0
@@ -251,6 +251,8 @@ struct src {/* GPR1 bitfields */ #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) +#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 +#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)/* GPR3 bitfields */ #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
Signature · 1 line
1.8.3.1
PATCH v4 2/6 i.MX6: define struct pwm_regs and PWMCR_* defines
In reply to Heiko Schocheradd defines for pwm modul found on imx6.
---
- changes for v2:
- new
- changes for v3:
none
- changes for v4:
none
arch/arm/include/asm/arch-mx6/imx-regs.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm/include/asm/arch-mx6/imx-regs.h +16 -0
@@ -669,5 +669,21 @@ struct wdog_regs {u16 wmcr;/* Miscellaneous Control */ }; +#define PWMCR_PRESCALER (x) (((x - 1) & 0xFFF) << 4) +#define PWMCR_DOZEEN (1 << 24) +#define PWMCR_WAITEN (1 << 23) +#define PWMCR_DBGEN (1 << 22) +#define PWMCR_CLKSRC_IPG_HIGH (2 << 16) +#define PWMCR_CLKSRC_IPG (1 << 16) +#define PWMCR_EN (1 << 0) + +struct pwm_regs { +u32 cr; +u32 sr; +u32 ir; +u32 sar; +u32 pr; +u32 cnr; +};#endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
Signature · 1 line
1.8.3.1
PATCH v4 3/6 pwm, imx6: add support for pwm modul on imx6
In reply to Heiko Schocheradd basic support for the pwm modul found on imx6.
Pieces of this code are based on linux code from drivers/pwm/pwm-imx.c Commit "cd3de83f1476 Linux 3.16-rc4"
---
- changes for v3:
new in v3, as Stefano Babic suggested
- changes for v4:
- add Acked-by from Stefano Babic
- add in the commit message the commit ID from linux on which pieces the code is based.
- add comment from Wolfgang Denk:
- move code which is based from linux into a seperate new file drivers/pwm/pwm-imx-util.c, so this can be with the GPL-2.0 license, and the code not taken from linux can be in GPL-2.0+
README | 4 +++ drivers/Makefile | 1 + drivers/pwm/Makefile | 13 +++++++++ drivers/pwm/pwm-imx-util.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/pwm/pwm-imx-util.h | 16 ++++++++++ drivers/pwm/pwm-imx.c | 59 +++++++++++++++++++++++++++++++++++++ 6 files changed, 166 insertions(+) create mode 100644 drivers/pwm/Makefile create mode 100644 drivers/pwm/pwm-imx-util.c create mode 100644 drivers/pwm/pwm-imx-util.h create mode 100644 drivers/pwm/pwm-imx.c
README +4 -0
@@ -1377,6 +1377,10 @@ The following options need to be configured: CONFIG_SH_ETHER_CACHE_WRITEBACK If this option is set, the driver enables cache flush. +- PWM Support: + CONFIG_PWM_IMX + Support for PWM modul on the imx6. + - TPM Support: CONFIG_TPM Support TPM devices.
drivers/Makefile +1 -0
@@ -15,3 +15,4 @@ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ obj-y += memory/ +obj-y += pwm/
drivers/pwm/Makefile new file +13 -0
@@ -0,0 +1,13 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen at mindspring.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#ccflags-y += -DDEBUG + +obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
drivers/pwm/pwm-imx-util.c new file +73 -0
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drivers/pwm/pwm-imx-util.h new file +16 -0
@@ -0,0 +1,16 @@ +/* +* (C) Copyright 2014 +* Heiko Schocher, DENX Software Engineering, hs at denx.de. +* +* Basic support for the pwm modul on imx6. +* +* SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef _pwm_imx_util_h_ +#define _pwm_imx_util_h_ + +struct pwm_regs *pwm_id_to_reg (int pwm_id); +int pwm_imx_get_parms (int period_ns,int duty_ns,unsigned long *period_c, +unsigned long *duty_c,unsigned long *prescale); +#endif
drivers/pwm/pwm-imx.c new file +59 -0
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Signature · 1 line
1.8.3.1
PATCH v4 4/6 i.MX6: add enable_spi_clk()
In reply to Heiko Schocheradd enable_spi_clk(), so board code can enable spi clocks.
---
- changes for v2:
- add comment from Stefano Babic:
- add comment for spi_num range
- add SPI_MAX_NUM in imx-regs.h
- changes for v3:
- add Reviewed-by from Jagannadha Sutradharudu Teki
- changes for v4:
none
arch/arm/cpu/armv7/mx6/clock.c | 18 ++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 1 + arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + 3 files changed, 20 insertions(+)
arch/arm/cpu/armv7/mx6/clock.c +18 -0
@@ -71,6 +71,24 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) }#endif +/* spi_num can be from 0 - SPI_MAX_NUM */ +int enable_spi_clk (unsigned char enable,unsigned spi_num) +{ +u32 reg; +u32 mask; + +if (spi_num >SPI_MAX_NUM ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (spi_num <<1 ); + reg =__raw_readl (&imx_ccm->CCGR1); +if (enable) + reg |= mask; +else + reg &= ~mask; +__raw_writel (reg, &imx_ccm->CCGR1); +return 0 ; +}static u32 decode_pll (enum pll_clocks pll,u32 infreq) {u32 div;
arch/arm/include/asm/arch-mx6/clock.h +1 -0
@@ -57,6 +57,7 @@ void enable_usboh3_clk(unsigned char enable);int enable_sata_clock (void );int enable_pcie_clock (void );int enable_i2c_clk (unsigned char enable,unsigned i2c_num); +int enable_spi_clk (unsigned char enable,unsigned spi_num);void enable_ipu_clock (void );int enable_fec_anatop_clock (enum enet_freq freq);#endif /* __ASM_ARCH_CLOCK_H */
arch/arm/include/asm/arch-mx6/imx-regs.h +1 -0
@@ -405,6 +405,7 @@ struct cspi_regs {#define MXC_CSPICTRL_RXOVF (1 << 6)#define MXC_CSPIPERIOD_32KHZ (1 << 15)#define MAX_SPI_BYTES 32 +#define SPI_MAX_NUM 4/* Bit position inside CTRL register to be associated with SS */ #define MXC_CSPICTRL_CHAN 18
Signature · 1 line
1.8.3.1
PATCH v4 5/6 spi: add config option to enable the WP pin function on st micron flashes
In reply to Heiko Schocherenable the W#/Vpp signal to disable writing to the status register on ST MICRON flashes like the N25Q128 thorugh the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
---
- changes for v4:
none
README | 11 +++++++++++ drivers/mtd/spi/sf_internal.h | 4 ++++ drivers/mtd/spi/sf_probe.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+)
README +11 -0
@@ -2937,6 +2937,17 @@ CBFS (Coreboot Filesystem) support CONFIG_SPI_FLASH_MTD add MTD translation layer driver. + CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + enable the W#/Vpp signal to disable writing to the status + register on ST MICRON flashes like the N25Q128. + The status register write enable/disable bit, combined with + the W#/VPP signal provides hardware data protection for the + device as follows: When the enable/disable bit is set to 1, + and the W#/VPP signal is driven LOW, the status register + nonvolatile bits become read-only and the WRITE STATUS REGISTER + operation will not execute. The only way to exit this + hardware-protected mode is to drive W#/VPP HIGH. + - SystemACE Support: CONFIG_SYSTEMACE
drivers/mtd/spi/sf_internal.h +4 -0
@@ -60,6 +60,10 @@#define STATUS_QEB_MXIC (1 << 6)#define STATUS_PEC (1 << 7) +#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN +#define STATUS_SRWD (1 << 7)/* SR write protect */ +#endif +/* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
drivers/mtd/spi/sf_probe.c +30 -0
@@ -281,6 +281,34 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) }#endif /* CONFIG_OF_CONTROL */ +#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN +/* enable the W#/Vpp signal to disable writing to the status register */ +static int spi_enable_wp_pin (struct spi_flash *flash) +{ +u8 status; +int ret; + + ret =spi_flash_cmd_read_status (flash, &status); +if (ret <0 ) +return ret; + + ret =spi_flash_cmd_write_status (flash,STATUS_SRWD ); +if (ret <0 ) +return ret; + + ret =spi_flash_cmd_write_disable (flash); +if (ret <0 ) +return ret; + +return 0 ; +} +#else +static int spi_enable_wp_pin (struct spi_flash *flash) +{ +return 0 ; +} +#endif +static struct spi_flash *spi_flash_probe_slave (struct spi_slave *spi) {struct spi_flash *flash =NULL ;
@@ -351,6 +379,8 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi) puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); }#endif +if (spi_enable_wp_pin (flash)) +puts ("Enable WP pin failed\n" );/* Release spi bus */ spi_release_bus (spi);
Signature · 1 line
1.8.3.1
PATCH v4 6/6 arm, imx6: add aristainetos board
In reply to Heiko SchocherCPU: Freescale i.MX6DL rev1.1 at 792 MHz Board: aristaitenos I2C: ready DRAM: 1 GiB NAND: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lb07wv8 (800x480)
- UART5 is console
- MMC 0 and 1
- USB 0 and 1
- boot from mmc0 and spi nor flash
- Splash screen support
---
- changes for v2:
- change MUX_PAD_CTRL value for MX6_PAD_GPIO_16__ENET_REF_CLK
- set cs1 from ecspi4 to high
- add splash screen support
- add comment from Stefano babic:
- remove mxc_iomux_set_gpr_register instead use setbits_le32 remove patch http://patchwork.ozlabs.org/patch/353324/
from this patchserie, as no longer needed
- use for loop for calling enable_spi_clk()
- simplify board_mmc_getcd()
- simplify board_mmc_init()
- remove board_phy_config()
- remove setup_fec() and work code into board_eth_init()
- use define for i2c slave address
- remove udelay in board_ehci_hcd_init()
- remove CONFIG_SPL_BUILD, as this board does not use CONFIG_SPL_BUILD
- changes for v3:
- add comment from Stefano Babic:
- simplify setup_iomux_uart()
- remove enable_spi()
- remove enable wp pin for the st micron flash from board code to spi driver. Enable this new config option only in board config file
- use common functions from pwm modul
- changes for v4:
- add comment from Stefano Babic:
- remove board_late_init()
- remove unnecessary ifdef in board config file
board/aristainetos/Makefile | 9 + board/aristainetos/aristainetos.c | 519 ++++++++++++++++++++++++++++++++++++ board/aristainetos/aristainetos.cfg | 33 +++ board/aristainetos/clocks.cfg | 24 ++ board/aristainetos/ddr-setup.cfg | 61 +++++ board/aristainetos/mt41j128M.cfg | 70 +++++ boards.cfg | 1 + include/configs/aristainetos.h | 325 ++++++++++++++++++++++ 8 files changed, 1042 insertions(+) create mode 100644 board/aristainetos/Makefile create mode 100644 board/aristainetos/aristainetos.c create mode 100644 board/aristainetos/aristainetos.cfg create mode 100644 board/aristainetos/clocks.cfg create mode 100644 board/aristainetos/ddr-setup.cfg create mode 100644 board/aristainetos/mt41j128M.cfg create mode 100644 include/configs/aristainetos.h
board/aristainetos/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <[email protected]> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := aristainetos.o
board/aristainetos/aristainetos.c new file +519 -0
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board/aristainetos/aristainetos.cfg new file +33 -0
@@ -0,0 +1,33 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs at denx.de. + * + * Based on: + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd + */ +BOOT_FROM spi + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "mt41j128M.cfg" +#include "clocks.cfg"
board/aristainetos/clocks.cfg new file +24 -0
@@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00c03f3f +DATA 4, CCM_CCGR1, 0x0030fcff +DATA 4, CCM_CCGR2, 0x0fffcfc0 +DATA 4, CCM_CCGR3, 0x3ff0300f +DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0f0000c3 +DATA 4, CCM_CCGR6, 0x000003ff
board/aristainetos/ddr-setup.cfg new file +61 -0
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board/aristainetos/mt41j128M.cfg new file +70 -0
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boards.cfg +1 -0
@@ -311,6 +311,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <[email protected]> +Active arm armv7 mx6 - aristainetos aristainetos aristainetos:IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL Heiko Schocher <[email protected]> Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <[email protected]> Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <[email protected]> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <[email protected]>
include/configs/aristainetos.h new file +325 -0
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Signature · 1 line
1.8.3.1
v4 cover arm, imx6: add aristainetos board support
In reply to Heiko SchocherHi Heiko,
On 18/07/2014 06:07, Heiko Schocher wrote:
All series applied with the following change due to inclusion Fabios's cleanup for iomuxc register (http://patchwork.ozlabs.org/patch/368335/)
int board_eth_init(bd_t *bis)
{
- struct iomuxc_base_regs *iomuxc_regs =
- (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *iomuxc_regs =
+ (struct iomuxc *)IOMUXC_BASE_ADDR;
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
Signature · 5 lines
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