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ODROID dynamic memory initialization

U-Boot New Daniel Drake 5 participants 10 messages Jul 22, 2014 – Sep 11, 2014

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Daniel Drake

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#0 lore raw

Hi Przemyslaw,

While looking at the old uboot from hardkernel, I'm curious about CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to run the memory at a high speed, by writing certain registers in the Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to 880MHz.

Your uboot patches don't seem to touch DMC regs like TIMINGROW, and also clock the MPLL at 800MHz.

I'm wondering if there is any reason for this? Wouldn't it be better to run at the faster speed like the vendor code does?

Thanks
Daniel

author
#1 lore raw
Quoted 8 lines · Daniel Drake

While looking at the old uboot from hardkernel, I'm curious about CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to run the memory at a high speed, by writing certain registers in the Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to 880MHz.

Your uboot patches don't seem to touch DMC regs like TIMINGROW, and also clock the MPLL at 800MHz.

I looked in more detail, and now understand better the SPL vs uboot division.

The vendor code I was referring to above is SPL code.

Since we are still using the same SPL as before, it means that MPLL and memory is already set up by the time the real/new uboot loads.

So I think there should be no need to modify MPLL, and I wonder if most of the other clock configuration code in your patches is also unnecessary.

Thoughts?

Thanks
Daniel

#2 lore raw

Hi Daniel,

Quoted 9 lines · Daniel Drake
Quoted 8 lines · Daniel Drake

While looking at the old uboot from hardkernel, I'm curious about CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to run the memory at a high speed, by writing certain registers in the Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to 880MHz.

Your uboot patches don't seem to touch DMC regs like TIMINGROW, and also clock the MPLL at 800MHz.

I used my private config from trats2 device, but there is Exynos4412 rev. 1.1 - DMC freq is 400MHz.
I need to check the 880Mhz value for the MPLL and I will give you an info.

Quoted 8 lines

I looked in more detail, and now understand better the SPL vs uboot division.

The vendor code I was referring to above is SPL code.

Since we are still using the same SPL as before, it means that MPLL and memory is already set up by the time the real/new uboot loads.

Quoted 9 lines

So I think there should be no need to modify MPLL, and I wonder if most of the other clock configuration code in your patches is also unnecessary.

Thoughts?

Thanks
Daniel

The BL2 is not a part of this patches, then maybe better is to configure the clocks for proper values by u-boot, moreover when I disable the clock configuration in u-boot then it can't boot - probably because of bad uart config and maybe some more.

Thank you for testing this code, but I don't have too much time for play with this config now.

I will test the MPLL with 880MHz tomorrow and it should be good enough, but next if dev freq will be enabled in the kernel - then probably DMC dividers will change without TIMINGROW change.

Thanks,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
#3 lore raw

PATCH 1/1 odroid: set MPLL clock to 880MHz

This patch changes MPLL from 800MHz to 880MHz on Odroid.

Signed-off-by Przemyslaw Marczak <[email protected]>
---
 board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
 1 file changed, 30 insertions(+), 30 deletions(-)
board/samsung/odroid/odroid.c +30 -30
index 2c5c107..b6f26ee 100644
@@ -195,8 +195,8 @@ static void board_clock_init(void)
 	while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
 		continue;
 
-	/* Set MPLL to 800MHz */
-	set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
+	/* Set MPLL to 880MHz */
+	set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1);
 
 	clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
 

@@ -220,15 +220,15 @@ static void board_clock_init(void)
 	      DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
 	/*
 	 * For:
-	 * MOUTdmc = 800 MHz
-	 * MOUTdphy = 800 MHz
+	 * MOUTdmc = 880 MHz
+	 * MOUTdphy = 880 MHz
 	 *
-	 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
-	 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
-	 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
-	 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
-	 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
-	 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
+	 * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3)
+	 * pclk_acp = aclk_acp / (ratio + 1) = 110 (1)
+	 * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1)
+	 * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1)
+	 * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1)
+	 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1)
 	 */
 	set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
 	      DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);

@@ -244,13 +244,13 @@ static void board_clock_init(void)
 	      C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
 	/*
 	 * For:
-	 * MOUTg2d = 800 MHz
-	 * MOUTc2c = 800 Mhz
+	 * MOUTg2d = 880 MHz
+	 * MOUTc2c = 880 Mhz
 	 * MOUTpwi = 108 MHz
 	 *
-	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
-	 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
-	 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
+	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1)
+	 * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1)
+	 * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1)
 	 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
 	 */
 	set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |

@@ -282,9 +282,9 @@ static void board_clock_init(void)
 	clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
 	      UART3_RATIO(15) | UART4_RATIO(15);
 	/*
-	 * For MOUTuart0-4: 800MHz
+	 * For MOUTuart0-4: 880MHz
 	 *
-	 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
+	 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7)
 	*/
 	set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
 	      UART3_RATIO(7) | UART4_RATIO(7);

@@ -298,12 +298,12 @@ static void board_clock_init(void)
 	clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
 	      MMC1_PRE_RATIO(255);
 	/*
-	 * For MOUTmmc0-3 = 800 MHz (MPLL)
+	 * For MOUTmmc0-3 = 880 MHz (MPLL)
 	 *
-	 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
-	 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
-	 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
-	 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
+	 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7)
+	 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1)
+	 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7)
+	 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1)
 	*/
 	set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
 	      MMC1_PRE_RATIO(1);

@@ -318,12 +318,12 @@ static void board_clock_init(void)
 	clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
 	      MMC3_PRE_RATIO(255);
 	/*
-	 * For MOUTmmc0-3 = 800 MHz (MPLL)
+	 * For MOUTmmc0-3 = 880 MHz (MPLL)
 	 *
-	 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
-	 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
-	 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
-	 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
+	 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7)
+	 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1)
+	 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7)
+	 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1)
 	*/
 	set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
 	      MMC3_PRE_RATIO(1);

@@ -337,10 +337,10 @@ static void board_clock_init(void)
 	/* CLK_DIV_FSYS3 */
 	clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
 	/*
-	 * For MOUTmmc4 = 800 MHz (MPLL)
+	 * For MOUTmmc4 = 880 MHz (MPLL)
 	 *
-	 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
-	 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
+	 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7)
+	 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0)
 	*/
 	set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
Signature · 1 line
1.9.1
#4 lore raw

PATCH 1/1 odroid: set MPLL clock to 880MHz

Hello Daniel,

Quoted 6 lines · Przemyslaw Marczak

This patch changes MPLL from 800MHz to 880MHz on Odroid.

Signed-off-by Przemyslaw Marczak <[email protected]>
---
  board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
  1 file changed, 30 insertions(+), 30 deletions(-)

Please apply this on the top of:
"[PATCH v6 00/12] Add support to Odroid U3/X2"

This change only one of MPLL divider and set the MPLL clock to 880. But such MPLL freq makes some other clocks issue.

In u-boot, the dw mmc driver sets wrong clock(probably some bug) and the emmc r/w performance is lower than before.
Kernel is booting the same as before. But most of clock values are not integers now.
I am not sure that everything will work fine.
Can you test in on your kernel?

Thank you,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
#6 lore raw

PATCH 1/1 odroid: set MPLL clock to 880MHz

Hello Minkyu,

Quoted 9 lines · Minkyu Kang
Quoted 7 lines · Przemyslaw Marczak

This patch changes MPLL from 800MHz to 880MHz on Odroid.

Signed-off-by Przemyslaw Marczak <[email protected]>
---
  board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
  1 file changed, 30 insertions(+), 30 deletions(-)
Quoted 6 lines

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

Thank you for applying the Odroid patch set.

I would like to note, that this one patch was intended for MR. Daniel just for his tests.

This patch breaks dw mmc performance:
e.g. eMMC uImage(fat) read performance:
- before this commit: 47.6 MiB/s
- after this commit: 13.0 MiB/s
So this requires some more changes in clocks and also in dw mmc driver.

And it can break some kernel clocks divider dependencies. It is not tested.

So please revert this patch.

Best Regards,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
#7 lore raw

PATCH 1/1 odroid: set MPLL clock to 880MHz

Quoted 28 lines · Przemyslaw Marczak

Hello Minkyu,

Quoted 9 lines · Minkyu Kang
Quoted 7 lines · Przemyslaw Marczak

This patch changes MPLL from 800MHz to 880MHz on Odroid.

Signed-off-by Przemyslaw Marczak <[email protected]>
---
  board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
  1 file changed, 30 insertions(+), 30 deletions(-)
Quoted 6 lines

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

Thank you for applying the Odroid patch set.

I would like to note, that this one patch was intended for MR. Daniel just for his tests.

This patch breaks dw mmc performance:
e.g. eMMC uImage(fat) read performance:
- before this commit: 47.6 MiB/s
- after this commit: 13.0 MiB/s
So this requires some more changes in clocks and also in dw mmc driver.

Quoted 6 lines

And it can break some kernel clocks divider dependencies. It is not tested.

So please revert this patch.

Best Regards,

reverted..

Thanks,
Minkyu Kang.

#8 lore raw

PATCH 1/1 odroid: set MPLL clock to 880MHz

Hi,

Quoted 21 lines · Minkyu Kang
Quoted 20 lines · Przemyslaw Marczak

Hello Minkyu,

Quoted 9 lines · Minkyu Kang
Quoted 7 lines · Przemyslaw Marczak

This patch changes MPLL from 800MHz to 880MHz on Odroid.

Signed-off-by Przemyslaw Marczak <[email protected]>
---
  board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++----------------------
  1 file changed, 30 insertions(+), 30 deletions(-)
Quoted 6 lines

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

Thank you for applying the Odroid patch set.

Quoted 7 lines
Quoted 7 lines

I would like to note, that this one patch was intended for MR. Daniel just for his tests.

This patch breaks dw mmc performance:
e.g. eMMC uImage(fat) read performance:
- before this commit: 47.6 MiB/s
- after this commit: 13.0 MiB/s
So this requires some more changes in clocks and also in dw mmc driver.

MPLL is used to the eMMC's source clock.
If MPLL is changed to 880MHz, then eMMC's clock should not be set to correct value. It has to test before changed MPLL clock. otherwise, we need to use other source clock.

Best Regards,
Jaehoon Chung

Quoted 17 lines
Quoted 7 lines

And it can break some kernel clocks divider dependencies. It is not tested.

So please revert this patch.

Best Regards,

reverted..

Thanks,
Minkyu Kang.
_______________________________________________
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U-Boot at lists.denx.de
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#9 lore raw

PATCH 1/1 odroid: set MPLL clock to 880MHz

Hi Jaehoon,

Quoted 35 lines

Hi,

Quoted 25 lines · Minkyu Kang
Quoted 24 lines · Przemyslaw Marczak

Hello Minkyu,

Quoted 10 lines · Minkyu Kang
Quoted 8 lines · Przemyslaw Marczak

This patch changes MPLL from 800MHz to 880MHz on Odroid.

Signed-off-by Przemyslaw Marczak <[email protected]>
---
  board/samsung/odroid/odroid.c | 60

+++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 30 deletions(-)

Quoted 6 lines

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

Thank you for applying the Odroid patch set.

I would like to note, that this one patch was intended for MR. Daniel just for his tests.

Quoted 6 lines
Quoted 6 lines

This patch breaks dw mmc performance:
e.g. eMMC uImage(fat) read performance:
- before this commit: 47.6 MiB/s
- after this commit: 13.0 MiB/s
So this requires some more changes in clocks and also in dw mmc driver.

Quoted 4 lines

MPLL is used to the eMMC's source clock.
If MPLL is changed to 880MHz, then eMMC's clock should not be set to correct value. It has to test before changed MPLL clock. otherwise, we need to use other source clock.

Yes, correct.

But for now this patch introduces considerable performance regression.

Moreover, as Przemek had written it down to Minkyu, this patch was supposed solely for Daniel's private usage and shouldn't be applied to u-boot main line.

Hence I'd like to ask for removing this patch from the pull request sent to Albert.

Quoted 21 lines

Best Regards,
Jaehoon Chung

Quoted 17 lines
Quoted 7 lines

And it can break some kernel clocks divider dependencies. It is not tested.

So please revert this patch.

Best Regards,

reverted..

Thanks,
Minkyu Kang.
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 5 lines
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group