cpufreq: use generic cpufreq drivers for exynos platforms

PATCH Superseded Thomas Abraham 4 participants 24 messages Jul 29, 2014

Subsystems (7)

Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +3 more subsystems

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Thomas Abraham

author

2014-07-29 05:28 UTC #0 lore raw

v8 cover cpufreq: use generic cpufreq drivers for exynos platforms

Changes since v7:
- Fixes suggested by Tomasz Figa.

This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver.

This patch series is dependent on two other patches
1. ARM: dts: add CPU nodes for Exynos4 SoCs
- https://lkml.org/lkml/2014/7/21/315
2. ARM: dts: smdk5250: Specify MAX77686 pmic interrupt
- http://www.spinics.net/lists/arm-kernel/msg351134.html

Since there are significant changes since v7, the Tested-by and Acked-by tags for all the patches in this series have been dropped.

Thomas Abraham (6):
clk: samsung: add infrastructure to register cpu clocks
clk: samsung: add cpu clock configuration data and instantiate cpu clock
ARM: dts: Exynos: add CPU OPP and regulator supply property
ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
clk: samsung: remove unused clock aliases and update clock flags

 arch/arm/boot/dts/exynos4210-origen.dts         |    6 +
 arch/arm/boot/dts/exynos4210-trats.dts          |    6 +
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    6 +
 arch/arm/boot/dts/exynos4210.dtsi               |   12 +
 arch/arm/boot/dts/exynos5250-arndale.dts        |    6 +
 arch/arm/boot/dts/exynos5250-cros-common.dtsi   |    6 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    6 +
 arch/arm/boot/dts/exynos5250.dtsi               |   23 ++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       |    6 +
 arch/arm/boot/dts/exynos5420.dtsi               |   38 +++
 arch/arm/mach-exynos/exynos.c                   |   24 +-
 drivers/clk/samsung/Makefile                    |    2 +-
 drivers/clk/samsung/clk-cpu.c                   |  335 +++++++++++++++++++++++
 drivers/clk/samsung/clk-cpu.h                   |   91 ++++++
 drivers/clk/samsung/clk-exynos4.c               |   59 ++--
 drivers/clk/samsung/clk-exynos5250.c            |   44 ++-
 drivers/clk/samsung/clk-exynos5420.c            |   72 ++++-
 drivers/cpufreq/Kconfig.arm                     |   22 --
 drivers/cpufreq/Makefile                        |    2 -
 drivers/cpufreq/exynos4210-cpufreq.c            |  184 -------------
 drivers/cpufreq/exynos5250-cpufreq.c            |  210 --------------
 include/dt-bindings/clock/exynos5250.h          |    1 +
 include/dt-bindings/clock/exynos5420.h          |    2 +
 23 files changed, 707 insertions(+), 456 deletions(-)
 create mode 100644 drivers/clk/samsung/clk-cpu.c
 create mode 100644 drivers/clk/samsung/clk-cpu.h
 delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
 delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c

Thomas Abraham

author

2014-07-29 05:28 UTC #1 lore raw

PATCH v8 1/6 clk: samsung: add infrastructure to register cpu clocks

The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms.

Cc Tomasz Figa <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/clk/samsung/Makefile  |    2 +-
 drivers/clk/samsung/clk-cpu.c |  335 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-cpu.h |   91 +++++++++++
 3 files changed, 427 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/samsung/clk-cpu.c
 create mode 100644 drivers/clk/samsung/clk-cpu.h

drivers/clk/samsung/Makefile +1 -1

index 6fb4bc6..8909c93 100644
@@ -2,7 +2,7 @@
 # Samsung Clock specific Makefile
 #
 
-obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o clk-cpu.o
 obj-$(CONFIG_SOC_EXYNOS3250)	+= clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o

drivers/clk/samsung/clk-cpu.c new file +335 -0

335 lines not on this page · raw message

drivers/clk/samsung/clk-cpu.h new file +91 -0

91 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-07-29 10:07 UTC #2 lore raw

PATCH v8 1/6 clk: samsung: add infrastructure to register cpu clocks

Hi Thomas,

Quoted 9 lines · Thomas Abraham

The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms.
Cc Tomasz Figa <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>

Quoted 8 lines

---
 drivers/clk/samsung/Makefile  |    2 +-
 drivers/clk/samsung/clk-cpu.c |  335 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-cpu.h |   91 +++++++++++
 3 files changed, 427 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/samsung/clk-cpu.c
 create mode 100644 drivers/clk/samsung/clk-cpu.h

Thanks for keeping up with review comments.

Reviewed-by Tomasz Figa <[email protected]>

Best regards,
Tomasz

Thomas Abraham

author

2014-07-29 05:28 UTC #3 lore raw

PATCH v8 2/6 clk: samsung: add cpu clock configuration data and instantiate cpu clock

In reply to Thomas Abraham

With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210, Exynos5250 and Exynos5420.

Cc Tomasz Figa <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/clk/samsung/clk-exynos4.c      |   15 +++++++++++
 drivers/clk/samsung/clk-exynos5250.c   |   25 ++++++++++++++++++
 drivers/clk/samsung/clk-exynos5420.c   |   45 ++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/exynos5250.h |    1 +
 include/dt-bindings/clock/exynos5420.h |    2 ++
 5 files changed, 88 insertions(+)

drivers/clk/samsung/clk-exynos4.c +15 -0

index ac163d7..5388806 100644
@@ -19,6 +19,7 @@
 #include <linux/syscore_ops.h>
 
 #include "clk.h"
+#include "clk-cpu.h"
 
 /* Exynos4 clock controller register offsets */
 #define SRC_LEFTBUS		0x4200

@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
 			VPLL_LOCK, VPLL_CON0, NULL),
 };
 
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+	{ 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+	{ 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+	{  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+	{  0 },
+};
+
 static void __init exynos4_core_down_clock(enum exynos4_soc soc)
 {
 	unsigned int tmp;

@@ -1459,6 +1470,10 @@ static void __init exynos4_clk_init(struct device_node *np,
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4210_fixed_factor_clks,
 			ARRAY_SIZE(exynos4210_fixed_factor_clks));
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+			e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
 	} else {
 		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
 			ARRAY_SIZE(exynos4x12_mux_clks));

drivers/clk/samsung/clk-exynos5250.c +25 -0

index 70ec3d2..e19e365 100644
@@ -19,6 +19,7 @@
 #include <linux/syscore_ops.h>
 
 #include "clk.h"
+#include "clk-cpu.h"
 
 #define APLL_LOCK		0x0
 #define APLL_CON0		0x100

@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
 		VPLL_LOCK, VPLL_CON0, NULL),
 };
 
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
+	{ 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+	{ 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+	{ 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+	{ 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  0 },
+};
+
 static const struct of_device_id ext_clk_match[] __initconst = {
 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
 	{ },

@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
 			ARRAY_SIZE(exynos5250_div_clks));
 	samsung_clk_register_gate(ctx, exynos5250_gate_clks,
 			ARRAY_SIZE(exynos5250_gate_clks));
+	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
+			CLK_CPU_HAS_DIV1);
 
 	/*
 	 * Enable arm clock down (in idle) and set arm divider

drivers/clk/samsung/clk-exynos5420.c +45 -0

63 lines not on this page · raw message

include/dt-bindings/clock/exynos5250.h +1 -0

index 4273891..855d809 100644
@@ -21,6 +21,7 @@
 #define CLK_FOUT_CPLL		6
 #define CLK_FOUT_EPLL		7
 #define CLK_FOUT_VPLL		8
+#define CLK_ARM_CLK		12
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_CAM_BAYER	128

include/dt-bindings/clock/exynos5420.h +2 -0

index 8dc0913..ec0af64 100644
@@ -25,6 +25,8 @@
 #define CLK_FOUT_MPLL		10
 #define CLK_FOUT_BPLL		11
 #define CLK_FOUT_KPLL		12
+#define CLK_ARM_CLK		13
+#define CLK_KFC_CLK		14
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_UART0		128

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-07-29 10:13 UTC #4 lore raw

PATCH v8 2/6 clk: samsung: add cpu clock configuration data and instantiate cpu clock

Hi Thomas,

Just few minor comments for things I probably missed before.

On 29.07.2014 07:28, Thomas Abraham wrote:

[snip]

drivers/clk/samsung/clk-exynos4.c static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { · line 1365

Quoted 10 lines

drivers/clk/samsung/clk-exynos4.c +6 -0

@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
 			VPLL_LOCK, VPLL_CON0, NULL),
 };
 
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+	{ 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+	{ 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+	{  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },

I have noticed that the old driver does not have this operating point. While it is probably OK to add this one and even few more for all possible APLL settings, I am interested in how you obtained the values for DIV0 and DIV1 registers for this configuration.

Quoted 3 lines

drivers/clk/samsung/clk-exynos4.c +3 -0

+	{  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+	{  0 },
+};

[snip]

include/dt-bindings/clock/exynos5250.h line 24

Quoted 9 lines

include/dt-bindings/clock/exynos5250.h +1 -0

index 4273891..855d809 100644
@@ -21,6 +21,7 @@
 #define CLK_FOUT_CPLL		6
 #define CLK_FOUT_EPLL		7
 #define CLK_FOUT_VPLL		8
+#define CLK_ARM_CLK		12

Why 12 not 9?

Best regards,
Tomasz

Thomas Abraham

2014-07-29 11:46 UTC #5 lore raw

PATCH v8 2/6 clk: samsung: add cpu clock configuration data and instantiate cpu clock

Hi Tomasz,

Quoted 12 lines · Tomasz Figa

Hi Thomas,
Just few minor comments for things I probably missed before.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]
Quoted 4 lines
drivers/clk/samsung/clk-exynos4.c +0 -0
@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
                      VPLL_LOCK, VPLL_CON0, NULL),
 };
 

Quoted 11 lines

drivers/clk/samsung/clk-exynos4.c static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { · line 1365
Quoted 6 lines
drivers/clk/samsung/clk-exynos4.c +6 -0
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+     { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+     { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+     {  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+     {  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+     {  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
I have noticed that the old driver does not have this operating point. While it is probably OK to add this one and even few more for all possible APLL settings, I am interested in how you obtained the values for DIV0 and DIV1 registers for this configuration.

I found these values from an old internal repo. So far no trouble seen with these values in all the testing.

Quoted 7 lines

Quoted 4 lines
drivers/clk/samsung/clk-exynos4.c +3 -0
+     {  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+     {  0 },
+};
[snip]

Quoted 11 lines

include/dt-bindings/clock/exynos5250.h line 24

Quoted 9 lines

include/dt-bindings/clock/exynos5250.h +1 -0

index 4273891..855d809 100644
@@ -21,6 +21,7 @@
 #define CLK_FOUT_CPLL                6
 #define CLK_FOUT_EPLL                7
 #define CLK_FOUT_VPLL                8
+#define CLK_ARM_CLK          12

Why 12 not 9?

Exynos4 uses 12 and so just wanted to keep it same for Exynos5250 as well.

Thanks,
Thomas.

Quoted 7 lines

Best regards,
Tomasz
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Tomasz Figa

2014-07-29 12:04 UTC #6 lore raw

PATCH v8 2/6 clk: samsung: add cpu clock configuration data and instantiate cpu clock

Quoted 27 lines · Thomas Abraham

Hi Tomasz,
Quoted 12 lines · Tomasz Figa
Hi Thomas,
Just few minor comments for things I probably missed before.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]
Quoted 4 lines
drivers/clk/samsung/clk-exynos4.c +0 -0
@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
                      VPLL_LOCK, VPLL_CON0, NULL),
 };
 
Quoted 11 lines
drivers/clk/samsung/clk-exynos4.c static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { · line 1365
Quoted 6 lines
drivers/clk/samsung/clk-exynos4.c +6 -0
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+     { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+     { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+     {  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+     {  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+     {  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
I have noticed that the old driver does not have this operating point. While it is probably OK to add this one and even few more for all possible APLL settings, I am interested in how you obtained the values for DIV0 and DIV1 registers for this configuration.

Quoted 2 lines

I found these values from an old internal repo. So far no trouble seen with these values in all the testing.

OK.

Quoted 20 lines

Quoted 8 lines

Quoted 5 lines
drivers/clk/samsung/clk-exynos4.c +3 -0
+     {  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+     {  0 },
+};
[snip]

Quoted 11 lines

include/dt-bindings/clock/exynos5250.h line 24

Quoted 9 lines

include/dt-bindings/clock/exynos5250.h +1 -0

index 4273891..855d809 100644
@@ -21,6 +21,7 @@
 #define CLK_FOUT_CPLL                6
 #define CLK_FOUT_EPLL                7
 #define CLK_FOUT_VPLL                8
+#define CLK_ARM_CLK          12

Why 12 not 9?

Quoted 1 line

Exynos4 uses 12 and so just wanted to keep it same for Exynos5250 as well.

There is no need to align those numbers between different bindings, because preprocessor macros are used anyway and leaving holes between clocks only makes the namespace harder to maintain.

Best regards,
Tomasz

Thomas Abraham

2014-07-29 12:05 UTC #7 lore raw

PATCH v8 2/6 clk: samsung: add cpu clock configuration data and instantiate cpu clock

Quoted 53 lines · Tomasz Figa

Quoted 27 lines · Thomas Abraham
Hi Tomasz,
Quoted 12 lines · Tomasz Figa
Hi Thomas,
Just few minor comments for things I probably missed before.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]
Quoted 4 lines
drivers/clk/samsung/clk-exynos4.c +0 -0
@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
                      VPLL_LOCK, VPLL_CON0, NULL),
 };
 
Quoted 11 lines
drivers/clk/samsung/clk-exynos4.c static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { · line 1365
Quoted 6 lines
drivers/clk/samsung/clk-exynos4.c +6 -0
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+     { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+     { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+     {  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+     {  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+     {  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
I have noticed that the old driver does not have this operating point. While it is probably OK to add this one and even few more for all possible APLL settings, I am interested in how you obtained the values for DIV0 and DIV1 registers for this configuration.
Quoted 2 lines
I found these values from an old internal repo. So far no trouble seen with these values in all the testing.
OK.
Quoted 20 lines
Quoted 19 lines
Quoted 5 lines
drivers/clk/samsung/clk-exynos4.c +3 -0
+     {  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+     {  0 },
+};
[snip]
include/dt-bindings/clock/exynos5250.h line 24
Quoted 9 lines
include/dt-bindings/clock/exynos5250.h +1 -0
index 4273891..855d809 100644
@@ -21,6 +21,7 @@
 #define CLK_FOUT_CPLL                6
 #define CLK_FOUT_EPLL                7
 #define CLK_FOUT_VPLL                8
+#define CLK_ARM_CLK          12
Why 12 not 9?

Quoted 5 lines

Quoted 1 line
Exynos4 uses 12 and so just wanted to keep it same for Exynos5250 as well.
There is no need to align those numbers between different bindings, because preprocessor macros are used anyway and leaving holes between clocks only makes the namespace harder to maintain.

Ok. I will fix this.

Thanks,
Thomas.

Quoted 3 lines

Best regards,
Tomasz

Thomas Abraham

author

2014-07-29 05:28 UTC #8 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

In reply to Thomas Abraham

For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers.

Cc Kukjin Kim <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/boot/dts/exynos4210-origen.dts         |    6 ++++
 arch/arm/boot/dts/exynos4210-trats.dts          |    6 ++++
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    6 ++++
 arch/arm/boot/dts/exynos4210.dtsi               |   12 +++++++
 arch/arm/boot/dts/exynos5250-arndale.dts        |    6 ++++
 arch/arm/boot/dts/exynos5250-cros-common.dtsi   |    6 ++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    6 ++++
 arch/arm/boot/dts/exynos5250.dtsi               |   23 ++++++++++++++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       |    6 ++++
 arch/arm/boot/dts/exynos5420.dtsi               |   38 +++++++++++++++++++++++
 10 files changed, 115 insertions(+)

arch/arm/boot/dts/exynos4210-origen.dts +6 -0

index f767c42..49a97fc 100644
@@ -33,6 +33,12 @@
 		bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
 	};
 
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&buck1_reg>;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;

arch/arm/boot/dts/exynos4210-trats.dts +6 -0

index f516da9..fe32b6a 100644
@@ -30,6 +30,12 @@
 		bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
 	};
 
+	cpus {
+		cpu: cpu at 0 {
+			cpu0-supply = <&varm_breg>;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";

arch/arm/boot/dts/exynos4210-universal_c210.dts +6 -0

index d50eb3a..8ab12d6 100644
@@ -28,6 +28,12 @@
 		bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
 	};
 
+	cpus {
+		cpu: cpu at 0 {
+			cpu0-supply = <&vdd_arm_reg>;
+		};
+	};
+
 	sysram at 02020000 {
 		smp-sysram at 0 {
 			status = "disabled";

arch/arm/boot/dts/exynos4210.dtsi +12 -0

index bcc9e63..cd68030 100644
@@ -39,6 +39,18 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0x900>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu";
+			clock-latency = <200000>;
+
+			operating-points = <
+				1200000 1250000
+				1000000 1150000
+				800000	1075000
+				500000	975000
+				400000	975000
+				200000	950000
+			>;
 		};
 
 		cpu at 901 {

arch/arm/boot/dts/exynos5250-arndale.dts +6 -0

index d0de1f5..d9b803b 100644
@@ -26,6 +26,12 @@
 		bootargs = "console=ttySAC2,115200";
 	};
 
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&buck2_reg>;
+		};
+	};
+
 	rtc at 101E0000 {
 		status = "okay";
 	};

arch/arm/boot/dts/exynos5250-cros-common.dtsi +6 -0

index 89ac90f..34bb31c 100644
@@ -19,6 +19,12 @@
 	chosen {
 	};
 
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&buck2_reg>;
+		};
+	};
+
 	pinctrl at 11400000 {
 		/*
 		 * Disabled pullups since external part has its own pullups and

arch/arm/boot/dts/exynos5250-smdk5250.dts +6 -0

index b4b35ad..cf38808 100644
@@ -27,6 +27,12 @@
 		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
 	};
 
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&buck2_reg>;
+		};
+	};
+
 	rtc at 101E0000 {
 		status = "okay";
 	};

arch/arm/boot/dts/exynos5250.dtsi +23 -0

index 492e1ef..876247a 100644
@@ -63,6 +63,29 @@
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 			clock-frequency = <1700000000>;
+
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu";
+			clock-latency = <200000>;
+
+			operating-points = <
+				1700000 1300000
+				1600000 1250000
+				1500000 1225000
+				1400000 1200000
+				1300000 1150000
+				1200000 1125000
+				1100000 1100000
+				1000000 1075000
+				 900000 1050000
+				 800000 1025000
+				 700000 1012500
+				 600000 1000000
+				 500000  975000
+				 400000  950000
+				 300000  937500
+				 200000  925000
+			>;
 		};
 		cpu at 1 {
 			device_type = "cpu";

arch/arm/boot/dts/exynos5420-smdk5420.dts +6 -0

index 6052aa9..084e587 100644
@@ -24,6 +24,12 @@
 		bootargs = "console=ttySAC2,115200 init=/linuxrc";
 	};
 
+	cpus {
+		cpu at 4 {
+			cpu0-supply = <&buck6_reg>;
+		};
+	};
+
 	fixed-rate-clocks {
 		oscclk {
 			compatible = "samsung,exynos5420-oscclk";

arch/arm/boot/dts/exynos5420.dtsi +38 -0

index cb2b70e..1116d55 100644
@@ -59,8 +59,26 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu-cluster.0";
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
+
+			operating-points = <
+				1800000 1250000
+				1700000 1212500
+				1600000 1175000
+				1500000 1137500
+				1400000 1112500
+				1300000 1062500
+				1200000 1037500
+				1100000 1012500
+				1000000 987500
+				 900000 962500
+				 800000 937500
+				 700000 912500
+			>;
 		};
 
 		cpu1: cpu at 1 {

@@ -69,6 +87,7 @@
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
 		};
 
 		cpu2: cpu at 2 {

@@ -77,6 +96,7 @@
 			reg = <0x2>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
 		};
 
 		cpu3: cpu at 3 {

@@ -85,14 +105,29 @@
 			reg = <0x3>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
 		};
 
 		cpu4: cpu at 100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
+			clocks = <&clock CLK_KFC_CLK>;
+			clock-names = "cpu-cluster.1";
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
+
+			operating-points = <
+				1300000 1275000
+				1200000 1212500
+				1100000 1162500
+				1000000 1112500
+				 900000 1062500
+				 800000 1025000
+				 700000 975000
+				 600000 937500
+			>;
 		};
 
 		cpu5: cpu at 101 {

@@ -101,6 +136,7 @@
 			reg = <0x101>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
 		};
 
 		cpu6: cpu at 102 {

@@ -109,6 +145,7 @@
 			reg = <0x102>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
 		};
 
 		cpu7: cpu at 103 {

@@ -117,6 +154,7 @@
 			reg = <0x103>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
 		};
 	};

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-07-29 10:31 UTC #9 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

Hi Thomas,

Other than the same question about 400 MHz OPP for Exynos4210, I have also few more inline.

Quoted 6 lines · Thomas Abraham

For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers.
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>

Quoted 10 lines

---
 arch/arm/boot/dts/exynos4210-origen.dts         |    6 ++++
 arch/arm/boot/dts/exynos4210-trats.dts          |    6 ++++
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    6 ++++
 arch/arm/boot/dts/exynos4210.dtsi               |   12 +++++++
 arch/arm/boot/dts/exynos5250-arndale.dts        |    6 ++++
 arch/arm/boot/dts/exynos5250-cros-common.dtsi   |    6 ++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    6 ++++
 arch/arm/boot/dts/exynos5250.dtsi               |   23 ++++++++++++++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       |    6 ++++

There are more Exynos5420-based boards supported in mainline. If you do not have necessary data and/or hardware to fully enable the new driver on them, you should add responsible people on Cc list, so at least they know they have one more item on their TODO list. Added them for you.

Quoted 2 lines

 arch/arm/boot/dts/exynos5420.dtsi               |   38 +++++++++++++++++++++++
 10 files changed, 115 insertions(+)

[snip]

arch/arm/boot/dts/exynos5250.dtsi line 69

Quoted 12 lines

arch/arm/boot/dts/exynos5250.dtsi +4 -0

index 492e1ef..876247a 100644
@@ -63,6 +63,29 @@
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 			clock-frequency = <1700000000>;
+
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu";
+			clock-latency = <200000>;

Where does this latency value comes from? How did you calculate it?

For example, on Exynos4210, for all operating points added by your patches, the highest PLL locking latency will be 60uS, because the highest PDIV value would be 6 and PLL lock time is PDIV*240 ticks of 24 MHz reference clock.

Quoted 4 lines

arch/arm/boot/dts/exynos5250.dtsi +4 -0
+
+			operating-points = <
+				1700000 1300000
+				1600000 1250000

[snip]

arch/arm/boot/dts/exynos5420-smdk5420.dts line 27

Quoted 9 lines

arch/arm/boot/dts/exynos5420-smdk5420.dts +1 -0

index 6052aa9..084e587 100644
@@ -24,6 +24,12 @@
 		bootargs = "console=ttySAC2,115200 init=/linuxrc";
 	};
 
+	cpus {

Is there no regulator for cpu0?

Quoted 12 lines

arch/arm/boot/dts/exynos5420-smdk5420.dts +5 -0

+		cpu at 4 {
+			cpu0-supply = <&buck6_reg>;
+		};
+	};
+
 	fixed-rate-clocks {
 		oscclk {
 			compatible = "samsung,exynos5420-oscclk";

arch/arm/boot/dts/exynos5420.dtsi +0 -0

index cb2b70e..1116d55 100644

[snip]

arch/arm/boot/dts/exynos5420.dtsi line 90

Quoted 7 lines

arch/arm/boot/dts/exynos5420.dtsi +1 -0

 		cpu1: cpu at 1 {

@@ -69,6 +87,7 @@
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;

Do you need to specify this property for every CPU or rather just for those which have operating points specified?

Best regards,
Tomasz

Thomas Abraham

2014-07-29 12:00 UTC #10 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

Hi Tomasz,

Quoted 23 lines · Tomasz Figa

Hi Thomas,
Other than the same question about 400 MHz OPP for Exynos4210, I have also few more inline.
Quoted 6 lines · Thomas Abraham
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers.
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Quoted 10 lines
---
 arch/arm/boot/dts/exynos4210-origen.dts         |    6 ++++
 arch/arm/boot/dts/exynos4210-trats.dts          |    6 ++++
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    6 ++++
 arch/arm/boot/dts/exynos4210.dtsi               |   12 +++++++
 arch/arm/boot/dts/exynos5250-arndale.dts        |    6 ++++
 arch/arm/boot/dts/exynos5250-cros-common.dtsi   |    6 ++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    6 ++++
 arch/arm/boot/dts/exynos5250.dtsi               |   23 ++++++++++++++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       |    6 ++++

Quoted 4 lines

There are more Exynos5420-based boards supported in mainline. If you do not have necessary data and/or hardware to fully enable the new driver on them, you should add responsible people on Cc list, so at least they know they have one more item on their TODO list. Added them for you.

Thanks!. Will do that next time.

Quoted 21 lines

Quoted 3 lines

 arch/arm/boot/dts/exynos5420.dtsi               |   38 +++++++++++++++++++++++
 10 files changed, 115 insertions(+)

[snip]

arch/arm/boot/dts/exynos5250.dtsi line 69

Quoted 12 lines

arch/arm/boot/dts/exynos5250.dtsi +4 -0

index 492e1ef..876247a 100644
@@ -63,6 +63,29 @@
                      compatible = "arm,cortex-a15";
                      reg = <0>;
                      clock-frequency = <1700000000>;
+
+                     clocks = <&clock CLK_ARM_CLK>;
+                     clock-names = "cpu";
+                     clock-latency = <200000>;

Where does this latency value comes from? How did you calculate it?

Quoted 4 lines

For example, on Exynos4210, for all operating points added by your patches, the highest PLL locking latency will be 60uS, because the highest PDIV value would be 6 and PLL lock time is PDIV*240 ticks of 24 MHz reference clock.

Since the CPU clock is a composite clock with dividers and muxes, the latency includes the settling time for these clock blocks as well. I have not made any measurements of the clock transition latency.

Quoted 16 lines

Quoted 5 lines

arch/arm/boot/dts/exynos5250.dtsi +4 -0

+
+                     operating-points = <
+                             1700000 1300000
+                             1600000 1250000

[snip]

Quoted 8 lines

arch/arm/boot/dts/exynos5420-smdk5420.dts +0 -0

index 6052aa9..084e587 100644
@@ -24,6 +24,12 @@
              bootargs = "console=ttySAC2,115200 init=/linuxrc";
      };

Quoted 3 lines

arch/arm/boot/dts/exynos5420-smdk5420.dts line 27
Quoted 1 line
arch/arm/boot/dts/exynos5420-smdk5420.dts +1 -0
+     cpus {
Is there no regulator for cpu0?

This was a mistake. I did not intend to add regulator for cpu4 as well but somehow I missed it. I will remove it in the next version.

Quoted 17 lines

Quoted 13 lines

arch/arm/boot/dts/exynos5420-smdk5420.dts +5 -0

+             cpu at 4 {
+                     cpu0-supply = <&buck6_reg>;
+             };
+     };
+
      fixed-rate-clocks {
              oscclk {
                      compatible = "samsung,exynos5420-oscclk";

arch/arm/boot/dts/exynos5420.dtsi +0 -0

index cb2b70e..1116d55 100644

[snip]

Quoted 1 line

Quoted 9 lines

arch/arm/boot/dts/exynos5420.dtsi line 90
Quoted 6 lines
              cpu1: cpu at 1 {
arch/arm/boot/dts/exynos5420.dtsi +1 -0
@@ -69,6 +87,7 @@
                      reg = <0x1>;
                      clock-frequency = <1800000000>;
                      cci-control-port = <&cci_control1>;
+                     clock-latency = <200000>;
Do you need to specify this property for every CPU or rather just for those which have operating points specified?

The big.little cpufreq driver expects each CPU to have the clock latency specified.

Thanks,
Thomas.

Quoted 7 lines

Best regards,
Tomasz
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Tomasz Figa

2014-07-29 12:10 UTC #11 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

On 29.07.2014 14:00, Thomas Abraham wrote:

[snip]

Quoted 15 lines

arch/arm/boot/dts/exynos5250.dtsi line 69

Quoted 12 lines

arch/arm/boot/dts/exynos5250.dtsi +4 -0

index 492e1ef..876247a 100644
@@ -63,6 +63,29 @@
                      compatible = "arm,cortex-a15";
                      reg = <0>;
                      clock-frequency = <1700000000>;
+
+                     clocks = <&clock CLK_ARM_CLK>;
+                     clock-names = "cpu";
+                     clock-latency = <200000>;

Where does this latency value comes from? How did you calculate it?

Quoted 9 lines

Quoted 4 lines
For example, on Exynos4210, for all operating points added by your patches, the highest PLL locking latency will be 60uS, because the highest PDIV value would be 6 and PLL lock time is PDIV*240 ticks of 24 MHz reference clock.
Since the CPU clock is a composite clock with dividers and muxes, the latency includes the settling time for these clock blocks as well. I have not made any measurements of the clock transition latency.

It might be more reasonable to find out correct latency values instead of specifying a rather random number.

Quoted 34 lines

Quoted 16 lines
Quoted 5 lines
arch/arm/boot/dts/exynos5250.dtsi +4 -0
+
+                     operating-points = <
+                             1700000 1300000
+                             1600000 1250000
[snip]
Quoted 8 lines
arch/arm/boot/dts/exynos5420-smdk5420.dts +0 -0
index 6052aa9..084e587 100644
@@ -24,6 +24,12 @@
              bootargs = "console=ttySAC2,115200 init=/linuxrc";
      };
 
Quoted 3 lines
arch/arm/boot/dts/exynos5420-smdk5420.dts line 27
Quoted 1 line
arch/arm/boot/dts/exynos5420-smdk5420.dts +1 -0
+     cpus {
Is there no regulator for cpu0?
This was a mistake. I did not intend to add regulator for cpu4 as well but somehow I missed it. I will remove it in the next version.
Quoted 10 lines
arch/arm/boot/dts/exynos5420-smdk5420.dts line 90
Quoted 7 lines
arch/arm/boot/dts/exynos5420-smdk5420.dts +1 -0
              cpu1: cpu at 1 {
@@ -69,6 +87,7 @@
                      reg = <0x1>;
                      clock-frequency = <1800000000>;
                      cci-control-port = <&cci_control1>;
+                     clock-latency = <200000>;
Do you need to specify this property for every CPU or rather just for those which have operating points specified?

Quoted 2 lines

The big.little cpufreq driver expects each CPU to have the clock latency specified.

OK, apparently this is the case, even though it seems a bit unreasonable, as they all share the same clock.

Best regards,
Tomasz

Andreas Färber

2014-07-29 12:08 UTC #12 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

In reply to Thomas Abraham

Hi Thomas,

Am 29.07.2014 07:28, schrieb Thomas Abraham:

Quoted 7 lines

arch/arm/boot/dts/exynos5250-cros-common.dtsi +0 -0
index 89ac90f..34bb31c 100644
@@ -19,6 +19,12 @@
 	chosen {
 	};

arch/arm/boot/dts/exynos5250-cros-common.dtsi line 30

Quoted 10 lines

arch/arm/boot/dts/exynos5250-cros-common.dtsi +6 -0

 
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&buck2_reg>;
+		};
+	};
+
 	pinctrl at 11400000 {
 		/*
 		 * Disabled pullups since external part has its own pullups and

I've been instructed to dismantle this .dtsi file, so please place this into exynos5250-snow.dts. It's probably wrong here anyway, since Spring doesn't use the max77686 but an s5m6787 PMIC.

How do I find out which -supply to specify here for Spring?

Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi to override it via &cpu0 { ... };?

Regards,
Andreas

Signature · 2 lines

SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg

Thomas Abraham

2014-07-29 12:35 UTC #13 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

Hi Andreas,

Quoted 11 lines · Andreas F?rber

Hi Thomas,
Am 29.07.2014 07:28, schrieb Thomas Abraham:
Quoted 8 lines
arch/arm/boot/dts/exynos5250-cros-common.dtsi +0 -0
index 89ac90f..34bb31c 100644
@@ -19,6 +19,12 @@
      chosen {
      };
 

Quoted 13 lines

arch/arm/boot/dts/exynos5250-cros-common.dtsi line 30
Quoted 9 lines
arch/arm/boot/dts/exynos5250-cros-common.dtsi +6 -0
+     cpus {
+             cpu at 0 {
+                     cpu0-supply = <&buck2_reg>;
+             };
+     };
+
      pinctrl at 11400000 {
              /*
               * Disabled pullups since external part has its own pullups and
I've been instructed to dismantle this .dtsi file, so please place this into exynos5250-snow.dts. It's probably wrong here anyway, since Spring doesn't use the max77686 but an s5m6787 PMIC.

Ok, I will move this to exynos5250-snow.dts.

Quoted 2 lines

How do I find out which -supply to specify here for Spring?

This information can be found in the Spring board schematic.

Quoted 3 lines

Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi to override it via &cpu0 { ... };?

Sorry, I did not understand the question.

Thanks,
Thomas.

Quoted 12 lines

Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg
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Andreas Färber

2014-07-29 12:42 UTC #14 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

Hi Thomas,

Am 29.07.2014 14:35, schrieb Thomas Abraham:

Quoted 24 lines · Andreas F?rber

Quoted 9 lines
Am 29.07.2014 07:28, schrieb Thomas Abraham:
Quoted 8 lines
arch/arm/boot/dts/exynos5250-cros-common.dtsi +0 -0
index 89ac90f..34bb31c 100644
@@ -19,6 +19,12 @@
      chosen {
      };
 
Quoted 13 lines
arch/arm/boot/dts/exynos5250-cros-common.dtsi line 30
Quoted 9 lines
arch/arm/boot/dts/exynos5250-cros-common.dtsi +6 -0
+     cpus {
+             cpu at 0 {
+                     cpu0-supply = <&buck2_reg>;
+             };
+     };
+
      pinctrl at 11400000 {
              /*
               * Disabled pullups since external part has its own pullups and
I've been instructed to dismantle this .dtsi file, so please place this into exynos5250-snow.dts. It's probably wrong here anyway, since Spring doesn't use the max77686 but an s5m6787 PMIC.

Quoted 6 lines

Ok, I will move this to exynos5250-snow.dts.
Quoted 2 lines
How do I find out which -supply to specify here for Spring?
This information can be found in the Spring board schematic.

Are those available publicly somewhere? I guess not...

Quoted 4 lines

Quoted 2 lines
Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi to override it via &cpu0 { ... };?
Sorry, I did not understand the question.

Instead of adding

cpus { cpu at 0 { ... }; };

to the board's / node, I am suggesting you do in the SoC's .dtsi:

- cpu at 0 {
+ cpu0: cpu at 0 {

and then in the board's file after / { ... }; add the following:

&cpu0 {
	cpu0-supply = <&buck2_reg>;
};

This is the new preferred way to override or extend inherited nodes, I am told. (&cpu0 should be inserted in alphabetical order then.)

Cheers,
Andreas

Signature · 2 lines

SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg

Thomas Abraham

2014-07-29 12:51 UTC #15 lore raw

PATCH v8 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

Hi Andreas,

Quoted 27 lines · Andreas F?rber

Hi Thomas,
Am 29.07.2014 14:35, schrieb Thomas Abraham:
Quoted 24 lines · Andreas F?rber
Quoted 22 lines
Am 29.07.2014 07:28, schrieb Thomas Abraham:
Quoted 7 lines
arch/arm/boot/dts/exynos5250-cros-common.dtsi +0 -0
index 89ac90f..34bb31c 100644
@@ -19,6 +19,12 @@
      chosen {
      };
arch/arm/boot/dts/exynos5250-cros-common.dtsi line 30
Quoted 10 lines
arch/arm/boot/dts/exynos5250-cros-common.dtsi +6 -0
 
+     cpus {
+             cpu at 0 {
+                     cpu0-supply = <&buck2_reg>;
+             };
+     };
+
      pinctrl at 11400000 {
              /*
               * Disabled pullups since external part has its own pullups and
I've been instructed to dismantle this .dtsi file, so please place this into exynos5250-snow.dts. It's probably wrong here anyway, since Spring doesn't use the max77686 but an s5m6787 PMIC.

Quoted 8 lines

Quoted 6 lines
Ok, I will move this to exynos5250-snow.dts.
Quoted 2 lines
How do I find out which -supply to specify here for Spring?
This information can be found in the Spring board schematic.
Are those available publicly somewhere? I guess not...

I am not sure if it is available publicly. Doug (Cc'ed on this email) might have it.

Quoted 15 lines

Quoted 5 lines
Quoted 3 lines
Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi to override it via &cpu0 { ... };?
Sorry, I did not understand the question.
Instead of adding
cpus { cpu at 0 { ... }; };
to the board's / node, I am suggesting you do in the SoC's .dtsi:
- cpu at 0 {
+ cpu0: cpu at 0 {

Quoted 8 lines

and then in the board's file after / { ... }; add the following:
&cpu0 {
        cpu0-supply = <&buck2_reg>;
};
This is the new preferred way to override or extend inherited nodes, I am told. (&cpu0 should be inserted in alphabetical order then.)

Okay, thanks for the clarification. I will update as per the preferred way.

Thanks,
Thomas.

Quoted 7 lines

Cheers,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg

Thomas Abraham

author

2014-07-29 05:28 UTC #16 lore raw

PATCH v8 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

In reply to Thomas Abraham

The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.

Cc Kukjin Kim <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/exynos.c |   24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

arch/arm/mach-exynos/exynos.c +23 -1

index df41bd1..4d7be5e 100644
@@ -279,6 +279,28 @@ static void __init exynos_init_irq(void)
 	exynos_map_pmu();
 }
 
+static const struct of_device_id exynos_cpufreq_matches[] = {
+	{ .compatible = "samsung,exynos5420", .data = "arm-bL-cpufreq-dt" },
+	{ .compatible = "samsung,exynos5250", .data = "cpufreq-cpu0" },
+	{ .compatible = "samsung,exynos4210", .data = "cpufreq-cpu0" },
+	{ .compatible = "samsung,exynos5440", .data = "exynos5440-cpufreq" },
+	{ /* sentinel */ }
+};
+
+static void __init exynos_cpufreq_init(void)
+{
+	struct device_node *root = of_find_node_by_path("/");
+	const struct of_device_id *match;
+
+	match = of_match_node(exynos_cpufreq_matches, root);
+	if (!match) {
+		platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
+		return;
+	}
+
+	platform_device_register_simple(match->data, -1, NULL, 0);
+}
+
 static void __init exynos_dt_machine_init(void)
 {
 	struct device_node *i2c_np;

@@ -318,7 +340,7 @@ static void __init exynos_dt_machine_init(void)
 			of_machine_is_compatible("samsung,exynos5250"))
 		platform_device_register(&exynos_cpuidle);
 
-	platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
+	exynos_cpufreq_init();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-07-29 10:32 UTC #17 lore raw

PATCH v8 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

Quoted 11 lines · Thomas Abraham

The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.
Suggested-by Tomasz Figa <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
---
 arch/arm/mach-exynos/exynos.c |   24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

Reviewed-by Tomasz Figa <[email protected]>

Best regards,
Tomasz

Thomas Abraham

author

2014-07-29 05:28 UTC #18 lore raw

PATCH v8 5/6 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support

In reply to Thomas Abraham

Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed.

Cc Viresh Kumar <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/cpufreq/Kconfig.arm          |   22 ----
 drivers/cpufreq/Makefile             |    2 -
 drivers/cpufreq/exynos4210-cpufreq.c |  184 -----------------------------
 drivers/cpufreq/exynos5250-cpufreq.c |  210 ----------------------------------
 4 files changed, 418 deletions(-)
 delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
 delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c

drivers/cpufreq/Kconfig.arm +0 ~~-22~~

index 7364a53..f81fc3e 100644
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
 config ARM_EXYNOS_CPUFREQ
 	bool
 
-config ARM_EXYNOS4210_CPUFREQ
-	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS4210
-	  SoC (S5PV310 or S5PC210).
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS4X12_CPUFREQ
 	bool "SAMSUNG EXYNOS4x12"
 	depends on SOC_EXYNOS4212 || SOC_EXYNOS4412

@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
 
 	  If in doubt, say N.
 
-config ARM_EXYNOS5250_CPUFREQ
-	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS5250
-	  SoC.
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS5440_CPUFREQ
 	bool "SAMSUNG EXYNOS5440"
 	depends on SOC_EXYNOS5440

drivers/cpufreq/Makefile +0 -2

index db6d9a2..fac36ef 100644
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ)		+= arm_big_little_dt.o
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci-cpufreq.o
 obj-$(CONFIG_UX500_SOC_DB8500)		+= dbx500-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)	+= exynos5440-cpufreq.o
 obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ)	+= highbank-cpufreq.o
 obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o

drivers/cpufreq/exynos4210-cpufreq.c deleted +0 ~~-184~~

184 lines not on this page · raw message

drivers/cpufreq/exynos5250-cpufreq.c deleted +0 ~~-210~~

210 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-07-29 10:34 UTC #19 lore raw

PATCH v8 5/6 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support

[CC Bart]

Quoted 476 lines · Thomas Abraham

Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed.

Cc Viresh Kumar <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/cpufreq/Kconfig.arm          |   22 ----
 drivers/cpufreq/Makefile             |    2 -
 drivers/cpufreq/exynos4210-cpufreq.c |  184 -----------------------------
 drivers/cpufreq/exynos5250-cpufreq.c |  210 ----------------------------------
 4 files changed, 418 deletions(-)
 delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
 delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c

drivers/cpufreq/Kconfig.arm +0 ~~-22~~

index 7364a53..f81fc3e 100644
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
 config ARM_EXYNOS_CPUFREQ
 	bool
 
-config ARM_EXYNOS4210_CPUFREQ
-	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS4210
-	  SoC (S5PV310 or S5PC210).
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS4X12_CPUFREQ
 	bool "SAMSUNG EXYNOS4x12"
 	depends on SOC_EXYNOS4212 || SOC_EXYNOS4412

@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
 
 	  If in doubt, say N.
 
-config ARM_EXYNOS5250_CPUFREQ
-	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS5250
-	  SoC.
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS5440_CPUFREQ
 	bool "SAMSUNG EXYNOS5440"
 	depends on SOC_EXYNOS5440

drivers/cpufreq/Makefile +0 -2

index db6d9a2..fac36ef 100644
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ)		+= arm_big_little_dt.o
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci-cpufreq.o
 obj-$(CONFIG_UX500_SOC_DB8500)		+= dbx500-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)	+= exynos5440-cpufreq.o
 obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ)	+= highbank-cpufreq.o
 obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o

drivers/cpufreq/exynos4210-cpufreq.c deleted +0 ~~-184~~

deleted file mode 100644
index 61a5431..0000000
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * EXYNOS4210 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/cpufreq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include "exynos-cpufreq.h"
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos4210_volt_table[] = {
-	1250000, 1150000, 1050000, 975000, 950000,
-};
-
-static struct cpufreq_frequency_table exynos4210_freq_table[] = {
-	{0, L0, 1200 * 1000},
-	{0, L1, 1000 * 1000},
-	{0, L2,  800 * 1000},
-	{0, L3,  500 * 1000},
-	{0, L4,  200 * 1000},
-	{0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_4210[] = {
-	/*
-	 * values:
-	 * freq
-	 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
-	 * clock divider for COPY, HPM, RESERVED
-	 * PLL M, P, S
-	 */
-	APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
-	APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
-	APLL_FREQ(800,  0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
-	APLL_FREQ(500,  0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
-	APLL_FREQ(200,  0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
-};
-
-static void exynos4210_set_clkdiv(unsigned int div_index)
-{
-	unsigned int tmp;
-
-	/* Change Divider - CPU0 */
-
-	tmp = apll_freq_4210[div_index].clk_div_cpu0;
-
-	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
-
-	do {
-		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
-	} while (tmp & 0x1111111);
-
-	/* Change Divider - CPU1 */
-
-	tmp = apll_freq_4210[div_index].clk_div_cpu1;
-
-	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
-
-	do {
-		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
-	} while (tmp & 0x11);
-}
-
-static void exynos4210_set_apll(unsigned int index)
-{
-	unsigned int tmp, freq = apll_freq_4210[index].freq;
-
-	/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
-	clk_set_parent(moutcore, mout_mpll);
-
-	do {
-		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
-			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
-		tmp &= 0x7;
-	} while (tmp != 0x2);
-
-	clk_set_rate(mout_apll, freq * 1000);
-
-	/* MUX_CORE_SEL = APLL */
-	clk_set_parent(moutcore, mout_apll);
-
-	do {
-		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
-		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
-	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
-}
-
-static void exynos4210_set_frequency(unsigned int old_index,
-				     unsigned int new_index)
-{
-	if (old_index > new_index) {
-		exynos4210_set_clkdiv(new_index);
-		exynos4210_set_apll(new_index);
-	} else if (old_index < new_index) {
-		exynos4210_set_apll(new_index);
-		exynos4210_set_clkdiv(new_index);
-	}
-}
-
-int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
-{
-	struct device_node *np;
-	unsigned long rate;
-
-	/*
-	 * HACK: This is a temporary workaround to get access to clock
-	 * controller registers directly and remove static mappings and
-	 * dependencies on platform headers. It is necessary to enable
-	 * Exynos multi-platform support and will be removed together with
-	 * this whole driver as soon as Exynos gets migrated to use
-	 * cpufreq-cpu0 driver.
-	 */
-	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
-	if (!np) {
-		pr_err("%s: failed to find clock controller DT node\n",
-			__func__);
-		return -ENODEV;
-	}
-
-	info->cmu_regs = of_iomap(np, 0);
-	if (!info->cmu_regs) {
-		pr_err("%s: failed to map CMU registers\n", __func__);
-		return -EFAULT;
-	}
-
-	cpu_clk = clk_get(NULL, "armclk");
-	if (IS_ERR(cpu_clk))
-		return PTR_ERR(cpu_clk);
-
-	moutcore = clk_get(NULL, "moutcore");
-	if (IS_ERR(moutcore))
-		goto err_moutcore;
-
-	mout_mpll = clk_get(NULL, "mout_mpll");
-	if (IS_ERR(mout_mpll))
-		goto err_mout_mpll;
-
-	rate = clk_get_rate(mout_mpll) / 1000;
-
-	mout_apll = clk_get(NULL, "mout_apll");
-	if (IS_ERR(mout_apll))
-		goto err_mout_apll;
-
-	info->mpll_freq_khz = rate;
-	/* 800Mhz */
-	info->pll_safe_idx = L2;
-	info->cpu_clk = cpu_clk;
-	info->volt_table = exynos4210_volt_table;
-	info->freq_table = exynos4210_freq_table;
-	info->set_freq = exynos4210_set_frequency;
-
-	cpufreq = info;
-
-	return 0;
-
-err_mout_apll:
-	clk_put(mout_mpll);
-err_mout_mpll:
-	clk_put(moutcore);
-err_moutcore:
-	clk_put(cpu_clk);
-
-	pr_debug("%s: failed initialization\n", __func__);
-	return -EINVAL;
-}

drivers/cpufreq/exynos5250-cpufreq.c deleted +0 ~~-210~~

deleted file mode 100644
index c91ce69..0000000
@@ -1,210 +0,0 @@
-/*
- * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * EXYNOS5250 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/cpufreq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include "exynos-cpufreq.h"
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos5250_volt_table[] = {
-	1300000, 1250000, 1225000, 1200000, 1150000,
-	1125000, 1100000, 1075000, 1050000, 1025000,
-	1012500, 1000000,  975000,  950000,  937500,
-	925000
-};
-
-static struct cpufreq_frequency_table exynos5250_freq_table[] = {
-	{0, L0, 1700 * 1000},
-	{0, L1, 1600 * 1000},
-	{0, L2, 1500 * 1000},
-	{0, L3, 1400 * 1000},
-	{0, L4, 1300 * 1000},
-	{0, L5, 1200 * 1000},
-	{0, L6, 1100 * 1000},
-	{0, L7, 1000 * 1000},
-	{0, L8,  900 * 1000},
-	{0, L9,  800 * 1000},
-	{0, L10, 700 * 1000},
-	{0, L11, 600 * 1000},
-	{0, L12, 500 * 1000},
-	{0, L13, 400 * 1000},
-	{0, L14, 300 * 1000},
-	{0, L15, 200 * 1000},
-	{0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_5250[] = {
-	/*
-	 * values:
-	 * freq
-	 * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
-	 * clock divider for COPY, HPM, RESERVED
-	 * PLL M, P, S
-	 */
-	APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
-	APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
-	APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
-	APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
-	APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
-	APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
-	APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
-	APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
-	APLL_FREQ(900,  0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
-	APLL_FREQ(800,  0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
-	APLL_FREQ(700,  0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
-	APLL_FREQ(600,  0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
-	APLL_FREQ(500,  0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
-	APLL_FREQ(400,  0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
-	APLL_FREQ(300,  0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
-	APLL_FREQ(200,  0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
-};
-
-static void set_clkdiv(unsigned int div_index)
-{
-	unsigned int tmp;
-
-	/* Change Divider - CPU0 */
-
-	tmp = apll_freq_5250[div_index].clk_div_cpu0;
-
-	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
-
-	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
-	       & 0x11111111)
-		cpu_relax();
-
-	/* Change Divider - CPU1 */
-	tmp = apll_freq_5250[div_index].clk_div_cpu1;
-
-	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
-
-	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
-		cpu_relax();
-}
-
-static void set_apll(unsigned int index)
-{
-	unsigned int tmp;
-	unsigned int freq = apll_freq_5250[index].freq;
-
-	/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
-	clk_set_parent(moutcore, mout_mpll);
-
-	do {
-		cpu_relax();
-		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
-			>> 16);
-		tmp &= 0x7;
-	} while (tmp != 0x2);
-
-	clk_set_rate(mout_apll, freq * 1000);
-
-	/* MUX_CORE_SEL = APLL */
-	clk_set_parent(moutcore, mout_apll);
-
-	do {
-		cpu_relax();
-		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
-		tmp &= (0x7 << 16);
-	} while (tmp != (0x1 << 16));
-}
-
-static void exynos5250_set_frequency(unsigned int old_index,
-				  unsigned int new_index)
-{
-	if (old_index > new_index) {
-		set_clkdiv(new_index);
-		set_apll(new_index);
-	} else if (old_index < new_index) {
-		set_apll(new_index);
-		set_clkdiv(new_index);
-	}
-}
-
-int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
-{
-	struct device_node *np;
-	unsigned long rate;
-
-	/*
-	 * HACK: This is a temporary workaround to get access to clock
-	 * controller registers directly and remove static mappings and
-	 * dependencies on platform headers. It is necessary to enable
-	 * Exynos multi-platform support and will be removed together with
-	 * this whole driver as soon as Exynos gets migrated to use
-	 * cpufreq-cpu0 driver.
-	 */
-	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
-	if (!np) {
-		pr_err("%s: failed to find clock controller DT node\n",
-			__func__);
-		return -ENODEV;
-	}
-
-	info->cmu_regs = of_iomap(np, 0);
-	if (!info->cmu_regs) {
-		pr_err("%s: failed to map CMU registers\n", __func__);
-		return -EFAULT;
-	}
-
-	cpu_clk = clk_get(NULL, "armclk");
-	if (IS_ERR(cpu_clk))
-		return PTR_ERR(cpu_clk);
-
-	moutcore = clk_get(NULL, "mout_cpu");
-	if (IS_ERR(moutcore))
-		goto err_moutcore;
-
-	mout_mpll = clk_get(NULL, "mout_mpll");
-	if (IS_ERR(mout_mpll))
-		goto err_mout_mpll;
-
-	rate = clk_get_rate(mout_mpll) / 1000;
-
-	mout_apll = clk_get(NULL, "mout_apll");
-	if (IS_ERR(mout_apll))
-		goto err_mout_apll;
-
-	info->mpll_freq_khz = rate;
-	/* 800Mhz */
-	info->pll_safe_idx = L9;
-	info->cpu_clk = cpu_clk;
-	info->volt_table = exynos5250_volt_table;
-	info->freq_table = exynos5250_freq_table;
-	info->set_freq = exynos5250_set_frequency;
-
-	cpufreq = info;
-
-	return 0;
-
-err_mout_apll:
-	clk_put(mout_mpll);
-err_mout_mpll:
-	clk_put(moutcore);
-err_moutcore:
-	clk_put(cpu_clk);
-
-	pr_err("%s: failed initialization\n", __func__);
-	return -EINVAL;
-}

Thomas Abraham

author

2014-07-29 05:28 UTC #20 lore raw

PATCH v8 6/6 clk: samsung: remove unused clock aliases and update clock flags

In reply to Thomas Abraham

With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags.

Cc Tomasz Figa <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/clk/samsung/clk-exynos4.c    |   44 +++++++++++++++++++---------------
 drivers/clk/samsung/clk-exynos5250.c |   19 ++++++++-------
 drivers/clk/samsung/clk-exynos5420.c |   27 ++++++++++++++-------
 3 files changed, 54 insertions(+), 36 deletions(-)

drivers/clk/samsung/clk-exynos4.c +25 ~~-19~~

index 5388806..b482e39 100644
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
 	MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
 	MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
-	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
+	MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0,
+			CLK_MUX_READ_ONLY),
 	MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
 	MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
 	MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),

@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
 			CLKOUT_CMU_RIGHTBUS, 8, 6),
 
-	DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
-	DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
-	DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
-	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
-	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
-	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
-	DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
-	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
-	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+	DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_periph", "div_core2", DIV_CPU0, 12, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_atb", "mout_core", DIV_CPU0, 16, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_core2", "div_core", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
 
 	DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),

@@ -770,8 +780,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
 	DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
 	DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
-	DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
-	DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+	DIV_F(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
 			CLK_SET_RATE_PARENT, 0),
 	DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,

@@ -1194,10 +1206,6 @@ static struct samsung_clock_alias exynos4_aliases[] __initdata = {
 	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
 };
 
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
-	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
-};
-
 static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
 	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
 };

@@ -1465,8 +1473,6 @@ static void __init exynos4_clk_init(struct device_node *np,
 			ARRAY_SIZE(exynos4210_div_clks));
 		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
 			ARRAY_SIZE(exynos4210_gate_clks));
-		samsung_clk_register_alias(ctx, exynos4210_aliases,
-			ARRAY_SIZE(exynos4210_aliases));
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4210_fixed_factor_clks,
 			ARRAY_SIZE(exynos4210_fixed_factor_clks));

@@ -1501,7 +1507,7 @@ static void __init exynos4_clk_init(struct device_node *np,
 		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
 		_get_rate("sclk_apll"),	_get_rate("sclk_mpll"),
 		_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
-		_get_rate("arm_clk"));
+		_get_rate("armclk"));
 }

drivers/clk/samsung/clk-exynos5250.c +11 -8

index e19e365..1d958f1 100644
@@ -291,14 +291,14 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	/*
 	 * CMU_CPU
 	 */
-	MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
-					CLK_SET_RATE_PARENT, 0, "mout_apll"),
-	MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, CLK_MUX_READ_ONLY),
 
 	/*
 	 * CMU_CORE
 	 */
-	MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
+	MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
 
 	/*
 	 * CMU_TOP

@@ -380,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
 	/*
 	 * CMU_CPU
 	 */
-	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
-	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+	DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	/*
 	 * CMU_TOP

@@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
 	samsung_clk_of_add_provider(np, ctx);
 
 	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
-			_get_rate("div_arm2"));
+			_get_rate("armclk"));
 }
 CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);

drivers/clk/samsung/clk-exynos5420.c +18 -9

index d7ef36a..fcf365d 100644
@@ -617,10 +617,14 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 	MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 
-	MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
-	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
-	MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
-	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+				CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0,
+				CLK_MUX_READ_ONLY),
+	MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+				CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, 0,
+				CLK_MUX_READ_ONLY),
 
 	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 	MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),

@@ -776,11 +780,16 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 };
 
 static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
-	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
-	DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
-	DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
-	DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
+	DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "armclk2", "div_arm", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
 	DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-07-29 10:44 UTC #21 lore raw

PATCH v8 6/6 clk: samsung: remove unused clock aliases and update clock flags

Hi Thomas,

You can find few comments inline.

On 29.07.2014 07:28, Thomas Abraham wrote:

[snip]

Review static struct samsung_div_clock exynos4_div_clks[] __initdata = {

Quoted 1 line

(quoted diff) +0 -0

@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {

^^^

Keep in mind that following clocks are common for Exynos4210 and Exynos4x12. Have you tested this series on a board based on Exynos4212 or 4412 to verify that it does not break the legacy driver? (I would test it myself, but I am on holidays at the moment.)

Quoted 7 lines

drivers/clk/samsung/clk-exynos4.c +0 -4

 	DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
 			CLKOUT_CMU_RIGHTBUS, 8, 6),
 
-	DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
-	DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
-	DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
-	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),

[snip]

drivers/clk/samsung/clk-exynos4.c static void __init exynos4_clk_init(struct device_node *np, · line 1510

Quoted 6 lines

drivers/clk/samsung/clk-exynos4.c +1 -1

@@ -1501,7 +1507,7 @@ static void __init exynos4_clk_init(struct device_node *np,
 		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
 		_get_rate("sclk_apll"),	_get_rate("sclk_mpll"),
 		_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
-		_get_rate("arm_clk"));
+		_get_rate("armclk"));

This will not work on Exynos4412, because there is no "armclk" added for this SoC. My suggestion is to simply keep name of the clock as is, move current "arm_clk" divider to Exynos4x12-specific clocks and register Exynos4210 CPU clock as "arm_clk".

Best regards,
Tomasz

Thomas Abraham

2014-07-29 12:04 UTC #22 lore raw

PATCH v8 6/6 clk: samsung: remove unused clock aliases and update clock flags

Hi Tomasz,

Quoted 8 lines · Tomasz Figa

Hi Thomas,
You can find few comments inline.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]

Quoted 7 lines

Review static struct samsung_div_clock exynos4_div_clks[] __initdata = {
Quoted 1 line
(quoted diff) +0 -0
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
                                                        ^^^
Keep in mind that following clocks are common for Exynos4210 and Exynos4x12. Have you tested this series on a board based on Exynos4212 or 4412 to verify that it does not break the legacy driver? (I would test it myself, but I am on holidays at the moment.)

Thanks for taking time to have a look at this series. I have tested this series with the old cpufreq driver for Exynos4412 on an Origen4412 board and it works fine. These divider clocks are not directly used or referenced by the legacy cpufreq driver. So I marked them as read-only here.

Quoted 11 lines

Quoted 8 lines

drivers/clk/samsung/clk-exynos4.c +0 -4

      DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
                      CLKOUT_CMU_RIGHTBUS, 8, 6),
 
-     DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
-     DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
-     DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
-     DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),

[snip]

Quoted 11 lines

drivers/clk/samsung/clk-exynos4.c static void __init exynos4_clk_init(struct device_node *np, · line 1510
Quoted 6 lines
drivers/clk/samsung/clk-exynos4.c +1 -1
@@ -1501,7 +1507,7 @@ static void __init exynos4_clk_init(struct device_node *np,
              exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
              _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
              _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
-             _get_rate("arm_clk"));
+             _get_rate("armclk"));
This will not work on Exynos4412, because there is no "armclk" added for this SoC. My suggestion is to simply keep name of the clock as is, move current "arm_clk" divider to Exynos4x12-specific clocks and register Exynos4210 CPU clock as "arm_clk".

Ok. Will do this in the next version.

Thanks,
Thomas.

Quoted 7 lines

Best regards,
Tomasz
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Tomasz Figa

2014-07-29 12:11 UTC #23 lore raw

PATCH v8 6/6 clk: samsung: remove unused clock aliases and update clock flags

Quoted 19 lines · Thomas Abraham

Hi Tomasz,
Quoted 8 lines · Tomasz Figa
Hi Thomas,
You can find few comments inline.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]
Quoted 7 lines
Review static struct samsung_div_clock exynos4_div_clks[] __initdata = {
Quoted 1 line
(quoted diff) +0 -0
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
                                                        ^^^
Keep in mind that following clocks are common for Exynos4210 and Exynos4x12. Have you tested this series on a board based on Exynos4212 or 4412 to verify that it does not break the legacy driver? (I would test it myself, but I am on holidays at the moment.)

Quoted 5 lines

Thanks for taking time to have a look at this series. I have tested this series with the old cpufreq driver for Exynos4412 on an Origen4412 board and it works fine. These divider clocks are not directly used or referenced by the legacy cpufreq driver. So I marked them as read-only here.

OK.

Best regards,
Tomasz