ARM: exynos_defconfig: Enable PL330 DMA
Subsystems (2)
PATCH 1/1 ARM: exynos_defconfig: Enable PL330 DMA
We are getting a system hang on Arndale-Octa board if PL330_DMA is not enabled. The issue is related to [1].
AUDSS block provides the clock for audio DMA controller. Any operation on this clock requires that the clock to AUDSS block be enabled. In current configuration, the clock is gated during late boot process when all unused clocks are disabled.
When PL330_DMA is enabled, the 'apb_pclk' is enabled/disabled during amba_probe(). Otherwise, this clock is also disabled during late boot. If the AUDSS block clock is disabled by then, we get a system hang.
[1] https://lkml.org/lkml/2014/6/11/32
--- arch/arm/configs/exynos_defconfig | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/configs/exynos_defconfig +2 -0
@@ -109,6 +109,8 @@ CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y
Signature · 1 line
1.7.9.5
PATCH 1/1 ARM: exynos_defconfig: Enable PL330 DMA
Hi Tushar,
Am 31.07.2014 07:42, schrieb Tushar Behera:
Quoted 24 lines
We are getting a system hang on Arndale-Octa board if
PL330_DMAis not enabled. The issue is related to [1].AUDSS block provides the clock for audio DMA controller. Any operation on this clock requires that the clock to AUDSS block be enabled. In current configuration, the clock is gated during late boot process when all unused clocks are disabled.
When
PL330_DMAis enabled, the 'apb_pclk' is enabled/disabled duringamba_probe(). Otherwise, this clock is also disabled during late boot. If the AUDSS block clock is disabled by then, we get a system hang.[1] https://lkml.org/lkml/2014/6/11/32
Signed-off-by Tushar Behera <[email protected]>--- arch/arm/configs/exynos_defconfig | 2 ++ 1 file changed, 2 insertions(+)arch/arm/configs/exynos_defconfig +0
-0
arch/arm/configs/exynos_defconfig CONFIG_MMC_DW_IDMAC=y · line 116
Quoted 8 lines
arch/arm/configs/exynos_defconfig +2
-0@@ -109,6 +109,8 @@ CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y
Turns out I had those enabled in my local config when testing the memory patches on Arndale Octa.
multi_v7_defconfig has them already.
However, shouldn't Kconfig grow a dependency to enable those options automatically for whatever driver or SoC needs them?
Cheers,
Andreas
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg
PATCH 1/1 ARM: exynos_defconfig: Enable PL330 DMA
Hi,
Quoted 14 lines · Andreas F?rber
Hi Tushar,
Am 31.07.2014 07:42, schrieb Tushar Behera:
Quoted 11 lines
We are getting a system hang on Arndale-Octa board if
PL330_DMAis not enabled. The issue is related to [1].AUDSS block provides the clock for audio DMA controller. Any operation on this clock requires that the clock to AUDSS block be enabled. In current configuration, the clock is gated during late boot process when all unused clocks are disabled.
When
PL330_DMAis enabled, the 'apb_pclk' is enabled/disabled duringamba_probe(). Otherwise, this clock is also disabled during late boot. If the AUDSS block clock is disabled by then, we get a system hang.
Could you please explain this more?
I don't get it how apb_pclk is related to AUDSS block clock and why enabling PL330_DMA fixes the issue (I suspect that enabling PL330_DMA enables PL330 DMA AMBA device so the amba_probe() keeps apb_pclk clock enabled but what is its relation to AUDSS block clock?).
Quoted 23 lines
Quoted 12 lines
[1] https://lkml.org/lkml/2014/6/11/32
Signed-off-by Tushar Behera <[email protected]>--- arch/arm/configs/exynos_defconfig | 2 ++ 1 file changed, 2 insertions(+)arch/arm/configs/exynos_defconfig +0
-0arch/arm/configs/exynos_defconfig CONFIG_MMC_DW_IDMAC=y · line 116
Quoted 8 lines
arch/arm/configs/exynos_defconfig +2
-0@@ -109,6 +109,8 @@ CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=yReviewed-by Andreas F?rber <[email protected]>
Quoted 4 lines
Turns out I had those enabled in my local config when testing the memory patches on Arndale Octa.
multi_v7_defconfighas them already.
I observe more and more discrepancies between exynos_defconfig and multi_v7_defconfig when it comes to Exynos specific options. I wanted to avoid this by proposing exynos_defconfig removal when multiplatform support was added to Exynos. Unfortunately there was no agreement on this at that time. It would really be great if all Exynos users run on a common configuration so the testing is done more efficiently.
Quoted 2 lines
However, shouldn't
Kconfiggrow a dependency to enable those options automatically for whatever driver or SoC needs them?
Yes, moreover it is not clear yet that enabling PL330 DMA to resolve the hang issue is the right approach (to be honest it looks like a workaround for the lack of proper clock dependencies in a code).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
PATCH 1/1 ARM: exynos_defconfig: Enable PL330 DMA
Quoted 15 lines · Bartlomiej Zolnierkiewicz
Hi,
Quoted 11 lines · Andreas F?rber
Hi Tushar,
Am 31.07.2014 07:42, schrieb Tushar Behera:
Quoted 8 lines
We are getting a system hang on Arndale-Octa board if
PL330_DMAis not enabled. The issue is related to [1].AUDSS block provides the clock for audio DMA controller. Any operation on this clock requires that the clock to AUDSS block be enabled. In current configuration, the clock is gated during late boot process when all unused clocks are disabled.
Quoted 7 lines
Quoted 3 lines
Quoted 3 lines
When
PL330_DMAis enabled, the 'apb_pclk' is enabled/disabled duringamba_probe(). Otherwise, this clock is also disabled during late boot. If the AUDSS block clock is disabled by then, we get a system hang.Could you please explain this more?
I don't get it how
apb_pclkis related to AUDSS block clock and why
apb_pclk for ADMA is provided by AUDSS block on Exynos5420. Access to the control register for this clock cause the system hang when the clock to the AUDSS block is gated.
Quoted 39 lines
enabling
PL330_DMAfixes the issue (I suspect that enablingPL330_DMAenables PL330 DMA AMBA device so theamba_probe()keepsapb_pclkclock enabled but what is its relation to AUDSS block clock?).Quoted 23 lines
Quoted 12 lines
[1] https://lkml.org/lkml/2014/6/11/32
Signed-off-by Tushar Behera <[email protected]>--- arch/arm/configs/exynos_defconfig | 2 ++ 1 file changed, 2 insertions(+)arch/arm/configs/exynos_defconfig +0
-0arch/arm/configs/exynos_defconfig CONFIG_MMC_DW_IDMAC=y · line 116
Quoted 8 lines
arch/arm/configs/exynos_defconfig +2
-0@@ -109,6 +109,8 @@ CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S3C=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=yReviewed-by Andreas F?rber <[email protected]>Quoted 4 lines
Turns out I had those enabled in my local config when testing the memory patches on Arndale Octa.
multi_v7_defconfighas them already.I observe more and more discrepancies between
exynos_defconfigandmulti_v7_defconfigwhen it comes to Exynos specific options. I wanted to avoid this by proposingexynos_defconfigremoval when multiplatform support was added to Exynos. Unfortunately there was no agreement on this at that time. It would really be great if all Exynos users run on a common configuration so the testing is done more efficiently.
Quoted 7 lines
Quoted 2 lines
However, shouldn't
Kconfiggrow a dependency to enable those options automatically for whatever driver or SoC needs them?Yes, moreover it is not clear yet that enabling PL330 DMA to resolve the hang issue is the right approach (to be honest it looks like a workaround for the lack of proper clock dependencies in a code).
This, for sure, is only a temporary fix. The real fix lies in patch
[1] (mentioned in the original patch comment) which needs a bit of redesign. I am not able to work on that because of lack of time.
Quoted 6 lines
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Signature · 1 line
Tushar Behera