zmx25: Add hardware support

index 220cf4e..e403eb9 100644
@@ -287,15 +287,19 @@ enum {
 
 	MX25_PAD_CSI_D6__CSI_D6			= IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CSI_D6__GPIO_1_31		= IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D6__CSPI3_SS0		= IOMUX_PAD(0x328, 0x130, 0x17, 0, 1, NO_PAD_CTRL),
 
 	MX25_PAD_CSI_D7__CSI_D7			= IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CSI_D7__GPIO_1_6		= IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D7__CSPI3_SS1		= IOMUX_PAD(0x32c, 0x134, 0x17, 0, 1, NO_PAD_CTRL),
 
 	MX25_PAD_CSI_D8__CSI_D8			= IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CSI_D8__GPIO_1_7		= IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D8__CSPI3_SS2		= IOMUX_PAD(0x330, 0x138, 0x17, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_CSI_D9__CSI_D9			= IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CSI_D9__GPIO_4_21		= IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D9__CSPI3_SS3		= IOMUX_PAD(0x334, 0x13c, 0x17, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_CSI_MCLK__CSI_MCLK		= IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CSI_MCLK__GPIO_1_8		= IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),

@@ -315,16 +319,18 @@ enum {
 	MX25_PAD_I2C1_DAT__I2C1_DAT		= IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_I2C1_DAT__GPIO_1_13		= IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x10, 0x568, 0, NO_PAD_CTRL),
 	MX25_PAD_CSPI1_MOSI__GPIO_1_14		= IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_CSPI1_MISO__CSPI1_MISO		= IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CSPI1_MISO__GPIO_1_15		= IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_CSPI1_SS0__CSPI1_SS0		= IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS0__LD16		= IOMUX_PAD(0x358, 0x160, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS0__PWM2_PWMO		= IOMUX_PAD(0x358, 0x160, 0x14, 0, 0, 0),
 	MX25_PAD_CSPI1_SS0__GPIO_1_16		= IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x10, 0x564, 0, NO_PAD_CTRL),
 	MX25_PAD_CSPI1_SS1__I2C3_DAT		= IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
 	MX25_PAD_CSPI1_SS1__GPIO_1_17		= IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
 

@@ -341,6 +347,7 @@ enum {
 	MX25_PAD_UART1_TXD__GPIO_4_23		= IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_RTS__GPT3_CAPIN1		= IOMUX_PAD(0x370, 0x178, 0x12, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_UART1_RTS__CSI_D0		= IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
 	MX25_PAD_UART1_RTS__GPIO_4_24		= IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
 

@@ -356,6 +363,7 @@ enum {
 
 	MX25_PAD_UART2_RTS__UART2_RTS		= IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_UART2_RTS__FEC_COL		= IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__GPT1_CAPIN1		= IOMUX_PAD(0x380, 0x188, 0x13, 0x504, 2, NO_PAD_CTRL),
 	MX25_PAD_UART2_RTS__GPIO_4_28		= IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_UART2_CTS__FEC_RX_ER		= IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),

@@ -385,17 +393,21 @@ enum {
 	MX25_PAD_SD1_DATA3__FEC_CRS		= IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
 	MX25_PAD_SD1_DATA3__GPIO_2_28		= IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0x568, 1, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW0__UART3_RXD		= IOMUX_PAD(0x3a0, 0x1a8, 0x01, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_KPP_ROW0__GPIO_2_29		= IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_KPP_ROW1__KPP_ROW1		= IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW1__UART3_TXD		= IOMUX_PAD(0x3a4, 0x1ac, 0x01, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_KPP_ROW1__GPIO_2_30		= IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0x564, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__UART3_RTS		= IOMUX_PAD(0x3a8, 0x1b0, 0x01, 0, 1,  NO_PAD_CTRL),
 	MX25_PAD_KPP_ROW2__CSI_D0		= IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
 	MX25_PAD_KPP_ROW2__GPIO_2_31		= IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_KPP_ROW3__KPP_ROW3		= IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__UART3_CTS		= IOMUX_PAD(0x3ac, 0x1b4, 0x01, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_KPP_ROW3__CSI_LD1		= IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
 	MX25_PAD_KPP_ROW3__GPIO_3_0		= IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
 

@@ -471,15 +483,15 @@ enum {
 	MX25_PAD_GPIO_C__CAN2_TX		= IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
 
 	MX25_PAD_GPIO_D__GPIO_D			= IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_E__LD16			= IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
 	MX25_PAD_GPIO_D__CAN2_RX		= IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
 
 	MX25_PAD_GPIO_E__GPIO_E			= IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_F__LD17			= IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
 	MX25_PAD_GPIO_E__I2C3_CLK		= IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__LD16			= IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
 	MX25_PAD_GPIO_E__AUD7_TXD		= IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_GPIO_F__GPIO_F			= IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__LD17			= IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
 	MX25_PAD_GPIO_F__AUD7_TXC		= IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		= IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),

@@ -492,6 +504,7 @@ enum {
 	MX25_PAD_VSTBY_REQ__AUD7_TXFS		= IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_VSTBY_REQ__GPIO_3_17		= IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_VSTBY_ACK__VSTBY_ACK		= IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__EPIT1_EPITO		= IOMUX_PAD(0x40c, 0x218, 0x13, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_VSTBY_ACK__GPIO_3_18		= IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_POWER_FAIL__POWER_FAIL		= IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),

index dec11a1..d71d676 100644
@@ -58,14 +58,18 @@ typedef u64 iomux_v3_cfg_t;
 
 #define MUX_MODE_SHIFT		36
 #define MUX_MODE_MASK		((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
+#define MUX_MODE_SION_SHIFT	40
+#define MUX_MODE_SION_MASK	((iomux_v3_cfg_t)0x1 << MUX_MODE_SION_SHIFT)
 #define MUX_PAD_CTRL_SHIFT	41
 #define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
 #define MUX_SEL_INPUT_SHIFT	59
 #define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
 
 #define MUX_MODE_SION		((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
-	MUX_MODE_SHIFT)
+				MUX_MODE_SHIFT)
 #define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT(x)	((iomux_v3_cfg_t)(x) << MUX_SEL_INPUT_SHIFT)
+
 
 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
 		sel_input, pad_ctrl)					\

@@ -79,6 +83,13 @@ typedef u64 iomux_v3_cfg_t;
 #define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
 					MUX_PAD_CTRL(pad))
 
+#define NEW_SEL_INPUT(cfg, input)	(((cfg) & ~MUX_SEL_INPUT_MASK) | \
+					MUX_SEL_INPUT(input))
+
+#define SET_MODE_SION(cfg)	(((cfg) | MUX_MODE_SION_MASK))
+
+#define CLEAR_MODE_SION(cfg)	(((cfg) & ~MUX_MODE_SION_MASK))
+
 #define __NA_			0x000
 #define NO_MUX_I		0
 #define NO_PAD_I		0

index b0c26e5..987cc8d 100644
@@ -115,6 +115,15 @@ int main(void)
 	/* AHB <-> IP-Bus Interface */
 	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
 	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+
+	/* M3IF */
+	DEFINE(M3IF_CTL, offsetof(struct m3if_regs, ctl));
+
+	/* WEIM */
+	DEFINE(WEIM_CSCR0U, offsetof(struct weim_regs, cscr0u));
+	DEFINE(WEIM_CSCR0L, offsetof(struct weim_regs, cscr0l));
+	DEFINE(WEIM_CSCR0A, offsetof(struct weim_regs, cscr0a));
+
 #endif
 
 #if defined(CONFIG_MX27)

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new file mode 100644
index 0000000..f906bbe
@@ -0,0 +1,35 @@
+/*
+ * (c) 2012 Graf-Syteco, Matthias Weisser
+ * <[email protected]>
+ *
+ * polytouch.h - EDT PolyTouch capacitive touch sensor controller
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __POLYTOUCH_H
+#define __POLYTOUCH_H
+
+#define POLYTOUCH_SA		0x38	/* I2C slave address of PolyTouch */
+
+
+struct polytouch_resolution {
+	uint x;
+	uint y;
+};
+
+struct polytouch_area {
+	uint x1; /* Start position x */
+	uint y1; /* Start position y */
+	uint x2; /* End position x */
+	uint y2; /* End position y */
+};
+
+
+int polytouch_init(void);
+void polytouch_get_resolution(struct polytouch_resolution *res);
+int polytouch_is_touched(struct polytouch_area *area);
+
+#endif
+

index 595019b..96cc739 100644
@@ -540,7 +540,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_set_bus_speed,
 			 CONFIG_SYS_MXC_I2C2_SPEED,
 			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
-#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
 	defined(CONFIG_MX6)
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,

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index a17f828..dc9a298 100644
@@ -161,6 +161,126 @@ struct aips_regs {
 	u32 mpr_0_7;
 	u32 mpr_8_15;
 };
+/* LCD controller registers */
+struct lcdc_regs {
+	u32 lssar;	/* Screen Start Address */
+	u32 lsr;	/* Size */
+	u32 lvpwr;	/* Virtual Page Width */
+	u32 lcpr;	/* Cursor Position */
+	u32 lcwhb;	/* Cursor Width Height and Blink */
+	u32 lccmr;	/* Color Cursor Mapping */
+	u32 lpcr;	/* Panel Configuration */
+	u32 lhcr;	/* Horizontal Configuration */
+	u32 lvcr;	/* Vertical Configuration */
+	u32 lpor;	/* Panning Offset */
+	u32 lscr;	/* Sharp Configuration */
+	u32 lpccr;	/* PWM Contrast Control */
+	u32 ldcr;	/* DMA Control */
+	u32 lrmcr;	/* Refresh Mode Control */
+	u32 licr;	/* Interrupt Configuration */
+	u32 lier;	/* Interrupt Enable */
+	u32 lisr;	/* Interrupt Status */
+	u32 res0[3];
+	u32 lgwsar;	/* Graphic Window Start Address */
+	u32 lgwsr;	/* Graphic Window Size */
+	u32 lgwvpwr;	/* Graphic Window Virtual Page Width Regist */
+	u32 lgwpor;	/* Graphic Window Panning Offset */
+	u32 lgwpr;	/* Graphic Window Position */
+	u32 lgwcr;	/* Graphic Window Control */
+	u32 lgwdcr;	/* Graphic Window DMA Control */
+	u32 res1[5];
+	u32 lauscr;	/* AUS Mode Control */
+	u32 lausccr;	/* AUS mode Cursor Control */
+	u32 res2[31 + 64*7];
+	u32 bglut;	/* Background Lookup Table */
+	u32 gwlut;	/* Graphic Window Lookup Table */
+};
+
+/* Wireless External Interface Module Registers */
+struct weim_regs {
+	u32 cscr0u;	/* Chip Select 0 Upper Register */
+	u32 cscr0l;	/* Chip Select 0 Lower Register */
+	u32 cscr0a;	/* Chip Select 0 Addition Register */
+	u32 pad0;
+	u32 cscr1u;	/* Chip Select 1 Upper Register */
+	u32 cscr1l;	/* Chip Select 1 Lower Register */
+	u32 cscr1a;	/* Chip Select 1 Addition Register */
+	u32 pad1;
+	u32 cscr2u;	/* Chip Select 2 Upper Register */
+	u32 cscr2l;	/* Chip Select 2 Lower Register */
+	u32 cscr2a;	/* Chip Select 2 Addition Register */
+	u32 pad2;
+	u32 cscr3u;	/* Chip Select 3 Upper Register */
+	u32 cscr3l;	/* Chip Select 3 Lower Register */
+	u32 cscr3a;	/* Chip Select 3 Addition Register */
+	u32 pad3;
+	u32 cscr4u;	/* Chip Select 4 Upper Register */
+	u32 cscr4l;	/* Chip Select 4 Lower Register */
+	u32 cscr4a;	/* Chip Select 4 Addition Register */
+	u32 pad4;
+	u32 cscr5u;	/* Chip Select 5 Upper Register */
+	u32 cscr5l;	/* Chip Select 5 Lower Register */
+	u32 cscr5a;	/* Chip Select 5 Addition Register */
+	u32 pad5;
+	u32 wcr;	/* WEIM Configuration Register */
+};
+
+/* Multi-Master Memory Interface */
+struct m3if_regs {
+	u32 ctl;	/* Control Register */
+	u32 wcfg0;	/* Watermark Configuration Register 0 */
+	u32 wcfg1;	/* Watermark Configuration Register1 */
+	u32 wcfg2;	/* Watermark Configuration Register2 */
+	u32 wcfg3;	/* Watermark Configuration Register 3 */
+	u32 wcfg4;	/* Watermark Configuration Register 4 */
+	u32 wcfg5;	/* Watermark Configuration Register 5 */
+	u32 wcfg6;	/* Watermark Configuration Register 6 */
+	u32 wcfg7;	/* Watermark Configuration Register 7 */
+	u32 wcsr;	/* Watermark Control and Status Register */
+	u32 scfg0;	/* Snooping Configuration Register 0 */
+	u32 scfg1;	/* Snooping Configuration Register 1 */
+	u32 scfg2;	/* Snooping Configuration Register 2 */
+	u32 ssr0;	/* Snooping Status Register 0 */
+	u32 ssr1;	/* Snooping Status Register 1 */
+	u32 res0;
+	u32 mlwe0;	/* Master Lock WEIM CS0 Register */
+	u32 mlwe1;	/* Master Lock WEIM CS1 Register */
+	u32 mlwe2;	/* Master Lock WEIM CS2 Register */
+	u32 mlwe3;	/* Master Lock WEIM CS3 Register */
+	u32 mlwe4;	/* Master Lock WEIM CS4 Register */
+	u32 mlwe5;	/* Master Lock WEIM CS5 Register */
+};
+
+/* Pulse width modulation */
+struct pwm_regs {
+	u32 cr;	/* Control Register */
+	u32 sr;	/* Status Register */
+	u32 ir;	/* Interrupt Register */
+	u32 sar;	/* Sample Register */
+	u32 pr;	/* Period Register */
+	u32 cnr;	/* Counter Register */
+};
+
+/* Enhanced Periodic Interrupt Timer */
+struct epit_regs {
+	u32 cr;	/* Control register */
+	u32 sr;	/* Status register */
+	u32 lr;	/* Load register */
+	u32 cmpr;	/* Compare register */
+	u32 cnr;	/* Counter register */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
 
 #endif
 

@@ -255,6 +375,7 @@ struct aips_regs {
 #define IMX_SDRAM_BANK0_BASE	(0x80000000)
 #define IMX_SDRAM_BANK1_BASE	(0x90000000)
 
+/* WEIM Memory Space */
 #define IMX_WEIM_CS0		(0xA0000000)
 #define IMX_WEIM_CS1		(0xA8000000)
 #define IMX_WEIM_CS2		(0xB0000000)

@@ -270,25 +391,69 @@ struct aips_regs {
 #define NFC_BASE_ADDR		IMX_NFC_BASE
 
 /* CCM bitfields */
+#define CCM_PLL_PD_SHIFT	26
+#define CCM_PLL_PD_MASK		0xf
+#define CCM_PLL_PD(x)		(((x) & CCM_PLL_PD_MASK) << CCM_PLL_PD_SHIFT)
+#define CCM_PLL_MFD_SHIFT	16
+#define CCM_PLL_MFD_MASK	0x3ff
+#define CCM_PLL_MFD(x)		(((x) & CCM_PLL_MFD_MASK) << CCM_PLL_MFD_SHIFT)
+#define CCM_PLL_LOCK		(1 << 15)
 #define CCM_PLL_MFI_SHIFT	10
 #define CCM_PLL_MFI_MASK	0xf
+#define CCM_PLL_MFI(x)		(((x) & CCM_PLL_MFI_MASK) << CCM_PLL_MFI_SHIFT)
 #define CCM_PLL_MFN_SHIFT	0
 #define CCM_PLL_MFN_MASK	0x3ff
-#define CCM_PLL_MFD_SHIFT	16
-#define CCM_PLL_MFD_MASK	0x3ff
-#define CCM_PLL_PD_SHIFT	26
-#define CCM_PLL_PD_MASK		0xf
+#define CCM_PLL_MFN(x)		(((x) & CCM_PLL_MFN_MASK) << CCM_PLL_MFN_SHIFT)
+
+#define CCM_UPCTL_PD_SHIFT	26
+#define CCM_UPCTL_PD_MASK	0xf
+#define CCM_UPCTL_PD(x)		(((x) & CCM_PLL_PD_MASK) << CCM_PLL_PD_SHIFT)
+#define CCM_UPCTL_MFD_SHIFT	16
+#define CCM_UPCTL_MFD_MASK	0x3ff
+#define CCM_UPCTL_MFD(x)	(((x) & CCM_PLL_MFD_MASK) << CCM_PLL_MFD_SHIFT)
+#define CCM_UPCTL_LOCK		(1 << 15)
+#define CCM_UPCTL_MFI_SHIFT	10
+#define CCM_UPCTL_MFI_MASK	0xf
+#define CCM_UPCTL_MFI(x)	(((x) & CCM_PLL_MFI_MASK) << CCM_PLL_MFI_SHIFT)
+#define CCM_UPCTL_MFN_SHIFT	0
+#define CCM_UPCTL_MFN_MASK	0x3ff
+#define CCM_UPCTL_MFN(x)	(((x) & CCM_PLL_MFN_MASK) << CCM_PLL_MFN_SHIFT)
+
 #define CCM_CCTL_ARM_DIV_SHIFT	30
-#define CCM_CCTL_ARM_DIV_MASK	3
+#define CCM_CCTL_ARM_DIV_MASK	0x3
 #define CCM_CCTL_AHB_DIV_SHIFT	28
-#define CCM_CCTL_AHB_DIV_MASK	3
-#define CCM_CCTL_ARM_SRC	(1 << 14)
+#define CCM_CCTL_AHB_DIV_MASK	0x3
+#define CCM_CCTL_AHB_DIV(x)	(((x) & CCM_CCTL_AHB_DIV_MASK) << \
+					CCM_CCTL_AHB_DIV_SHIFT)
+#define CCM_CCTL_MPLL_RST_SHIFT	27
+#define CCM_CCTL_MPLL_RST_MASK	0x1
+#define CCM_CCTL_UPLL_RST_SHIFT	26
+#define CCM_CCTL_UPLL_RST_MASK	0x1
+#define CCM_CCTL_LP_CTL_SHIFT	24
+#define CCM_CCTL_LP_CTL_MASK	0x3
+
+#define CCM_CCTL_MPLL_BYP_SHIFT	22
+#define CCM_CCTL_MPLL_BYP_MASK	0x1
+#define CCM_CCTL_USB_DIV_SHIFT	16
+#define CCM_CCTL_USB_DIV_MASK	0x3f
+#define CCM_CCTL_USB_DIV(x)	(((x) & CCM_CCTL_USB_DIV_MASK) << \
+					CCM_CCTL_USB_DIV_SHIFT)
+#define CCM_CCTL_ARM_SRC_SHIFT	14
+#define CCM_CCTL_ARM_SRC_MASK	1
+#define CCM_CCTL_ARM_SRC	(1 << CCM_CCTL_ARM_SRC_SHIFT)
 #define CCM_CGR1_GPT1		(1 << 19)
 #define CCM_PERCLK_REG(clk)	(clk / 4)
 #define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
 #define CCM_PERCLK_MASK		0x3f
 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
 #define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
+#define CCM_CRDR_BT_UART_SRC_SHIFT	29
+#define CCM_CRDR_BT_UART_SRC_MASK	7
+
+#define CCM_MCR_CLKO_SEL(x)	(((x) & 0xf) << 20)
+#define CCM_MCR_CLKO_DIV(x)	(((x) & 0x3f) << 24)
+#define CCM_MCR_CLKO_EN		(1 << 30)
+
 
 /* ESDRAM Controller register bitfields */
 #define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)

@@ -345,14 +510,106 @@ struct aips_regs {
 #define WSR_UNLOCK1		0x5555
 #define WSR_UNLOCK2		0xAAAA
 
+/* MAX bits */
+#define MAX_MGPCR_AULB(x)	(((x) & 0x7) << 0)
+
+/* M3IF bits */
+#define M3IF_CTL_MRRP(x)	(((x) & 0xff) << 0)
+
+/* WEIM bits */
+/* The upper CS control register */
+#define WEIM_CSCR_U_SP		(1 << 31)
+#define WEIM_CSCR_U_WP		(1 << 30)
+#define WEIM_CSCR_U_BCD(x)	(((x) & 0x3) << 28)
+#define WEIM_CSCR_U_BCS(x)	(((x) & 0xf) << 24)
+#define WEIM_CSCR_U_PSZ(x)	(((x) & 0x3) << 22)
+#define WEIM_CSCR_U_PME		(1 << 21)
+#define WEIM_CSCR_U_SYNC	(1 << 20)
+#define WEIM_CSCR_U_DOL(x)	(((x) & 0xf) << 16)
+#define WEIM_CSCR_U_CNC(x)	(((x) & 0x3) << 14)
+#define WEIM_CSCR_U_WSC(x)	(((x) & 0x3f) << 8)
+#define WEIM_CSCR_U_EW		(1 << 7)
+#define WEIM_CSCR_U_WWS(x)	(((x) & 0x7) << 4)
+#define WEIM_CSCR_U_EDC(x)	(((x) & 0xf) << 0)
+
+/* The lower CS control register */
+#define WEIM_CSCR_L_OAE(x)	(((x) & 0xf) << 28)
+#define WEIM_CSCR_L_OEN(x)	(((x) & 0xf) << 24)
+#define WEIM_CSCR_L_EBWA(x)	(((x) & 0xf) << 20)
+#define WEIM_CSCR_L_EBWN(x)	(((x) & 0xf) << 16)
+#define WEIM_CSCR_L_CSA(x)	(((x) & 0xf) << 12)
+#define WEIM_CSCR_L_EBC		(1 << 11)
+#define WEIM_CSCR_L_DSZ(x)	(((x) & 0x7) << 8)
+#define WEIM_CSCR_L_CSN(x)	(((x) & 0xf) << 4)
+#define WEIM_CSCR_L_PSR		(1 << 3)
+#define WEIM_CSCR_L_CRE		(1 << 2)
+#define WEIM_CSCR_L_WRAP	(1 << 1)
+#define WEIM_CSCR_L_CS_EN	(1 << 0)
+
+/* The additional CS control register */
+#define WEIM_CSCR_A_EBRA(x)	(((x) & 0xf) << 28)
+#define WEIM_CSCR_A_EBRN(x)	(((x) & 0xf) << 24)
+#define WEIM_CSCR_A_RWA(x)	(((x) & 0xf) << 20)
+#define WEIM_CSCR_A_RWN(x)	(((x) & 0xf) << 16)
+#define WEIM_CSCR_A_MUM		(1 << 15)
+#define WEIM_CSCR_A_LAH(x)	(((x) & 0x3) << 13)
+#define WEIM_CSCR_A_LBN(x)	(((x) & 0x7) << 10)
+#define WEIM_CSCR_A_LBA(x)	(((x) & 0x3) << 8)
+#define WEIM_CSCR_A_DWW(x)	(((x) & 0x3) << 6)
+#define WEIM_CSCR_A_DCT(x)	(((x) & 0x3) << 4)
+#define WEIM_CSCR_A_WWU		(1 << 3)
+#define WEIM_CSCR_A_AGE		(1 << 2)
+#define WEIM_CSCR_A_CNC2	(1 << 1)
+#define WEIM_CSCR_A_FCE		(1 << 0)
+
 /* Names used in GPIO driver */
 #define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
 #define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
 #define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
 #define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	IMX_CSPI1_BASE, \
+	IMX_CSPI2_BASE, \
+	IMX_CSPI3_BASE
+
 #define CHIP_REV_1_0		0x10
 #define CHIP_REV_1_1		0x11
 #define CHIP_REV_1_2		0x12
 
+/* EPIT bitfields */
+#define EPIT_CR_EN		(1 << 0)
+#define EPIT_CR_RLD		(1 << 3)
+#define EPIT_CR_IOVW		(1 << 17)
+#define EPIT_CR_OM(x)		(((x) & 0x3) << 22)
+#define EPIT_CR_CLKSRC(x)	(((x) & 0x3) << 24)
+#define EPIT_LR(x)		(((x) & 0xFFFFFFFF) << 0)
+#define EPIT_CMPR(x)		(((x) & 0xFFFFFFFF) << 0)
+
+/* PWM bitfields */
+#define PWM_CR_EN		(1 << 0)
+#define PWM_CR_CLKSRC(x)	(((x) & 0x3) << 16)
+#define PWM_CR_POUTC(x)		(((x) & 0x3) << 18)
+
 #endif				/* _IMX_REGS_H */

index 3b45472..94ef033 100644
@@ -23,6 +23,19 @@
 #define FB_SYNC_CLK_INV		(1<<16)	/* pixel clock inverted */
 
 /*
+ * We do not enforce board code to provide empty/unused
+ * functions for this driver and define weak default
+ * functions here.
+ */
+unsigned int __board_video_init (void)
+{
+	return 0;
+}
+
+unsigned int board_video_init (void)
+			__attribute__((weak, alias("__board_video_init")));
+
+/*
  * Graphic Device
  */
 static GraphicDevice imx25fb;

@@ -117,6 +130,12 @@ void *video_hw_init(void)
 		writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1);
 	}
 
+	/*
+	 * Initialization of the access to the graphic chipset Retreive base
+	 * address of the chipset (see board/RPXClassic/eccx.c)
+	 */
+	board_video_init();
+
 	return pGD;
 }