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ARM: non-sec: Add spin table reserved memory support

PATCH New Xiubo Li 2 participants 3 messages Aug 7, 2014 – Aug 8, 2014 Arm (32-bit)

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Xiubo Li

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#0 lore raw

PATCH 1/1 ARM: non-sec: Add spin table reserved memory support

The memory where loaded the smp_waitloop code section probablly be corrupted by Linux Kernel, then the secondary cores will be running the random code, leading booting the secondary cores failed.

Signed-off-by Xiubo Li <[email protected]>
---
 arch/arm/cpu/armv7/nonsec_virt.S |  6 ++++++
 arch/arm/include/asm/nonsecure.h | 14 ++++++++++++++
 arch/arm/lib/Makefile            |  4 ++++
 arch/arm/lib/nonsecure.c         | 34 ++++++++++++++++++++++++++++++++++
 4 files changed, 58 insertions(+)
 create mode 100644 arch/arm/include/asm/nonsecure.h
 create mode 100644 arch/arm/lib/nonsecure.c
arch/arm/cpu/armv7/nonsec_virt.S +6 -0
index c334a15..e3a62af 100644
@@ -175,6 +175,9 @@ ENTRY(_nonsec_init)
 	bx	lr
 ENDPROC(_nonsec_init)
 
+.globl smp_waitloop_start
+smp_waitloop_start:
+	.word .
 #ifdef CONFIG_SMP_PEN_ADDR
 /* void __weak smp_waitloop(unsigned previous_address); */
 ENTRY(smp_waitloop)

@@ -190,6 +193,9 @@ ENTRY(smp_waitloop)
 ENDPROC(smp_waitloop)
 .weak smp_waitloop
 #endif
+.globl smp_waitloop_end
+smp_waitloop_end:
+	.word .
 
 ENTRY(_switch_to_hyp)
 	mov	r0, lr
arch/arm/include/asm/nonsecure.h new file +14 -0
new file mode 100644
index 0000000..31a4071
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARM_NONSECURE_H_
+#define _ARM_NONSECURE_H_
+
+extern ulong smp_waitloop_start;         /* start of image for smp spin table */
+extern ulong smp_waitloop_end;         /* end of image for smp spin table */
+int fdt_add_smp_waitloop_mem_rsv(void *blob);
+
+#endif /* _ARM_NONSECURE_H_ */
arch/arm/lib/Makefile +4 -0
index 321997c..fe707e9 100644
@@ -55,6 +55,10 @@ ifndef CONFIG_ARM64
 obj-y	+= cache-cp15.o
 endif
 
+ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+obj-y   += nonsecure.o
+endif
+
 # For EABI conformant tool chains, provide eabi_compat()
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
arch/arm/lib/nonsecure.c new file +34 -0
new file mode 100644
index 0000000..2a83669
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/nonsecure.h>
+#include <libfdt.h>
+
+#define PG_4K_ALING ~((1 << 12) - 1)
+#define PG_4K (1 << 12)
+
+int fdt_add_smp_waitloop_mem_rsv(void *blob)
+{
+	unsigned long rsv_start = smp_waitloop_start & PG_4K_ALING;
+	unsigned long rsv_end = smp_waitloop_end & PG_4K_ALING;
+	unsigned long rsv_size;
+	int off;
+
+	if (smp_waitloop_end == smp_waitloop_start + 0x4)
+		return 0;
+
+	if (rsv_start != rsv_end)
+		rsv_size = 2 * PG_4K;
+	else
+		rsv_size = PG_4K;
+
+	off = fdt_add_mem_rsv(blob, rsv_start, (u64)rsv_size);
+	if (off < 0)
+		printf("Failed to reserve memory for smp waitloop: %s\n",
+				fdt_strerror(off));
+
+	return off;
+}
Signature · 1 line
1.8.5
#1 lore raw

PATCH 1/1 ARM: non-sec: Add spin table reserved memory support

Quoted 4 lines · Xiubo Li

The memory where loaded the smp_waitloop code section probablly be corrupted by Linux Kernel, then the secondary cores will be running the random code, leading booting the secondary cores failed.

There is now similar reservation code in virt-dt.c. Probably some form of consolidation is in order.

Thanks,

	M.
Quoted 110 lines
Signed-off-by Xiubo Li <[email protected]>
---
 arch/arm/cpu/armv7/nonsec_virt.S |  6 ++++++
 arch/arm/include/asm/nonsecure.h | 14 ++++++++++++++
 arch/arm/lib/Makefile            |  4 ++++
 arch/arm/lib/nonsecure.c         | 34 ++++++++++++++++++++++++++++++++++
 4 files changed, 58 insertions(+)
 create mode 100644 arch/arm/include/asm/nonsecure.h
 create mode 100644 arch/arm/lib/nonsecure.c
arch/arm/cpu/armv7/nonsec_virt.S +6 -0
index c334a15..e3a62af 100644
@@ -175,6 +175,9 @@ ENTRY(_nonsec_init)
 	bx	lr
 ENDPROC(_nonsec_init)
 
+.globl smp_waitloop_start
+smp_waitloop_start:
+	.word .
 #ifdef CONFIG_SMP_PEN_ADDR
 /* void __weak smp_waitloop(unsigned previous_address); */
 ENTRY(smp_waitloop)

@@ -190,6 +193,9 @@ ENTRY(smp_waitloop)
 ENDPROC(smp_waitloop)
 .weak smp_waitloop
 #endif
+.globl smp_waitloop_end
+smp_waitloop_end:
+	.word .
 
 ENTRY(_switch_to_hyp)
 	mov	r0, lr
arch/arm/include/asm/nonsecure.h new file +14 -0
new file mode 100644
index 0000000..31a4071
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARM_NONSECURE_H_
+#define _ARM_NONSECURE_H_
+
+extern ulong smp_waitloop_start;         /* start of image for smp spin table */
+extern ulong smp_waitloop_end;         /* end of image for smp spin table */
+int fdt_add_smp_waitloop_mem_rsv(void *blob);
+
+#endif /* _ARM_NONSECURE_H_ */
arch/arm/lib/Makefile +4 -0
index 321997c..fe707e9 100644
@@ -55,6 +55,10 @@ ifndef CONFIG_ARM64
 obj-y	+= cache-cp15.o
 endif
 
+ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+obj-y   += nonsecure.o
+endif
+
 # For EABI conformant tool chains, provide eabi_compat()
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
arch/arm/lib/nonsecure.c new file +34 -0
new file mode 100644
index 0000000..2a83669
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/nonsecure.h>
+#include <libfdt.h>
+
+#define PG_4K_ALING ~((1 << 12) - 1)
+#define PG_4K (1 << 12)
+
+int fdt_add_smp_waitloop_mem_rsv(void *blob)
+{
+	unsigned long rsv_start = smp_waitloop_start & PG_4K_ALING;
+	unsigned long rsv_end = smp_waitloop_end & PG_4K_ALING;
+	unsigned long rsv_size;
+	int off;
+
+	if (smp_waitloop_end == smp_waitloop_start + 0x4)
+		return 0;
+
+	if (rsv_start != rsv_end)
+		rsv_size = 2 * PG_4K;
+	else
+		rsv_size = PG_4K;
+
+	off = fdt_add_mem_rsv(blob, rsv_start, (u64)rsv_size);
+	if (off < 0)
+		printf("Failed to reserve memory for smp waitloop: %s\n",
+				fdt_strerror(off));
+
+	return off;
+}
Signature · 1 line
Jazz is not dead. It just smells funny...
author
#2 lore raw

PATCH 1/1 ARM: non-sec: Add spin table reserved memory support

Quoted 8 lines

Subject: Re: [PATCH] ARM: non-sec: Add spin table reserved memory support

Quoted 4 lines · Xiubo Li

The memory where loaded the smp_waitloop code section probablly be corrupted by Linux Kernel, then the secondary cores will be running the random code, leading booting the secondary cores failed.

Quoted 7 lines

There is now similar reservation code in virt-dt.c. Probably some form of consolidation is in order.

Thanks,

	M.

That's good, I will check that.

Thanks,

BRs
Xiubo

Quoted 118 lines

Review

Quoted 11 lines
Signed-off-by Xiubo Li <[email protected]>
---
 arch/arm/cpu/armv7/nonsec_virt.S |  6 ++++++
 arch/arm/include/asm/nonsecure.h | 14 ++++++++++++++
 arch/arm/lib/Makefile            |  4 ++++
 arch/arm/lib/nonsecure.c         | 34 ++++++++++++++++++++++++++++++++++
 4 files changed, 58 insertions(+)
 create mode 100644 arch/arm/include/asm/nonsecure.h
 create mode 100644 arch/arm/lib/nonsecure.c
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/nonsec_virt.S

Review

Quoted 24 lines

index c334a15..e3a62af 100644

arch/arm/cpu/armv7/nonsec_virt.S +6 -0
@@ -175,6 +175,9 @@ ENTRY(_nonsec_init)
 	bx	lr
 ENDPROC(_nonsec_init)
 
+.globl smp_waitloop_start
+smp_waitloop_start:
+	.word .
 #ifdef CONFIG_SMP_PEN_ADDR
 /* void __weak smp_waitloop(unsigned previous_address); */
 ENTRY(smp_waitloop)

@@ -190,6 +193,9 @@ ENTRY(smp_waitloop)
 ENDPROC(smp_waitloop)
 .weak smp_waitloop
 #endif
+.globl smp_waitloop_end
+smp_waitloop_end:
+	.word .
 
 ENTRY(_switch_to_hyp)
 	mov	r0, lr
(quoted diff) +0 -0

b/arch/arm/include/asm/nonsecure.h

Quoted 5 lines

new file mode 100644
index 0000000..31a4071

arch/arm/include/asm/nonsecure.h line 10

Quoted 10 lines
arch/arm/include/asm/nonsecure.h new file +10 -0
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARM_NONSECURE_H_
+#define _ARM_NONSECURE_H_
+
+extern ulong smp_waitloop_start;         /* start of image for smp spin

table */

arch/arm/include/asm/nonsecure.h line 11

Quoted 1 line
arch/arm/include/asm/nonsecure.h new file +1 -0
+extern ulong smp_waitloop_end;         /* end of image for smp spin table

*/

Quoted 49 lines
arch/arm/include/asm/nonsecure.h new file +3 -0
+int fdt_add_smp_waitloop_mem_rsv(void *blob);
+
+#endif /* _ARM_NONSECURE_H_ */
arch/arm/lib/Makefile +4 -0
index 321997c..fe707e9 100644
@@ -55,6 +55,10 @@ ifndef CONFIG_ARM64
 obj-y	+= cache-cp15.o
 endif
 
+ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+obj-y   += nonsecure.o
+endif
+
 # For EABI conformant tool chains, provide eabi_compat()
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
arch/arm/lib/nonsecure.c new file +24 -0
new file mode 100644
index 0000000..2a83669
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/nonsecure.h>
+#include <libfdt.h>
+
+#define PG_4K_ALING ~((1 << 12) - 1)
+#define PG_4K (1 << 12)
+
+int fdt_add_smp_waitloop_mem_rsv(void *blob)
+{
+	unsigned long rsv_start = smp_waitloop_start & PG_4K_ALING;
+	unsigned long rsv_end = smp_waitloop_end & PG_4K_ALING;
+	unsigned long rsv_size;
+	int off;
+
+	if (smp_waitloop_end == smp_waitloop_start + 0x4)
+		return 0;
+
+	if (rsv_start != rsv_end)
+		rsv_size = 2 * PG_4K;

arch/arm/lib/nonsecure.c line 34

Quoted 10 lines
arch/arm/lib/nonsecure.c new file +10 -0
+	else
+		rsv_size = PG_4K;
+
+	off = fdt_add_mem_rsv(blob, rsv_start, (u64)rsv_size);
+	if (off < 0)
+		printf("Failed to reserve memory for smp waitloop: %s\n",
+				fdt_strerror(off));
+
+	return off;
+}

--
Jazz is not dead. It just smells funny...