Introduce cm-fx6 board (partial V2)
Subsystems (7)
v2 cover Introduce cm-fx6 board (partial V2)
This is a partial V2 of the "Introduce cm-fx6 board" series, spanning all the patches up to "arm: mx6: ddr: configure MMDC for slow_pd" (not including). This series constitutes the majority of the preparational steps for introducing the cm-fx6 board.
Changes in V2:
- Patch "spl: improve spi configuration" is replaced with "spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*", which kills CONFIG_SPL_SPI_* defines in favor of using CONFIG_SF_DEFAULT_*.
- Updated commit message of "sf: fix sf probe", renaming it in the process to "spi: mxc: fix sf probe when using mxc_spi".
- Return value handling.
Cc Igor Grinberg <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tom Rini <[email protected]>
Cc Marek Vasut <[email protected]>
Nikita Kiryanov (9):
spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
mx6: add clock enabling functions
spi: mxc: fix sf probe when using mxc_spi
mtd: spi: add support for M25PE16 and M25PX16
compulab: eeprom: add support for defining eeprom i2c bus
sata: dwc_ahsata: implement sata_port_status
i2c: imx: add macros to setup pads for multiple SoC types
arm: mx6: ddr: cleanup
arm: mx6: ddr: do not write into reserved bit
arch/arm/cpu/armv7/mx6/clock.c | 99 ++++++++++ arch/arm/cpu/armv7/mx6/ddr.c | 272 +++++++++++++------------- arch/arm/include/asm/arch-mx6/clock.h | 5 + arch/arm/include/asm/imx-common/mxc_i2c.h | 33 ++++ board/boundary/nitrogen6x/nitrogen6x.c | 5 + board/compulab/common/eeprom.c | 13 +- board/embest/mx6boards/mx6boards.c | 5 + board/freescale/mx6qsabreauto/mx6qsabreauto.c | 7 + board/freescale/mx6sabresd/mx6sabresd.c | 7 + board/freescale/mx6slevk/mx6slevk.c | 5 + board/gateworks/gw_ventana/gw_ventana.c | 7 +- board/genesi/mx51_efikamx/efikamx.c | 5 + board/ttcontrol/vision2/vision2.c | 5 + common/cmd_sf.c | 13 -- drivers/block/dwc_ahsata.c | 17 ++ drivers/mtd/spi/sf_params.c | 2 + drivers/mtd/spi/spi_spl_load.c | 6 +- drivers/spi/mxc_spi.c | 48 ++--- include/configs/am335x_evm.h | 2 - include/configs/cm_t335.h | 1 + include/configs/cm_t35.h | 1 + include/configs/cm_t54.h | 1 + include/configs/da850evm.h | 4 - include/configs/dra7xx_evm.h | 2 - include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/ks2_evm.h | 2 - include/configs/mx51_efikamx.h | 4 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/pcm051.h | 2 - include/configs/sama5d3xek.h | 2 - include/configs/siemens-am33x-common.h | 2 - include/configs/tseries.h | 2 - include/configs/vision2.h | 4 +- include/configs/zynq-common.h | 2 - include/sata.h | 1 + include/spi_flash.h | 13 ++ 39 files changed, 402 insertions(+), 207 deletions(-)
Signature · 1 line
1.9.1
PATCH v2 1/9 spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in SPL. These #defines do not allow the user to select SPI mode for the SPI flash (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in spi_spl_load.c), and duplicate information already provided by CONFIG_SF_DEFAULT_* #defines.
Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Cc Jagannadha Sutradharudu Teki <[email protected]>
Cc Tom Rini <[email protected]>
Cc Sudhakar Rajashekhara <[email protected]>
Cc Lokesh Vutla <[email protected]>
Cc Vitaly Andrianov <[email protected]>
Cc Lars Poeschel <[email protected]>
Cc Bo Shen <[email protected]>
Cc Hannes Petermaier <[email protected]>
Cc Michal Simek <[email protected]>
Cc Marek Vasut <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- New patch replacing "spl: improve spi configuration".
common/cmd_sf.c | 13 ------------- drivers/mtd/spi/spi_spl_load.c | 6 ++++-- include/configs/am335x_evm.h | 2 -- include/configs/da850evm.h | 4 ---- include/configs/dra7xx_evm.h | 2 -- include/configs/ks2_evm.h | 2 -- include/configs/pcm051.h | 2 -- include/configs/sama5d3xek.h | 2 -- include/configs/siemens-am33x-common.h | 2 -- include/configs/tseries.h | 2 -- include/configs/zynq-common.h | 2 -- include/spi_flash.h | 13 +++++++++++++ 12 files changed, 17 insertions(+), 35 deletions(-)
common/cmd_sf.c +0 -13
@@ -13,19 +13,6 @@#include <asm/io.h> -#ifndef CONFIG_SF_DEFAULT_SPEED -# define CONFIG_SF_DEFAULT_SPEED 1000000 -#endif -#ifndef CONFIG_SF_DEFAULT_MODE -# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#endif -#ifndef CONFIG_SF_DEFAULT_CS -# define CONFIG_SF_DEFAULT_CS 0 -#endif -#ifndef CONFIG_SF_DEFAULT_BUS -# define CONFIG_SF_DEFAULT_BUS 0 -#endif -static struct spi_flash *flash;
drivers/mtd/spi/spi_spl_load.c +4 -2
@@ -56,8 +56,10 @@ void spl_spi_load_image(void)* Load U-Boot image from SPI flash into RAM */ - flash =spi_flash_probe (CONFIG_SPL_SPI_BUS ,CONFIG_SPL_SPI_CS , -CONFIG_SF_DEFAULT_SPEED ,SPI_MODE_3 ); + flash =spi_flash_probe (CONFIG_SF_DEFAULT_BUS , +CONFIG_SF_DEFAULT_CS , +CONFIG_SF_DEFAULT_SPEED , +CONFIG_SF_DEFAULT_MODE );if (!flash) {puts ("SPI probe failed.\n" );hang ();
include/configs/am335x_evm.h +0 -2
@@ -381,8 +381,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000#define CONFIG_ENV_IS_IN_SPI_FLASH
include/configs/da850evm.h +0 -4
@@ -157,8 +157,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000#endif
@@ -377,8 +375,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT
include/configs/dra7xx_evm.h +0 -2
@@ -115,8 +115,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000#define CONFIG_SUPPORT_EMMC_BOOT
include/configs/ks2_evm.h +0 -2
@@ -58,8 +58,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO#define CONFIG_SPL_FRAMEWORK
include/configs/pcm051.h +0 -2
@@ -233,8 +233,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
include/configs/sama5d3xek.h +0 -2
@@ -288,8 +288,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400#endif
include/configs/siemens-am33x-common.h +0 -2
@@ -168,8 +168,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
include/configs/tseries.h +0 -2
@@ -222,8 +222,6 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000#undef CONFIG_ENV_IS_NOWHERE#define CONFIG_ENV_IS_IN_SPI_FLASH
include/configs/zynq-common.h +0 -2
@@ -305,9 +305,7 @@#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_BUS 0#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 -#define CONFIG_SPL_SPI_CS 0#endif /* for booting directly linux */
include/spi_flash.h +13 -0
@@ -19,6 +19,19 @@#include <linux/types.h> #include <linux/compiler.h> +#ifndef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +/* sf param flags */ #define SECT_4K 1 << 1#define SECT_32K 1 << 2
Signature · 1 line
1.9.1
PATCH v2 1/9 spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
Quoted 8 lines · Nikita Kiryanov
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in SPL. These #defines do not allow the user to select SPI mode for the SPI flash (there's no
CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded inspi_spl_load.c), and duplicate information already provided by CONFIG_SF_DEFAULT_* #defines.Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Quoted 11 lines
Cc Jagannadha Sutradharudu Teki <[email protected]>Cc Tom Rini <[email protected]>Cc Sudhakar Rajashekhara <[email protected]>Cc Lokesh Vutla <[email protected]>Cc Vitaly Andrianov <[email protected]>Cc Lars Poeschel <[email protected]>Cc Bo Shen <[email protected]>Cc Hannes Petermaier <[email protected]>Cc Michal Simek <[email protected]>Cc Marek Vasut <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>
Oh, right. This doesn't collide with the Kconfig work, does it ?
Otherwise, I see this as OK,
Reviewed-by Marek Vasut <[email protected]>
Best regards,
Marek Vasut
PATCH v2 1/9 spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
Quoted 21 lines · Marek Vasut
Quoted 8 lines · Nikita Kiryanov
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in SPL. These #defines do not allow the user to select SPI mode for the SPI flash (there's no
CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded inspi_spl_load.c), and duplicate information already provided by CONFIG_SF_DEFAULT_* #defines.Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Quoted 11 lines
Cc Jagannadha Sutradharudu Teki <[email protected]>Cc Tom Rini <[email protected]>Cc Sudhakar Rajashekhara <[email protected]>Cc Lokesh Vutla <[email protected]>Cc Vitaly Andrianov <[email protected]>Cc Lars Poeschel <[email protected]>Cc Bo Shen <[email protected]>Cc Hannes Petermaier <[email protected]>Cc Michal Simek <[email protected]>Cc Marek Vasut <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>
Quoted 1 line
Oh, right. This doesn't collide with the
Kconfigwork, does it ?
It does not.
(No "config CONFIG_SPL_SPI_*", nor "config CONFIG_SF_DEFAULT_*" in any Kconfig files)
Quoted 8 lines
Otherwise, I see this as OK,
Reviewed-by Marek Vasut <[email protected]>Best regards,
Marek Vasut
PATCH v2 1/9 spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
Quoted 22 lines · Nikita Kiryanov
Quoted 21 lines · Marek Vasut
Quoted 19 lines · Nikita Kiryanov
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in SPL. These #defines do not allow the user to select SPI mode for the SPI flash (there's no
CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded inspi_spl_load.c), and duplicate information already provided by CONFIG_SF_DEFAULT_* #defines.Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Cc Jagannadha Sutradharudu Teki <[email protected]>Cc Tom Rini <[email protected]>Cc Sudhakar Rajashekhara <[email protected]>Cc Lokesh Vutla <[email protected]>Cc Vitaly Andrianov <[email protected]>Cc Lars Poeschel <[email protected]>Cc Bo Shen <[email protected]>Cc Hannes Petermaier <[email protected]>Cc Michal Simek <[email protected]>Cc Marek Vasut <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>
Quoted 5 lines
Quoted 1 line
Oh, right. This doesn't collide with the
Kconfigwork, does it ?It does not.
(No "config CONFIG_SPL_SPI_*", nor "config CONFIG_SF_DEFAULT_*" in anyKconfigfiles)
Coolness, now it's up to Jagan to pick this stuff up I guess :)
Thanks,
Acked-by Marek Vasut <[email protected]>
Best regards,
Marek Vasut
PATCH v2 2/9 mx6: add clock enabling functions
In reply to Nikita KiryanovAdd functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc Stefano Babic <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- No changes.
arch/arm/cpu/armv7/mx6/clock.c | 99 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 5 ++ 2 files changed, 104 insertions(+)
arch/arm/cpu/armv7/mx6/clock.c +99 -0
@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable) }#endif +#ifdef CONFIG_NAND_MXS +void setup_gpmi_io_clk (u32 cfg) +{ +/* Disable clocks per ERR007177 from MX6 errata */ +clrbits_le32 (&imx_ccm->CCGR4, +MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | +MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK ); + +clrbits_le32 (&imx_ccm->CCGR2,MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK ); + +clrsetbits_le32 (&imx_ccm->cs2cdr, +MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | +MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | +MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK , + cfg); + +setbits_le32 (&imx_ccm->CCGR2,MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK ); +setbits_le32 (&imx_ccm->CCGR4, +MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | +MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK ); +} +#endif +void enable_usboh3_clk (unsigned char enable) {u32 reg;
@@ -49,6 +78,76 @@ void enable_usboh3_clk(unsigned char enable) } +#ifdef CONFIG_FEC_MXC +void enable_enet_clk (unsigned char enable) +{ +u32 reg; + + reg =__raw_readl (&imx_ccm->CCGR1); +if (enable) + reg |=MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK ; +else + reg &= ~(MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK ); +__raw_writel (reg, &imx_ccm->CCGR1); +} +#endif + +#ifdef CONFIG_MXC_UART +void enable_uart_clk (unsigned char enable) +{ +u32 reg, mask; + + reg =__raw_readl (&imx_ccm->CCGR5); + mask =MXC_CCM_CCGR5_UART_MASK |MXC_CCM_CCGR5_UART_SERIAL_MASK ; +if (enable) + reg |= mask; +else + reg &= ~mask; +__raw_writel (reg, &imx_ccm->CCGR5); +} +#endif + +#ifdef CONFIG_SPI +/* spi_num can be from 0 - 4 */ +int enable_cspi_clock (unsigned char enable,unsigned spi_num) +{ +u32 reg, mask; + +if (spi_num >4 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (spi_num *2 ); + reg =readl (&imx_ccm->CCGR1); +if (enable) + reg |= mask; +else + reg &= ~mask; + +__raw_writel (reg, &imx_ccm->CCGR1); +return 0 ; +} +#endif + +#ifdef CONFIG_MMC +int enable_usdhc_clk (unsigned char enable,unsigned bus_num) +{ +u32 reg, mask; + +if (bus_num >3 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (bus_num *2 +2 ); + reg =readl (&imx_ccm->CCGR6); +if (enable) + reg |= mask; +else + reg &= ~mask; + +__raw_writel (reg, &imx_ccm->CCGR6); +return 0 ; +} +#endif +#ifdef CONFIG_SYS_I2C_MXC /* i2c_num can be from 0 - 2 */ int enable_i2c_clk (unsigned char enable,unsigned i2c_num)
arch/arm/include/asm/arch-mx6/clock.h +5 -0
@@ -52,11 +52,16 @@ enum enet_freq {u32 imx_get_uartclk (void );u32 imx_get_fecclk (void );unsigned int mxc_get_clock (enum mxc_clock clk); +void setup_gpmi_io_clk (u32 cfg);void enable_ocotp_clk (unsigned char enable);void enable_usboh3_clk (unsigned char enable); +void enable_uart_clk (unsigned char enable); +int enable_cspi_clock (unsigned char enable,unsigned spi_num); +int enable_usdhc_clk (unsigned char enable,unsigned bus_num);int enable_sata_clock (void );int enable_pcie_clock (void );int enable_i2c_clk (unsigned char enable,unsigned i2c_num);void enable_ipu_clock (void );int enable_fec_anatop_clock (enum enet_freq freq); +void enable_enet_clk (unsigned char enable);#endif /* __ASM_ARCH_CLOCK_H */
Signature · 1 line
1.9.1
PATCH v2 2/9 mx6: add clock enabling functions
Hi Nikita,
Quoted 20 lines · Nikita Kiryanov
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc Stefano Babic <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>---
Changes in V2:
- No changes.arch/arm/cpu/armv7/mx6/clock.c | 99 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 5 ++ 2 files changed, 104 insertions(+)arch/arm/cpu/armv7/mx6/clock.c +0
-0@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable) }#endif
[...]
Quoted 59 lines
arch/arm/cpu/armv7/mx6/clock.c +59
-0+#ifdef CONFIG_FEC_MXC +void enable_enet_clk (unsigned char enable) +{ +u32 reg; + + reg =__raw_readl (&imx_ccm->CCGR1); +if (enable) + reg |=MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK ; +else + reg &= ~(MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK ); +__raw_writel (reg, &imx_ccm->CCGR1); +} +#endif + +#ifdef CONFIG_MXC_UART +void enable_uart_clk (unsigned char enable) +{ +u32 reg, mask; + + reg =__raw_readl (&imx_ccm->CCGR5); + mask =MXC_CCM_CCGR5_UART_MASK |MXC_CCM_CCGR5_UART_SERIAL_MASK ; +if (enable) + reg |= mask; +else + reg &= ~mask; +__raw_writel (reg, &imx_ccm->CCGR5); +} +#endif + +#ifdef CONFIG_SPI +/* spi_num can be from 0 - 4 */ +int enable_cspi_clock (unsigned char enable,unsigned spi_num) +{ +u32 reg, mask; + +if (spi_num >4 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (spi_num *2 ); + reg =readl (&imx_ccm->CCGR1); +if (enable) + reg |= mask; +else + reg &= ~mask; + +__raw_writel (reg, &imx_ccm->CCGR1); +return 0 ; +} +#endif + +#ifdef CONFIG_MMC +int enable_usdhc_clk (unsigned char enable,unsigned bus_num) +{ +u32 reg, mask; + +if (bus_num >3 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (bus_num *2 +2 );
arch/arm/cpu/armv7/mx6/clock.c void enable_usboh3_clk(unsigned char enable) · line 149
Quoted 10 lines
arch/arm/cpu/armv7/mx6/clock.c +10
-0+ reg =readl (&imx_ccm->CCGR6); +if (enable) + reg |= mask; +else + reg &= ~mask; + +__raw_writel (reg, &imx_ccm->CCGR6); + return 0; +} +#endif
In all the above functions, can we use the clrsetbits_le32() helpers?
[...]
Signature · 2 lines
Regards, Igor.
PATCH v2 2/9 mx6: add clock enabling functions
Quoted 89 lines · Igor Grinberg
Hi Nikita,
Quoted 20 lines · Nikita Kiryanov
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc Stefano Babic <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>---
Changes in V2:
- No changes.arch/arm/cpu/armv7/mx6/clock.c | 99 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 5 ++ 2 files changed, 104 insertions(+)arch/arm/cpu/armv7/mx6/clock.c +0
-0@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable) }#endif [...]
Quoted 63 lines
arch/arm/cpu/armv7/mx6/clock.c +63
-0+#ifdef CONFIG_FEC_MXC +void enable_enet_clk (unsigned char enable) +{ +u32 reg; + + reg =__raw_readl (&imx_ccm->CCGR1); +if (enable) + reg |=MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK ; +else + reg &= ~(MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK ); +__raw_writel (reg, &imx_ccm->CCGR1); +} +#endif + +#ifdef CONFIG_MXC_UART +void enable_uart_clk (unsigned char enable) +{ +u32 reg, mask; + + reg =__raw_readl (&imx_ccm->CCGR5); + mask =MXC_CCM_CCGR5_UART_MASK |MXC_CCM_CCGR5_UART_SERIAL_MASK ; +if (enable) + reg |= mask; +else + reg &= ~mask; +__raw_writel (reg, &imx_ccm->CCGR5); +} +#endif + +#ifdef CONFIG_SPI +/* spi_num can be from 0 - 4 */ +int enable_cspi_clock (unsigned char enable,unsigned spi_num) +{ +u32 reg, mask; + +if (spi_num >4 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (spi_num *2 ); + reg =readl (&imx_ccm->CCGR1); +if (enable) + reg |= mask; +else + reg &= ~mask; + +__raw_writel (reg, &imx_ccm->CCGR1); +return 0 ; +} +#endif + +#ifdef CONFIG_MMC +int enable_usdhc_clk (unsigned char enable,unsigned bus_num) +{ +u32 reg, mask; + +if (bus_num >3 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (bus_num *2 +2 ); + reg =readl (&imx_ccm->CCGR6); +if (enable) + reg |= mask; +else
Quoted 8 lines
arch/arm/cpu/armv7/mx6/clock.c void enable_usboh3_clk(unsigned char enable) · line 149
Quoted 6 lines
arch/arm/cpu/armv7/mx6/clock.c +6
-0+ reg &= ~mask; + +__raw_writel (reg, &imx_ccm->CCGR6); + return 0; +} +#endif In all the above functions, can we use the
clrsetbits_le32()helpers?
We can. V3 coming up..
Quoted 3 lines
[...]
PATCH v3 2/9 mx6: add clock enabling functions
In reply to Nikita KiryanovAdd functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc Stefano Babic <[email protected]>
Cc Igor Grinberg <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V3:
- Use (clr|set)bits_le32() where possible
Changes in V2:
- No changes.
arch/arm/cpu/armv7/mx6/clock.c | 90 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 5 ++ 2 files changed, 95 insertions(+)
arch/arm/cpu/armv7/mx6/clock.c +90 -0
@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable) }#endif +#ifdef CONFIG_NAND_MXS +void setup_gpmi_io_clk (u32 cfg) +{ +/* Disable clocks per ERR007177 from MX6 errata */ +clrbits_le32 (&imx_ccm->CCGR4, +MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | +MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK ); + +clrbits_le32 (&imx_ccm->CCGR2,MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK ); + +clrsetbits_le32 (&imx_ccm->cs2cdr, +MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | +MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | +MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK , + cfg); + +setbits_le32 (&imx_ccm->CCGR2,MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK ); +setbits_le32 (&imx_ccm->CCGR4, +MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | +MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | +MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK ); +} +#endif +void enable_usboh3_clk (unsigned char enable) {u32 reg;
@@ -49,6 +78,67 @@ void enable_usboh3_clk(unsigned char enable) } +#ifdef CONFIG_FEC_MXC +void enable_enet_clk (unsigned char enable) +{ +u32 mask =MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK ; + +if (enable) +setbits_le32 (&imx_ccm->CCGR1, mask); +else +clrbits_le32 (&imx_ccm->CCGR1, mask); +} +#endif + +#ifdef CONFIG_MXC_UART +void enable_uart_clk (unsigned char enable) +{ +u32 mask =MXC_CCM_CCGR5_UART_MASK |MXC_CCM_CCGR5_UART_SERIAL_MASK ; + +if (enable) +setbits_le32 (&imx_ccm->CCGR5, mask); +else +clrbits_le32 (&imx_ccm->CCGR5, mask); +} +#endif + +#ifdef CONFIG_SPI +/* spi_num can be from 0 - 4 */ +int enable_cspi_clock (unsigned char enable,unsigned spi_num) +{ +u32 mask; + +if (spi_num >4 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (spi_num *2 ); +if (enable) +setbits_le32 (&imx_ccm->CCGR1, mask); +else +clrbits_le32 (&imx_ccm->CCGR1, mask); + +return 0 ; +} +#endif + +#ifdef CONFIG_MMC +int enable_usdhc_clk (unsigned char enable,unsigned bus_num) +{ +u32 mask; + +if (bus_num >3 ) +return -EINVAL ; + + mask =MXC_CCM_CCGR_CG_MASK << (bus_num *2 +2 ); +if (enable) +setbits_le32 (&imx_ccm->CCGR6, mask); +else +clrbits_le32 (&imx_ccm->CCGR6, mask); + +return 0 ; +} +#endif +#ifdef CONFIG_SYS_I2C_MXC /* i2c_num can be from 0 - 2 */ int enable_i2c_clk (unsigned char enable,unsigned i2c_num)
arch/arm/include/asm/arch-mx6/clock.h +5 -0
@@ -52,11 +52,16 @@ enum enet_freq {u32 imx_get_uartclk (void );u32 imx_get_fecclk (void );unsigned int mxc_get_clock (enum mxc_clock clk); +void setup_gpmi_io_clk (u32 cfg);void enable_ocotp_clk (unsigned char enable);void enable_usboh3_clk (unsigned char enable); +void enable_uart_clk (unsigned char enable); +int enable_cspi_clock (unsigned char enable,unsigned spi_num); +int enable_usdhc_clk (unsigned char enable,unsigned bus_num);int enable_sata_clock (void );int enable_pcie_clock (void );int enable_i2c_clk (unsigned char enable,unsigned i2c_num);void enable_ipu_clock (void );int enable_fec_anatop_clock (enum enet_freq freq); +void enable_enet_clk (unsigned char enable);#endif /* __ASM_ARCH_CLOCK_H */
Signature · 1 line
1.9.1
PATCH v3 2/9 mx6: add clock enabling functions
Quoted 5 lines · Nikita Kiryanov
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc Stefano Babic <[email protected]>Cc Igor Grinberg <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>
Acked-by Igor Grinberg <[email protected]>
Thanks!
Signature · 2 lines
Regards, Igor.
PATCH v2 3/9 spi: mxc: fix sf probe when using mxc_spi
In reply to Nikita KiryanovMXC SPI driver has a feature whereas a GPIO line can be used to force CS high across multiple transactions. This is set up by embedding the GPIO information in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because the CS argument doesn't have the GPIO information in it. Instead, the user must use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will accept a naked CS value, and provide the driver with the relevant GPIO, if one is necessary.
Cc Jagannadha Sutradharudu Teki <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Eric Benard <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Tom Rini <[email protected]>
Cc Marek Vasut <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- Rewrote commit message, renaming the patch in the process (originally "sf: fix sf probe").
board/boundary/nitrogen6x/nitrogen6x.c | 5 +++ board/embest/mx6boards/mx6boards.c | 5 +++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 7 ++++ board/freescale/mx6sabresd/mx6sabresd.c | 7 ++++ board/freescale/mx6slevk/mx6slevk.c | 5 +++ board/gateworks/gw_ventana/gw_ventana.c | 7 +++- board/genesi/mx51_efikamx/efikamx.c | 5 +++ board/ttcontrol/vision2/vision2.c | 5 +++ drivers/spi/mxc_spi.c | 48 ++++++++++++++------------- include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/mx51_efikamx.h | 4 +-- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/vision2.h | 4 +-- 16 files changed, 79 insertions(+), 33 deletions(-)
board/boundary/nitrogen6x/nitrogen6x.c +5 -0
@@ -328,6 +328,11 @@ int board_mmc_init(bd_t *bis)#endif #ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio (unsigned bus,unsigned cs) +{ +return (bus ==0 && cs ==0 ) ? (IMX_GPIO_NR (3 ,19 )) :-1 ; +} +iomux_v3_cfg_t const ecspi1_pads[] = {/* SS1 */ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
board/embest/mx6boards/mx6boards.c +5 -0
@@ -284,6 +284,11 @@ iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +int board_spi_cs_gpio (unsigned bus,unsigned cs) +{ +return (bus ==0 && cs ==0 ) ? (IMX_GPIO_NR (2 ,30 )) :-1 ; +} +static void setup_spi (void ) {imx_iomux_v3_setup_multiple_pads (ecspi1_pads,ARRAY_SIZE (ecspi1_pads));
board/freescale/mx6qsabreauto/mx6qsabreauto.c +7 -0
@@ -259,6 +259,13 @@ int board_init(void)return 0 ; } +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio (unsigned bus,unsigned cs) +{ +return (bus ==0 && cs ==0 ) ? (IMX_GPIO_NR (4 ,9 )) :-1 ; +} +#endif +#ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */
board/freescale/mx6sabresd/mx6sabresd.c +7 -0
@@ -513,6 +513,13 @@ static int pfuze_init(void)return 0 ; } +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio (unsigned bus,unsigned cs) +{ +return (bus ==0 && cs ==0 ) ? (IMX_GPIO_NR (4 ,9 )) :-1 ; +} +#endif +#ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */
board/freescale/mx6slevk/mx6slevk.c +5 -0
@@ -82,6 +82,11 @@ static iomux_v3_cfg_t ecspi1_pads[] = { MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +int board_spi_cs_gpio (unsigned bus,unsigned cs) +{ +return (bus ==0 && cs ==0 ) ? (IMX_GPIO_NR (4 ,11 )) :-1 ; +} +static void setup_spi (void ) {imx_iomux_v3_setup_multiple_pads (ecspi1_pads,ARRAY_SIZE (ecspi1_pads));
board/gateworks/gw_ventana/gw_ventana.c +6 -1
@@ -353,9 +353,14 @@ iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), }; +int board_spi_cs_gpio (unsigned bus,unsigned cs) +{ +return (bus ==0 && cs ==0 ) ? (IMX_GPIO_NR (3 ,19 )) :-1 ; +} +static void setup_spi (void ) { -gpio_direction_output (CONFIG_SF_DEFAULT_CS ,1 ); +gpio_direction_output (IMX_GPIO_NR (3 ,19 ),1 );SETUP_IOMUX_PADS (ecspi1_pads); }#endif
board/genesi/mx51_efikamx/efikamx.c +5 -0
@@ -152,6 +152,11 @@ static iomux_v3_cfg_t const efikamx_spi_pads[] = {* PMIC configuration */ #ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio (unsigned bus,unsigned cs) +{ +return (bus ==0 && cs ==1 ) ?121 :-1 ; +} +static void power_init (void ) {unsigned int val;
board/ttcontrol/vision2/vision2.c +5 -0
@@ -144,6 +144,11 @@ static void setup_uart(void) } #ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 1) ? 121 : -1; +} + void spi_io_init(void) { static const iomux_v3_cfg_t spi_pads[] = {
drivers/spi/mxc_spi.c +25 -23
76 lines not on this page · raw message
include/configs/embestmx6boards.h +1 -1
@@ -100,7 +100,7 @@#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(2, 30) << 8)) +#define CONFIG_SF_DEFAULT_CS 0#define CONFIG_SF_DEFAULT_SPEED 20000000#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0#endif
include/configs/gw_ventana.h +1 -1
@@ -61,7 +61,7 @@#define CONFIG_SPI_FLASH_BAR #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) +#define CONFIG_SF_DEFAULT_CS 0/* GPIO 3-19 (21248) */ #define CONFIG_SF_DEFAULT_SPEED 30000000#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
include/configs/mx51_efikamx.h +2 -2
@@ -96,11 +96,11 @@#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST -#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) +#define CONFIG_SF_DEFAULT_CS 1#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_ENV_SPI_CS (1 | 121 << 8) +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS#define CONFIG_ENV_SPI_BUS 0#define CONFIG_ENV_SPI_MAX_HZ 25000000#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
include/configs/mx6sabre_common.h +1 -1
@@ -74,7 +74,7 @@#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 9) << 8)) +#define CONFIG_SF_DEFAULT_CS 0#define CONFIG_SF_DEFAULT_SPEED 20000000#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0#endif
include/configs/mx6slevk.h +1 -1
@@ -203,7 +203,7 @@#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 11) << 8)) +#define CONFIG_SF_DEFAULT_CS 0#define CONFIG_SF_DEFAULT_SPEED 20000000#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0#endif
include/configs/nitrogen6x.h +1 -1
@@ -53,7 +53,7 @@#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) +#define CONFIG_SF_DEFAULT_CS 0#define CONFIG_SF_DEFAULT_SPEED 25000000#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)#endif
include/configs/vision2.h +2 -2
@@ -57,11 +57,11 @@* Use gpio 4 pin 25 as chip select for SPI flash * This corresponds to gpio 121 */ -#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_CS 1#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_ENV_SPI_CS (1 | (121 << 8)) +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS#define CONFIG_ENV_SPI_BUS 0#define CONFIG_ENV_SPI_MAX_HZ 25000000#define CONFIG_ENV_SPI_MODE SPI_MODE_0
Signature · 1 line
1.9.1
PATCH v2 3/9 spi: mxc: fix sf probe when using mxc_spi
Quoted 20 lines · Nikita Kiryanov
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high across multiple transactions. This is set up by embedding the GPIO information in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because the CS argument doesn't have the GPIO information in it. Instead, the user must use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must type "sf probe 15872".This is inconsistent with the description of the sf probe command, and forces the user to be aware of implementaiton details.
Fix this by introducing a new board function:
board_spi_cs_gpio(), which will accept a naked CS value, and provide the driver with the relevant GPIO, if one is necessary.
Quoted 7 lines
Cc Jagannadha Sutradharudu Teki <[email protected]>Cc Eric Nelson <[email protected]>Cc Eric Benard <[email protected]>Cc Fabio Estevam <[email protected]>Cc Tim Harvey <[email protected]>Cc Stefano Babic <[email protected]>Cc Tom Rini <[email protected]>
Let's go with this:
Reviewed-by Marek Vasut <[email protected]>
[...]
Best regards,
Marek Vasut
PATCH v2 4/9 mtd: spi: add support for M25PE16 and M25PX16
In reply to Nikita KiryanovAdd support for M25PE16 and M25PX16
Cc Jagannadha Sutradharudu Teki <[email protected]>
Cc Marek Vasut <[email protected]>
Acked-by Marek Vasut <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- No changes.
drivers/mtd/spi/sf_params.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/mtd/spi/sf_params.c +2 -0
@@ -68,6 +68,8 @@ const struct spi_flash_params spi_flash_params_table[] = { {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0}, {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0}, {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0}, + {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0, 0}, + {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0}, {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0}, {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
Signature · 1 line
1.9.1
PATCH v2 5/9 compulab: eeprom: add support for defining eeprom i2c bus
In reply to Nikita KiryanovCreate CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM.
Cc Igor Grinberg <[email protected]>
Cc Dmitry Lifshitz <[email protected]>
Cc Tom Rini <[email protected]>
Cc Marek Vasut <[email protected]>
Acked-by Igor Grinberg <[email protected]>
Acked-by Dmitry Lifshitz <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- Check return value of i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS)
board/compulab/common/eeprom.c | 13 ++++++++++++- include/configs/cm_t335.h | 1 + include/configs/cm_t35.h | 1 + include/configs/cm_t54.h | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
board/compulab/common/eeprom.c +12 -1
@@ -31,8 +31,19 @@ static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */static int cl_eeprom_read (uint offset,uchar *buf,int len) { -return i2c_read (CONFIG_SYS_I2C_EEPROM_ADDR , offset, +int res; +unsigned int current_i2c_bus =i2c_get_bus_num (); + + res =i2c_set_bus_num (CONFIG_SYS_I2C_EEPROM_BUS ); +if (res <0 ) +return res; + + res =i2c_read (CONFIG_SYS_I2C_EEPROM_ADDR , offset,CONFIG_SYS_I2C_EEPROM_ADDR_LEN , buf, len); + +i2c_set_bus_num (current_i2c_bus); + +return res; }static int cl_eeprom_setup_layout (void )
include/configs/cm_t335.h +1 -0
@@ -107,6 +107,7 @@/* I2C Configuration */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50/* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0/* SPL */ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
include/configs/cm_t35.h +1 -0
@@ -136,6 +136,7 @@#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0#define CONFIG_I2C_MULTI_BUS /*
include/configs/cm_t54.h +1 -0
@@ -27,6 +27,7 @@#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0/* Enable SD/MMC CD and WP GPIOs */ #define OMAP_HSMMC_USE_GPIO
Signature · 1 line
1.9.1
PATCH v2 5/9 compulab: eeprom: add support for defining eeprom i2c bus
Quoted 11 lines · Nikita Kiryanov
Create
CONFIG_SYS_I2C_EEPROM_BUS#define to tell the EEPROM module what I2C bus the EEPROM is located at. Makecl_eeprom_read()switch to that bus when reading EEPROM.Cc Igor Grinberg <[email protected]>Cc Dmitry Lifshitz <[email protected]>Cc Tom Rini <[email protected]>Cc Marek Vasut <[email protected]>Acked-by Igor Grinberg <[email protected]>Acked-by Dmitry Lifshitz <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>
Reviewed-by Marek Vasut <[email protected]>
Best regards,
Marek Vasut
PATCH v2 6/9 sata: dwc_ahsata: implement sata_port_status
In reply to Nikita KiryanovDefine the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata.
Cc Stefano Babic <[email protected]>
Cc Tom Rini <[email protected]>
Cc Marek Vasut <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- Use errno values.
drivers/block/dwc_ahsata.c | 17 +++++++++++++++++ include/sata.h | 1 + 2 files changed, 18 insertions(+)
drivers/block/dwc_ahsata.c +17 -0
@@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,return blkcnt; } +int sata_port_status (int dev,int port) +{ +struct sata_port_regs *port_mmio; +struct ahci_probe_ent *probe_ent =NULL ; + +if (dev <0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE -1 )) +return -EINVAL ; + +if (sata_dev_desc[dev].priv ==NULL ) +return -ENODEV ; + + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; + port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio; + +return readl (&(port_mmio->ssts)) &&SATA_PORT_SSTS_DET_MASK ; +} +/* * SATA interface between low level driver and command layer */
include/sata.h +1 -0
@@ -9,6 +9,7 @@ ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);int sata_initialize (void );int __sata_initialize (void ); +int sata_port_status (int dev,int port);extern block_dev_desc_t sata_dev_desc[];
Signature · 1 line
1.9.1
PATCH v2 6/9 sata: dwc_ahsata: implement sata_port_status
Quoted 8 lines · Nikita Kiryanov
Define the new common function
sata_port_status()which can be used to query the sata driver for the state of ports, and implement it fordwc_ahsata.Cc Stefano Babic <[email protected]>Cc Tom Rini <[email protected]>Cc Marek Vasut <[email protected]>Signed-off-by Nikita Kiryanov <[email protected]>
Reviewed-by Marek Vasut <[email protected]>
Thanks!
Best regards,
Marek Vasut
PATCH v2 7/9 i2c: imx: add macros to setup pads for multiple SoC types
In reply to Nikita KiryanovAdd macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types.
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Acked-by Tim Harvey <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- No changes.
arch/arm/include/asm/imx-common/mxc_i2c.h | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
arch/arm/include/asm/imx-common/mxc_i2c.h +33 -0
@@ -19,6 +19,39 @@ struct i2c_pads_info {struct i2c_pin_ctrl sda; }; +#if defined(CONFIG_MX6QDL ) +#define I2C_PADS (name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \ + struct i2c_pads_info mx6q_##name = { \ + .scl = { \ + .i2c_mode = MX6Q_##scl_i2c, \ + .gpio_mode = MX6Q_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6Q_##sda_i2c, \ + .gpio_mode = MX6Q_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; \ + struct i2c_pads_info mx6s_##name = { \ + .scl = { \ + .i2c_mode = MX6DL_##scl_i2c, \ + .gpio_mode = MX6DL_##scl_gpio, \ + .gp = scl_gp, \ + }, \ + .sda = { \ + .i2c_mode = MX6DL_##sda_i2c, \ + .gpio_mode = MX6DL_##sda_gpio, \ + .gp = sda_gp, \ + } \ + }; + + +#define I2C_PADS_INFO (name) \ + (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \ + &mx6q_##name : &mx6s_##name +#endif +void setup_i2c (unsigned i2c_index,int speed,int slave_addr,struct i2c_pads_info *p); void bus_i2c_init(void *base, int speed, int slave_addr,
Signature · 1 line
1.9.1
PATCH v2 8/9 arm: mx6: ddr: cleanup
In reply to Nikita KiryanovNo functional changes.
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Acked-by Tim Harvey <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- No changes.
arch/arm/cpu/armv7/mx6/ddr.c | 272 +++++++++++++++++++++---------------------- 1 file changed, 134 insertions(+), 138 deletions(-)
arch/arm/cpu/armv7/mx6/ddr.c +134 -138
@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,*/ #define MR (val, ba, cmd, cs1) \ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) -void mx6_dram_cfg (const struct mx6_ddr_sysinfo *i, -const struct mx6_mmdc_calibration *c, -const struct mx6_ddr3_cfg *m) +void mx6_dram_cfg (const struct mx6_ddr_sysinfo *sysinfo, +const struct mx6_mmdc_calibration *calib, +const struct mx6_ddr3_cfg *ddr3_cfg) {volatile struct mmdc_p_regs *mmdc0;volatile struct mmdc_p_regs *mmdc1; -u32 reg; +u32 val;u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;u8 todt_idle_off =0x4 ;/* from DDR3 Script Aid spreadsheet */ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; -u16 CS0_END ; +u16 cs0_end;u16 tdllk =0x1ff ;/* DLL locking time: 512 cycles (JEDEC DDR3) */ int clkper;/* clock period in picoseconds */ int clock;/* clock freq in mHz */
@@ -214,13 +214,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, clock =400 ; tcwl =3 ; } - clkper = (1000 *1000 )/clock;/* ps */ + clkper = (1000 *1000 ) / clock;/* pico seconds */ todtlon = tcwl; taxpd = tcwl; tanpd = tcwl; - tcwl = tcwl; -switch (m->density) { +switch (ddr3_cfg->density) {case 1 :/* 1Gb per chip */ trfc =DIV_ROUND_UP (110000 , clkper) -1 ; txs =DIV_ROUND_UP (120000 , clkper) -1 ;
@@ -239,80 +238,84 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,break ;default :/* invalid density */ -printf ("invalid chip density\n" ); +puts ("invalid chip density\n" );hang ();break ; } txpr = txs; -switch (m->mem_speed) { +switch (ddr3_cfg->mem_speed) {case 800 : - txp =DIV_ROUND_UP (MAX (3 *clkper,7500 ), clkper) -1 ; - tcke =DIV_ROUND_UP (MAX (3 *clkper,7500 ), clkper) -1 ; -if (m->pagesz ==1 ) { + txp =DIV_ROUND_UP (MAX (3 * clkper,7500 ), clkper) -1 ; + tcke =DIV_ROUND_UP (MAX (3 * clkper,7500 ), clkper) -1 ; +if (ddr3_cfg->pagesz ==1 ) { tfaw =DIV_ROUND_UP (40000 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,10000 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,10000 ), clkper) -1 ; }else { tfaw =DIV_ROUND_UP (50000 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,10000 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,10000 ), clkper) -1 ; }break ;case 1066 : - txp =DIV_ROUND_UP (MAX (3 *clkper,7500 ), clkper) -1 ; - tcke =DIV_ROUND_UP (MAX (3 *clkper,5625 ), clkper) -1 ; -if (m->pagesz ==1 ) { + txp =DIV_ROUND_UP (MAX (3 * clkper,7500 ), clkper) -1 ; + tcke =DIV_ROUND_UP (MAX (3 * clkper,5625 ), clkper) -1 ; +if (ddr3_cfg->pagesz ==1 ) { tfaw =DIV_ROUND_UP (37500 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,7500 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,7500 ), clkper) -1 ; }else { tfaw =DIV_ROUND_UP (50000 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,10000 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,10000 ), clkper) -1 ; }break ;case 1333 : - txp =DIV_ROUND_UP (MAX (3 *clkper,6000 ), clkper) -1 ; - tcke =DIV_ROUND_UP (MAX (3 *clkper,5625 ), clkper) -1 ; -if (m->pagesz ==1 ) { + txp =DIV_ROUND_UP (MAX (3 * clkper,6000 ), clkper) -1 ; + tcke =DIV_ROUND_UP (MAX (3 * clkper,5625 ), clkper) -1 ; +if (ddr3_cfg->pagesz ==1 ) { tfaw =DIV_ROUND_UP (30000 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,6000 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,6000 ), clkper) -1 ; }else { tfaw =DIV_ROUND_UP (45000 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,7500 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,7500 ), clkper) -1 ; }break ;case 1600 : - txp =DIV_ROUND_UP (MAX (3 *clkper,6000 ), clkper) -1 ; - tcke =DIV_ROUND_UP (MAX (3 *clkper,5000 ), clkper) -1 ; -if (m->pagesz ==1 ) { + txp =DIV_ROUND_UP (MAX (3 * clkper,6000 ), clkper) -1 ; + tcke =DIV_ROUND_UP (MAX (3 * clkper,5000 ), clkper) -1 ; +if (ddr3_cfg->pagesz ==1 ) { tfaw =DIV_ROUND_UP (30000 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,6000 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,6000 ), clkper) -1 ; }else { tfaw =DIV_ROUND_UP (40000 , clkper) -1 ; - trrd =DIV_ROUND_UP (MAX (4 *clkper,7500 ), clkper) -1 ; + trrd =DIV_ROUND_UP (MAX (4 * clkper,7500 ), clkper) -1 ; }break ;default : -printf ("invalid memory speed\n" ); +puts ("invalid memory speed\n" );hang ();break ; } - txpdll =DIV_ROUND_UP (MAX (10 *clkper,24000 ), clkper) -1 ; - tcl =DIV_ROUND_UP (m->trcd, clkper/10 ) -3 ; - tcksre =DIV_ROUND_UP (MAX (5 *clkper,10000 ), clkper); - tcksrx = tcksre; + txpdll =DIV_ROUND_UP (MAX (10 * clkper,24000 ), clkper) -1 ; + tcksre =DIV_ROUND_UP (MAX (5 * clkper,10000 ), clkper); taonpd =DIV_ROUND_UP (2000 , clkper) -1 ; + tcksrx = tcksre; taofpd = taonpd; - trp =DIV_ROUND_UP (m->trcd, clkper/10 ) -1 ; + twr =DIV_ROUND_UP (15000 , clkper) -1 ; + tmrd =DIV_ROUND_UP (MAX (12 * clkper,15000 ), clkper) -1 ; + trc =DIV_ROUND_UP (ddr3_cfg->trcmin, clkper /10 ) -1 ; + tras =DIV_ROUND_UP (ddr3_cfg->trasmin, clkper /10 ) -1 ; + tcl =DIV_ROUND_UP (ddr3_cfg->trcd, clkper /10 ) -3 ; + trp =DIV_ROUND_UP (ddr3_cfg->trcd, clkper /10 ) -1 ; + twtr =ROUND (MAX (4 * clkper,7500 ) / clkper,1 ) -1 ; trcd = trp; - trc =DIV_ROUND_UP (m->trcmin, clkper/10 ) -1 ; - tras =DIV_ROUND_UP (m->trasmin, clkper/10 ) -1 ; - twr =DIV_ROUND_UP (15000 , clkper) -1 ; - tmrd =DIV_ROUND_UP (MAX (12 *clkper,15000 ), clkper) -1 ; - twtr =ROUND (MAX (4 *clkper,7500 )/clkper,1 ) -1 ; trtp = twtr; -CS0_END = ((4 *i->cs_density) <=120 ) ? (4 *i->cs_density)+7 :127 ; -debug ("density:%d Gb (%d Gb per chip)\n" , i->cs_density, m->density); + cs0_end = (4 * sysinfo->cs_density <=120 ) ? +4 * sysinfo->cs_density +7 : +127 ; + +debug ("density:%d Gb (%d Gb per chip)\n" , + sysinfo->cs_density, ddr3_cfg->density);debug ("clock: %dMHz (%d ps)\n" , clock, clkper); -debug ("memspd:%d\n" , m->mem_speed); +debug ("memspd:%d\n" , ddr3_cfg->mem_speed);debug ("tcke=%d\n" , tcke);debug ("tcksrx=%d\n" , tcksrx);debug ("tcksre=%d\n" , tcksre);
@@ -339,11 +342,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,debug ("twtr=%d\n" , twtr);debug ("trrd=%d\n" , trrd);debug ("txpr=%d\n" , txpr); -debug ("CS0_END=%d\n" ,CS0_END ); -debug ("ncs=%d\n" , i->ncs); -debug ("Rtt_wr=%d\n" , i->rtt_wr); -debug ("Rtt_nom=%d\n" , i->rtt_nom); -debug ("SRT=%d\n" , m->SRT); +debug ("cs0_end=%d\n" , cs0_end); +debug ("ncs=%d\n" , sysinfo->ncs); +debug ("Rtt_wr=%d\n" , sysinfo->rtt_wr); +debug ("Rtt_nom=%d\n" , sysinfo->rtt_nom); +debug ("SRT=%d\n" , ddr3_cfg->SRT);debug ("tcl=%d\n" , tcl);debug ("twr=%d\n" , twr);
@@ -353,137 +356,130 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,* see: * appnote, ddr3 spreadsheet */ - mmdc0->mpwldectrl0 = c->p0_mpwldectrl0; - mmdc0->mpwldectrl1 = c->p0_mpwldectrl1; - mmdc0->mpdgctrl0 = c->p0_mpdgctrl0; - mmdc0->mpdgctrl1 = c->p0_mpdgctrl1; - mmdc0->mprddlctl = c->p0_mprddlctl; - mmdc0->mpwrdlctl = c->p0_mpwrdlctl; -if (i->dsize >1 ) { - mmdc1->mpwldectrl0 = c->p1_mpwldectrl0; - mmdc1->mpwldectrl1 = c->p1_mpwldectrl1; - mmdc1->mpdgctrl0 = c->p1_mpdgctrl0; - mmdc1->mpdgctrl1 = c->p1_mpdgctrl1; - mmdc1->mprddlctl = c->p1_mprddlctl; - mmdc1->mpwrdlctl = c->p1_mpwrdlctl; + mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; + mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; + mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; + mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; + mmdc0->mprddlctl = calib->p0_mprddlctl; + mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; +if (sysinfo->dsize >1 ) { + mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0; + mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1; + mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0; + mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1; + mmdc1->mprddlctl = calib->p1_mprddlctl; + mmdc1->mpwrdlctl = calib->p1_mpwrdlctl; }/* Read data DQ Byte0-3 delay */ - mmdc0->mprddqby0dl = (u32 )0x33333333 ; - mmdc0->mprddqby1dl = (u32 )0x33333333 ; -if (i->dsize >0 ) { - mmdc0->mprddqby2dl = (u32 )0x33333333 ; - mmdc0->mprddqby3dl = (u32 )0x33333333 ; + mmdc0->mprddqby0dl =0x33333333 ; + mmdc0->mprddqby1dl =0x33333333 ; +if (sysinfo->dsize >0 ) { + mmdc0->mprddqby2dl =0x33333333 ; + mmdc0->mprddqby3dl =0x33333333 ; } -if (i->dsize >1 ) { - mmdc1->mprddqby0dl = (u32 )0x33333333 ; - mmdc1->mprddqby1dl = (u32 )0x33333333 ; - mmdc1->mprddqby2dl = (u32 )0x33333333 ; - mmdc1->mprddqby3dl = (u32 )0x33333333 ; + +if (sysinfo->dsize >1 ) { + mmdc1->mprddqby0dl =0x33333333 ; + mmdc1->mprddqby1dl =0x33333333 ; + mmdc1->mprddqby2dl =0x33333333 ; + mmdc1->mprddqby3dl =0x33333333 ; }/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ - reg = (i->rtt_nom ==2 ) ?0x00011117 :0x00022227 ; - mmdc0->mpodtctrl = reg; -if (i->dsize >1 ) - mmdc1->mpodtctrl = reg; + val = (sysinfo->rtt_nom ==2 ) ?0x00011117 :0x00022227 ; + mmdc0->mpodtctrl = val; +if (sysinfo->dsize >1 ) + mmdc1->mpodtctrl = val;/* complete calibration */ - reg = (1 <<11 );/* Force measurement on delay-lines */ - mmdc0->mpmur0 = reg; -if (i->dsize >1 ) - mmdc1->mpmur0 = reg; + val = (1 <<11 );/* Force measurement on delay-lines */ + mmdc0->mpmur0 = val; +if (sysinfo->dsize >1 ) + mmdc1->mpmur0 = val;/* Step 1: configuration request */ mmdc0->mdscr = (u32)(1 <<15 );/* config request */ /* Step 2: Timing configuration */ - reg = (trfc <<24 ) | (txs <<16 ) | (txp <<13 ) | (txpdll <<9 ) | - (tfaw <<4 ) | tcl; - mmdc0->mdcfg0 = reg; - reg = (trcd <<29 ) | (trp <<26 ) | (trc <<21 ) | (tras <<16 ) | - (1 <<15 ) |/* trpa */ - (twr <<9 ) | (tmrd <<5 ) | tcwl; - mmdc0->mdcfg1 = reg; - reg = (tdllk <<16 ) | (trtp <<6 ) | (twtr <<3 ) | trrd; - mmdc0->mdcfg2 = reg; - reg = (taofpd <<27 ) | (taonpd <<24 ) | (tanpd <<20 ) | (taxpd <<16 ) | - (todtlon <<12 ) | (todt_idle_off <<4 ); - mmdc0->mdotc = reg; - mmdc0->mdasp =CS0_END ;/* CS addressing */ + mmdc0->mdcfg0 = (trfc <<24 ) | (txs <<16 ) | (txp <<13 ) | + (txpdll <<9 ) | (tfaw <<4 ) | tcl; + mmdc0->mdcfg1 = (trcd <<29 ) | (trp <<26 ) | (trc <<21 ) | + (tras <<16 ) | (1 <<15 )/* trpa */ | + (twr <<9 ) | (tmrd <<5 ) | tcwl; + mmdc0->mdcfg2 = (tdllk <<16 ) | (trtp <<6 ) | (twtr <<3 ) | trrd; + mmdc0->mdotc = (taofpd <<27 ) | (taonpd <<24 ) | (tanpd <<20 ) | + (taxpd <<16 ) | (todtlon <<12 ) | (todt_idle_off <<4 ); + mmdc0->mdasp = cs0_end;/* CS addressing */ /* Step 3: Configure DDR type */ - reg = (i->cs1_mirror <<19 ) | (i->walat <<16 ) | (i->bi_on <<12 ) | - (i->mif3_mode <<9 ) | (i->ralat <<6 ); - mmdc0->mdmisc = reg; + mmdc0->mdmisc = (sysinfo->cs1_mirror <<19 ) | (sysinfo->walat <<16 ) | + (sysinfo->bi_on <<12 ) | (sysinfo->mif3_mode <<9 ) | + (sysinfo->ralat <<6 );/* Step 4: Configure delay while leaving reset */ - reg = (txpr <<16 ) | (i->sde_to_rst <<8 ) | (i->rst_to_cke <<0 ); - mmdc0->mdor = reg; + mmdc0->mdor = (txpr <<16 ) | (sysinfo->sde_to_rst <<8 ) | + (sysinfo->rst_to_cke <<0 );/* Step 5: Configure DDR physical parameters (density and burst len) */ - reg = (m->rowaddr -11 ) <<24 |/* ROW */ - (m->coladdr -9 ) <<20 |/* COL */ - (1 <<19 ) |/* Burst Length = 8 for DDR3 */ - (i->dsize <<16 );/* DDR data bus size */ - mmdc0->mdctl = reg; + mmdc0->mdctl = (ddr3_cfg->rowaddr -11 ) <<24 |/* ROW */ + (ddr3_cfg->coladdr -9 ) <<20 |/* COL */ + (1 <<19 ) |/* Burst Length = 8 for DDR3 */ + (sysinfo->dsize <<16 );/* DDR data bus size */ /* Step 6: Perform ZQ calibration */ - reg = (u32 )0xa1390001 ;/* one-time HW ZQ calib */ - mmdc0->mpzqhwctrl = reg; -if (i->dsize >1 ) - mmdc1->mpzqhwctrl = reg; + val =0xa1390001 ;/* one-time HW ZQ calib */ + mmdc0->mpzqhwctrl = val; +if (sysinfo->dsize >1 ) + mmdc1->mpzqhwctrl = val;/* Step 7: Enable MMDC with desired chip select */ - reg = mmdc0->mdctl | - (1 <<31 ) |/* SDE_0 for CS0 */ - ((i->ncs ==2 ) ?1 :0 ) <<30 ;/* SDE_1 for CS1 */ - mmdc0->mdctl = reg; + mmdc0->mdctl |= (1 <<31 ) |/* SDE_0 for CS0 */ + ((sysinfo->ncs ==2 ) ?1 :0 ) <<30 ;/* SDE_1 for CS1 */ /* Step 8: Write Mode Registers to Init DDR3 devices */ -for (cs =0 ; cs < i->ncs; cs++) { +for (cs =0 ; cs < sysinfo->ncs; cs++) {/* MR2 */ - reg = (i->rtt_wr &3 ) <<9 | (m->SRT &1 ) <<7 | + val = (sysinfo->rtt_wr &3 ) <<9 | (ddr3_cfg->SRT &1 ) <<7 | ((tcwl -3 ) &3 ) <<3 ; - mmdc0->mdscr = (u32 )MR (reg,2 ,3 , cs); + mmdc0->mdscr =MR (val,2 ,3 , cs);/* MR3 */ - mmdc0->mdscr = (u32 )MR (0 ,3 ,3 , cs); + mmdc0->mdscr =MR (0 ,3 ,3 , cs);/* MR1 */ - reg = ((i->rtt_nom &1 ) ?1 :0 ) <<2 | - ((i->rtt_nom &2 ) ?1 :0 ) <<6 ; - mmdc0->mdscr = (u32 )MR (reg,1 ,3 , cs); - reg = ((tcl -1 ) <<4 ) |/* CAS */ + val = ((sysinfo->rtt_nom &1 ) ?1 :0 ) <<2 | + ((sysinfo->rtt_nom &2 ) ?1 :0 ) <<6 ; + mmdc0->mdscr =MR (val,1 ,3 , cs); +/* MR0 */ + val = ((tcl -1 ) <<4 ) |/* CAS */ (1 <<8 ) |/* DLL Reset */ ((twr -3 ) <<9 );/* Write Recovery */ -/* MR0 */ - mmdc0->mdscr = (u32 )MR (reg,0 ,3 , cs); + mmdc0->mdscr =MR (val,0 ,3 , cs);/* ZQ calibration */ - reg = (1 <<10 ); - mmdc0->mdscr = (u32 )MR (reg,0 ,4 , cs); + val = (1 <<10 ); + mmdc0->mdscr =MR (val,0 ,4 , cs); }/* Step 10: Power down control and self-refresh */ - reg = (tcke &0x7 ) <<16 | -5 <<12 |/* PWDT_1: 256 cycles */ -5 <<8 |/* PWDT_0: 256 cycles */ -1 <<6 |/* BOTH_CS_PD */ - (tcksrx &0x7 ) <<3 | - (tcksre &0x7 ); - mmdc0->mdpdc = reg; - mmdc0->mapsr = (u32 )0x00011006 ;/* ADOPT power down enabled */ + mmdc0->mdpdc = (tcke &0x7 ) <<16 | +5 <<12 |/* PWDT_1: 256 cycles */ +5 <<8 |/* PWDT_0: 256 cycles */ +1 <<6 |/* BOTH_CS_PD */ + (tcksrx &0x7 ) <<3 | + (tcksre &0x7 ); + mmdc0->mapsr =0x00011006 ;/* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ - mmdc0->mpzqhwctrl = (u32 )0xa1390003 ; -if (i->dsize >1 ) - mmdc1->mpzqhwctrl = (u32 )0xa1390003 ; + val =0xa1390003 ; + mmdc0->mpzqhwctrl = val; +if (sysinfo->dsize >1 ) + mmdc1->mpzqhwctrl = val;/* Step 12: Configure and activate periodic refresh */ - reg = (1 <<14 ) |/* REF_SEL: Periodic refresh cycles of 32kHz */ - (7 <<11 );/* REFR: Refresh Rate - 8 refreshes */ - mmdc0->mdref = reg; + mmdc0->mdref = (1 <<14 ) |/* REF_SEL: Periodic refresh cycle: 32kHz */ + (7 <<11 );/* REFR: Refresh Rate - 8 refreshes */ /* Step 13: Deassert config request - init complete */ - mmdc0->mdscr = (u32 )0x00000000 ; + mmdc0->mdscr =0x00000000 ;/* wait for auto-ZQ calibration to complete */ mdelay (1 );
Signature · 1 line
1.9.1
PATCH v2 9/9 arm: mx6: ddr: do not write into reserved bit
In reply to Nikita KiryanovBit 16 in mapsr register is in a reserved field. Don't write to it.
Cc Stefano Babic <[email protected]>
Cc Tim Harvey <[email protected]>
Acked-by Tim Harvey <[email protected]>
Signed-off-by Nikita Kiryanov <[email protected]>
---
Changes in V2:
- No changes.
arch/arm/cpu/armv7/mx6/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/cpu/armv7/mx6/ddr.c +1 -1
@@ -466,7 +466,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,1 <<6 |/* BOTH_CS_PD */ (tcksrx &0x7 ) <<3 | (tcksre &0x7 ); - mmdc0->mapsr =0x00011006 ;/* ADOPT power down enabled */ + mmdc0->mapsr =0x00001006 ;/* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ val =0xa1390003 ;
Signature · 1 line
1.9.1