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iMX6: Disable the L2 before chaning the PL310 latency

PATCH New Ye.Li 2 participants 3 messages Aug 20, 2014 – Sep 9, 2014 Arm (32-bit)

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Ye.Li

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#0 lore raw

PATCH 1/1 iMX6: Disable the L2 before chaning the PL310 latency

From: "Ye.Li" <[email protected]>

The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting.

Signed-off-by Ye.Li <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c |    3 +++
 1 file changed, 3 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +3 -0
index f20bdeb..cc2231a 100644
@@ -394,6 +394,9 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
+	/* Must disable the L2 before changing the latency parameters */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 iMX6: Disable the L2 before chaning the PL310 latency

Hi Ye,

Quoted 19 lines · Ye.Li

From: "Ye.Li" <[email protected]>

The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting.

Signed-off-by Ye.Li <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c |    3 +++
 1 file changed, 3 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +0 -0
index f20bdeb..cc2231a 100644

arch/arm/cpu/armv7/mx6/soc.c void v7_outer_cache_enable(void) · line 402

Quoted 9 lines
arch/arm/cpu/armv7/mx6/soc.c +3 -0
@@ -394,6 +394,9 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
+	/* Must disable the L2 before changing the latency parameters */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);
Acked-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#2 lore raw

PATCH 1/1 iMX6: Disable the L2 before chaning the PL310 latency

In reply to Ye.Li
Quoted 11 lines · Ye.Li

From: "Ye.Li" <[email protected]>

The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting.

Signed-off-by Ye.Li <[email protected]>

---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================