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arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support

PATCH Superseded Alison Wang 4 participants 22 messages Aug 19, 2014 – Aug 20, 2014

Subsystems (8)
Network drivers Arm (32-bit) PowerPC Arm i.MX and Layerscape +4 more subsystems

v5 of 6 Superseded Latest is v6 →

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Alison Wang

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#0 lore raw

v5 cover arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support

This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board.

The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability.

For the detail information about LS1021AQDS/TWR board, please refer to README in the patch.

Changes in v5:
- Remove private MDIO read/write functions. Handling
the board muxing between the RGMII/SGMII phys in eth.c.
- Add detailed commit messages for I2C patch.
- Adjust the video patches' order.
- Remove LETECH patch, as it is used internally, maybe send out later.

Changes in v4:
- Add commit messages.

Changes in v3:
- Fix checkpatch errors.
- Add I2C 3 support.
- Split arm: ls102xa: Add etsec support for LS102xA into 3 patches. The 3 patches:
net: mdio: Add private MDIO read/write function,
net: mdio: Use mb() to be compatible for both ARM and PowerPC,
ls102xa: etsec: Add etsec support for LS102xA.
- Use mb() to be compatible for both ARM and PowerPC.
- Update to Kconfig.
- Add new patches:
net: tsec: Remove tx snooping support from LS1
serial: lpuart: add 32-bit registers lpuart support
arm: ls102xa: Add LETECH support for LS1021AQDS/TWR board
video: dcu: Add Sii9022A HDMI Transmitter support
video: dcu: Add DCU driver support
ls102xa: dcu: Add platform support for DCU on LS1021ATWR board

Changes in v2:
- Add serdes support.
- Update DDR frequency and data rate information.
- Fix overflow condition error for the timer.
- Add private mdio read and write support.
- Remove ethaddr/ipaddr setting.
- Add board maintainer.
- Add serdes and multiple ethernet controllers support.
- Add new patch:
arm: ls102xa: Add basic support for LS1021ATWR board

author
#1 lore raw

PATCH v5 1/16 arm: ls102xa: Add Freescale LS102xA SoC support

From: Wang Huan <[email protected]>

The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability.

Signed-off-by Alison Wang <[email protected]>
Signed-off-by Jason Jin <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: Fix checkpatch errors.
v2: Add serdes support.
Update DDR frequency and data rate information. Fix overflow condition error for the timer.

 arch/arm/cpu/armv7/ls102xa/Makefile               |  12 +
 arch/arm/cpu/armv7/ls102xa/clock.c                | 130 ++++++
 arch/arm/cpu/armv7/ls102xa/cpu.c                  | 103 +++++
 arch/arm/cpu/armv7/ls102xa/fdt.c                  | 128 ++++++
 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c       | 119 ++++++
 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h       |  12 +
 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c       |  41 ++
 arch/arm/cpu/armv7/ls102xa/timer.c                | 127 ++++++
 arch/arm/include/asm/arch-ls102xa/clock.h         |  23 ++
 arch/arm/include/asm/arch-ls102xa/config.h        |  71 ++++
 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h    |  33 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 461 ++++++++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/imx-regs.h      |  53 +++
 arch/arm/include/asm/config.h                     |   4 +
 arch/arm/include/asm/io.h                         |   8 +-
 drivers/watchdog/Makefile                         |   2 +-
 16 files changed, 1325 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile
 create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
 create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h
arch/arm/cpu/armv7/ls102xa/Makefile new file +12 -0
new file mode 100644
index 0000000..d82ce8d
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y	+= cpu.o
+obj-y	+= clock.o
+obj-y	+= timer.o
+
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
arch/arm/cpu/armv7/ls102xa/clock.c new file +130 -0

130 lines not on this page · raw message

arch/arm/cpu/armv7/ls102xa/cpu.c new file +103 -0

103 lines not on this page · raw message

arch/arm/cpu/armv7/ls102xa/fdt.c new file +128 -0

128 lines not on this page · raw message

arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c new file +119 -0

119 lines not on this page · raw message

arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h new file +12 -0
new file mode 100644
index 0000000..834aa53
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_LS1_SERDES_H
+#define __FSL_LS1_SERDES_H
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+#endif /* __FSL_LS1_SERDES_H */
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c new file +41 -0

41 lines not on this page · raw message

arch/arm/cpu/armv7/ls102xa/timer.c new file +127 -0

127 lines not on this page · raw message

arch/arm/include/asm/arch-ls102xa/clock.h new file +23 -0
new file mode 100644
index 0000000..fd36bb0
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
+#define __ASM_ARCH_LS102XA_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
arch/arm/include/asm/arch-ls102xa/config.h new file +71 -0

71 lines not on this page · raw message

arch/arm/include/asm/arch-ls102xa/fsl_serdes.h new file +33 -0
new file mode 100644
index 0000000..3a92f5a
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	SATA1,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+
+#endif /* __FSL_SERDES_H */
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h new file +461 -0

461 lines not on this page · raw message

arch/arm/include/asm/arch-ls102xa/imx-regs.h new file +53 -0

53 lines not on this page · raw message

arch/arm/include/asm/config.h +4 -0
index 5f2a5f4..2f1e0a1 100644
@@ -23,4 +23,8 @@
 #include <asm/arch-fsl-lsch3/config.h>
 #endif
 
+#ifdef CONFIG_LS102xA
+#include <asm/arch/config.h>
+#endif
+
 #endif
arch/arm/include/asm/io.h +7 -1
index 6d18eb3..e60ed73 100644
@@ -376,7 +376,12 @@ out:
 	return retval;
 }
 
-#elif !defined(readb)
+#else
+#define memset_io(a, b, c)		memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)		memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)		memcpy((void *)(a), (b), (c))
+
+#if !defined(readb)
 
 #define readb(addr)			(__readwrite_bug("readb"),0)
 #define readw(addr)			(__readwrite_bug("readw"),0)

@@ -389,6 +394,7 @@ out:
 
 #define check_signature(io,sig,len)	(0)
 
+#endif
 #endif	/* __mem_pci */
 
 /*
drivers/watchdog/Makefile +1 -1
index 0276a10..1dc0f5a 100644
@@ -7,7 +7,7 @@
 
 obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
 obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
 obj-y += imx_watchdog.o
 endif
 obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
Signature · 1 line
1.8.0
#2 lore raw

PATCH v5 1/16 arm: ls102xa: Add Freescale LS102xA SoC support

Hi,

Quoted 25 lines · Alison Wang

From: Wang Huan <[email protected]>

The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability.

Signed-off-by Alison Wang <[email protected]>
Signed-off-by Jason Jin <[email protected]>
Signed-off-by Jingchang Lu <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: Fix checkpatch errors.
v2: Add serdes support.
Update DDR frequency and data rate information. Fix overflow condition error for the timer.

[...]

arch/arm/cpu/armv7/ls102xa/timer.c line 65

Quoted 10 lines
arch/arm/cpu/armv7/ls102xa/timer.c new file +10 -0
+int timer_init(void)
+{
+       struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+       unsigned long ctrl, val, freq;
+
+       /* Enable System Counter */
+       writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
+
+       freq = GENERIC_TIMER_CLK;
+       asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));

Is CNTFRQ initialised for both CPUs?

If the CPUs are booted at PL1 rather than PL2, is CNTVOFF initialised to the same value on both CPUs?

Thanks,
Mark.

#3 lore raw

PATCH v5 1/16 arm: ls102xa: Add Freescale LS102xA SoC support

Hi, Mark,

arch/arm/cpu/armv7/ls102xa/timer.c line 65

Quoted 10 lines · Alison Wang
arch/arm/cpu/armv7/ls102xa/timer.c new file +10 -0
+int timer_init(void) 
+{ 
+       struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; 
+       unsigned long ctrl, val, freq; 
+ 
+       /* Enable System Counter */ 
+       writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); 
+ 
+       freq = GENERIC_TIMER_CLK; 
+       asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));

Is CNTFRQ initialised for both CPUs?

[Alison Wang] No, only one CPU is booted now.

If the CPUs are booted at PL1 rather than PL2, is CNTVOFF initialised to the same value on both CPUs?

[Alison Wang] CNTVOFF is not initialized in the current secure mode. When we add virtualization support and switch to non-secure mode, we will initialize CNTVOFF to zero on both CPUs.

Thanks.
Alison

--
View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v5-0-16-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp186978p187075.html
Sent from the U-Boot mailing list archive at Nabble.com.

#4 lore raw

PATCH v5 1/16 arm: ls102xa: Add Freescale LS102xA SoC support

Quoted 17 lines · AlisonWang

Hi, Mark,

arch/arm/cpu/armv7/ls102xa/timer.c line 65

Quoted 10 lines · Alison Wang
arch/arm/cpu/armv7/ls102xa/timer.c new file +10 -0
+int timer_init(void) 
+{ 
+       struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; 
+       unsigned long ctrl, val, freq; 
+ 
+       /* Enable System Counter */ 
+       writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); 
+ 
+       freq = GENERIC_TIMER_CLK; 
+       asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));

Is CNTFRQ initialised for both CPUs?

Quoted 1 line

[Alison Wang] No, only one CPU is booted now.

Ah, ok. I missed that.

Quoted 6 lines

If the CPUs are booted at PL1 rather than PL2, is CNTVOFF initialised to the same value on both CPUs?

[Alison Wang] CNTVOFF is not initialized in the current secure mode. When we add virtualization support and switch to non-secure mode, we will initialize CNTVOFF to zero on both CPUs.

Ok. So long as CNTFRQ is also initialised that sounds fine.

Thanks,
Mark.

author
#5 lore raw

PATCH v5 2/16 ls102xa: i2c: Add i2c support for LS102xA

In reply to Alison Wang

The existing i.MX's I2C driver mxc_i2c.c is compatible with the controller of LS102xA. As I2C's registers are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to use 8-bit driver.

This patch is to add I2C 1,2,3 support for LS102xA.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: Add detailed commit messages.
v4: Add commit messages.
v3: Add I2C 3 support.
v2: No change.

 drivers/i2c/mxc_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/i2c/mxc_i2c.c +2 -2
index c14797c..83a9ffa 100644
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
 	(void *)IMX_I2C2_BASE
 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||	\
-	defined(CONFIG_MX6)
+	defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
 	(void *)I2C1_BASE_ADDR,
 	(void *)I2C2_BASE_ADDR,
 	(void *)I2C3_BASE_ADDR

@@ -545,7 +545,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
-	defined(CONFIG_MX6)
+	defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_read, mxc_i2c_write,
 			 mxc_i2c_set_bus_speed,
Signature · 1 line
1.8.0
author
#6 lore raw

PATCH v5 3/16 net: Merge asm/fsl_enet.h into fsl_mdio.h

In reply to Alison Wang

From: Claudiu Manoil <[email protected]>

fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead.

Signed-off-by Claudiu Manoil <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: No change.
v2: No change.

 arch/powerpc/include/asm/fsl_enet.h       | 24 ------------------------
 board/freescale/mpc8360emds/mpc8360emds.c |  2 +-
 board/freescale/mpc837xemds/mpc837xemds.c |  1 -
 drivers/net/fm/dtsec.c                    |  1 -
 drivers/net/fm/fm.h                       |  2 +-
 drivers/net/fm/init.c                     |  1 +
 drivers/net/fm/memac.c                    |  1 -
 drivers/net/fm/tgec.c                     |  1 -
 drivers/net/fsl_mdio.c                    |  1 -
 drivers/qe/uec.h                          |  1 -
 include/fm_eth.h                          |  2 +-
 include/fsl_mdio.h                        | 13 ++++++++++++-
 include/tsec.h                            |  2 +-
 13 files changed, 17 insertions(+), 35 deletions(-)
 delete mode 100644 arch/powerpc/include/asm/fsl_enet.h
arch/powerpc/include/asm/fsl_enet.h deleted +0 -24
deleted file mode 100644
index 96146b6..0000000
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include <phy.h>
-
-struct tsec_mii_mng {
-	u32 miimcfg;		/* MII management configuration reg */
-	u32 miimcom;		/* MII management command reg */
-	u32 miimadd;		/* MII management address reg */
-	u32 miimcon;		/* MII management control reg */
-	u32 miimstat;		/* MII management status reg  */
-	u32 miimind;		/* MII management indication reg */
-	u32 ifstat;		/* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
board/freescale/mpc8360emds/mpc8360emds.c +1 -1
index ac96163..5ff9dff 100644
@@ -11,13 +11,13 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <phy.h>
+#include <fsl_mdio.h>
 #if defined(CONFIG_PCI)
 #include <pci.h>
 #endif
 #include <spd_sdram.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/mmu.h>
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
board/freescale/mpc837xemds/mpc837xemds.c +0 -1
index 0a3c972..c749e55 100644
@@ -10,7 +10,6 @@
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/fsl_mpc83xx_serdes.h>
-#include <asm/fsl_enet.h>
 #include <spd_sdram.h>
 #include <tsec.h>
 #include <libfdt.h>
drivers/net/fm/dtsec.c +0 -1
index 78bbd43..8d3dc0e 100644
@@ -7,7 +7,6 @@
 #include <common.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_dtsec.h>
 #include <fsl_mdio.h>
 #include <phy.h>
drivers/net/fm/fm.h +1 -1
index 316e06e..a9691c6 100644
@@ -8,8 +8,8 @@
 #define __FM_H__
 
 #include <common.h>
+#include <phy.h>
 #include <fm_eth.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_fman.h>
 
 /* Port ID */
drivers/net/fm/init.c +1 -0
index ff04695..6cf21c6 100644
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
+#include <fsl_mdio.h>
 
 #include "fm.h"
drivers/net/fm/memac.c +0 -1
index 592a67f..9499290 100644
@@ -12,7 +12,6 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_memac.h>
 
 #include "fm.h"
drivers/net/fm/tgec.c +0 -1
index f450f80..5017123 100644
@@ -12,7 +12,6 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_tgec.h>
 
 #include "fm.h"
drivers/net/fsl_mdio.c +0 -1
index 1d88e65..8d09f5d 100644
@@ -11,7 +11,6 @@
 #include <fsl_mdio.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/fsl_enet.h>
 
 void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 		int dev_addr, int regnum, int value)
drivers/qe/uec.h +0 -1
index 48a1634..6b559f7 100644
@@ -13,7 +13,6 @@
 #include "qe.h"
 #include "uccf.h"
 #include <phy.h>
-#include <asm/fsl_enet.h>
 
 #define MAX_TX_THREADS				8
 #define MAX_RX_THREADS				8
include/fm_eth.h +1 -1
index 98edfcf..e46a684 100644
@@ -8,8 +8,8 @@
 #define __FM_ETH_H__
 
 #include <common.h>
+#include <phy.h>
 #include <asm/types.h>
-#include <asm/fsl_enet.h>
 
 enum fm_port {
 	FM1_DTSEC1,
include/fsl_mdio.h +12 -1
index b58713d..a531edf 100644
@@ -10,7 +10,18 @@
 
 #include <net.h>
 #include <miiphy.h>
-#include <asm/fsl_enet.h>
+
+struct tsec_mii_mng {
+	u32 miimcfg;		/* MII management configuration reg */
+	u32 miimcom;		/* MII management command reg */
+	u32 miimadd;		/* MII management address reg */
+	u32 miimcon;		/* MII management control reg */
+	u32 miimstat;		/* MII management status reg  */
+	u32 miimind;		/* MII management indication reg */
+	u32 ifstat;		/* Interface Status Register */
+} __packed;
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
 
 /* PHY register offsets */
 #define PHY_EXT_PAGE_ACCESS	0x1f
include/tsec.h +1 -1
index 1046426..2054715 100644
@@ -20,7 +20,7 @@
 #include <net.h>
 #include <config.h>
 #include <phy.h>
-#include <asm/fsl_enet.h>
+#include <fsl_mdio.h>
 
 #define TSEC_SIZE 		0x01000
 #define TSEC_MDIO_OFFSET	0x01000
Signature · 1 line
1.8.0
author
#7 lore raw

PATCH v5 4/16 net: mdio: Use mb() to be compatible for both ARM and PowerPC

In reply to Alison Wang

Use mb() instead of sync assembly instruction to be compatible for both ARM and PowerPC.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: Use mb() to be compatible for both ARM and PowerPC.

     Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.

v2: Add private mdio read and write support.

 drivers/net/fsl_mdio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/net/fsl_mdio.c +3 -3
index 8d09f5d..69ffd63 100644
@@ -19,7 +19,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 
 	out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
 	out_be32(&phyregs->miimcon, value);
-	asm("sync");
+	mb();
 
 	while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
 		;

@@ -37,11 +37,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 
 	/* Clear the command register, and wait */
 	out_be32(&phyregs->miimcom, 0);
-	asm("sync");
+	mb();
 
 	/* Initiate a read command, and wait */
 	out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
-	asm("sync");
+	mb();
 
 	/* Wait for the the indication that the read is done */
 	while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
Signature · 1 line
1.8.0
author
#8 lore raw

PATCH v5 5/16 ls102xa: etsec: Add etsec support for LS102xA

In reply to Alison Wang

For LS102xA, RxBDs and TxBDs are interpreted with little-endian bytes ordering. The offset for each of eTSECs and MDIOs is 256K bytes.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: No change.
v2: Add private mdio read and write support.

 drivers/net/tsec.c | 7 +++++++
 include/tsec.h     | 7 ++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)
drivers/net/tsec.c +7 -0
index e9138f0..a220221 100644
@@ -20,6 +20,7 @@
 #include <fsl_mdio.h>
 #include <asm/errno.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 
 	do {
 		uint16_t status;

@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 }
 
 /* This returns the status bits of the device.	The return value
include/tsec.h +6 -1
index 2054715..5b74f67 100644
@@ -20,10 +20,14 @@
 #include <net.h>
 #include <config.h>
 #include <phy.h>
-#include <fsl_mdio.h>
 
+#ifdef CONFIG_LS102xA
+#define TSEC_SIZE		0x40000
+#define TSEC_MDIO_OFFSET	0x40000
+#else
 #define TSEC_SIZE 		0x01000
 #define TSEC_MDIO_OFFSET	0x01000
+#endif
 
 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
 

@@ -128,6 +132,7 @@
 #define DMACTRL_INIT_SETTINGS	0x000000c3
 #define DMACTRL_GRS		0x00000010
 #define DMACTRL_GTS		0x00000008
+#define DMACTRL_LE		0x00008000
 
 #define TSTAT_CLEAR_THALT	0x80000000
 #define RSTAT_CLEAR_RHALT	0x00800000
Signature · 1 line
1.8.0
author
#9 lore raw

PATCH v5 6/16 ls102xa: esdhc: Add esdhc support for LS102xA

In reply to Alison Wang

For LS102xA, the platform is little endian, while esdhc IP is big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers' reading/writing in big or little endian format.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: Add commit messages.
v2: No change.

 drivers/mmc/fsl_esdhc.c |  4 ++--
 include/fsl_esdhc.h     | 14 +++++++++++++-
 2 files changed, 15 insertions(+), 3 deletions(-)
drivers/mmc/fsl_esdhc.c +2 -2
index 5541613..aec459f 100644
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102xA)
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 		xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif

@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 
 	voltage_caps = 0;
-	caps = regs->hostcapblt;
+	caps = esdhc_read32(&regs->hostcapblt);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
include/fsl_esdhc.h +13 -1
index 9814964..c1b6648 100644
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
 };
 
 /* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32            in_be32
+#define esdhc_write32           out_be32
+#define esdhc_clrsetbits32      clrsetbits_be32
+#define esdhc_clrbits32         clrbits_be32
+#define esdhc_setbits32         setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
 #define esdhc_read32		in_le32
 #define esdhc_write32		out_le32
 #define esdhc_clrsetbits32	clrsetbits_le32
Signature · 1 line
1.8.0
author
#10 lore raw

PATCH v5 7/16 driver/ddr/freescale: Add support of accumulate ECC

In reply to Alison Wang

From: York Sun <[email protected]>

If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated.

Signed-off-by York Sun <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: No change.
v2: No change.

 drivers/ddr/fsl/ctrl_regs.c | 5 +++++
 1 file changed, 5 insertions(+)
drivers/ddr/fsl/ctrl_regs.c +5 -0
index 04e4178..5e0ee77 100644
@@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int x32_en = 0;	/* x32 enable */
 	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
 	unsigned int hse;		/* Global half strength override */
+	unsigned int acc_ecc_en = 0;	/* Accumulated ECC enable */
 	unsigned int mem_halt = 0;	/* memory controller halt */
 	unsigned int bi = 0;		/* Bypass initialization */
 

@@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	ba_intlv_ctl = popts->ba_intlv_ctl;
 	hse = popts->half_strength_driver_enable;
 
+	/* set when ddr bus width < 64 */
+	acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
+
 	ddr->ddr_sdram_cfg = (0
 			| ((mem_en & 0x1) << 31)
 			| ((sren & 0x1) << 30)

@@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			| ((x32_en & 0x1) << 5)
 			| ((pchb8 & 0x1) << 4)
 			| ((hse & 0x1) << 3)
+			| ((acc_ecc_en & 0x1) << 2)
 			| ((mem_halt & 0x1) << 1)
 			| ((bi & 0x1) << 0)
 			);
Signature · 1 line
1.8.0
author
#11 lore raw

PATCH v5 8/16 driver/ddr/freescale: Fix DDR3 driver for ARM

In reply to Alison Wang

From: York Sun <[email protected]>

Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by York Sun <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: No change.
v2: No change.

 drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/ddr/fsl/arm_ddr_gen3.c +1 -1
index d4ed9ae..59f2fd6 100644
@@ -194,7 +194,7 @@ step2:
 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 	 * Let's wait for 800ms
 	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 		(get_ddr_freq(0) >> 20)) << 1;
Signature · 1 line
1.8.0
author
#12 lore raw

PATCH v5 9/16 driver/ddr/fsl: Add support of overriding chip select write leveling

In reply to Alison Wang

From: York Sun <[email protected]>

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose.

Signed-off-by York Sun <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: No change.
v2: No change.

 drivers/ddr/fsl/ctrl_regs.c   | 3 +++
 drivers/ddr/fsl/interactive.c | 2 ++
 include/fsl_ddr_sdram.h       | 2 ++
 3 files changed, 7 insertions(+)
drivers/ddr/fsl/ctrl_regs.c +3 -0
index 5e0ee77..d9cac22 100644
@@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	if (ip_rev > 0x40400)
 		unq_mrs_en = 1;
 
+	if (ip_rev > 0x40700)
+		ddr->debug[18] = popts->cswl_override;
+
 	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
 	set_ddr_sdram_mode(ddr, popts, common_dimm,
 				cas_latency, additive_latency, unq_mrs_en);
drivers/ddr/fsl/interactive.c +2 -0
index 7fb4187..6aa16b2 100644
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(wrlvl_override),
 		CTRL_OPTIONS(wrlvl_sample),
 		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS(cswl_override),
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),

@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(wrlvl_override),
 		CTRL_OPTIONS(wrlvl_sample),
 		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS_HEX(cswl_override),
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),
include/fsl_ddr_sdram.h +2 -0
index e8a2db9..987119b 100644
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
 #define DDR_DATA_BUS_WIDTH_64 0
 #define DDR_DATA_BUS_WIDTH_32 1
 #define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0	0x04000001
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller

@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
 	unsigned int cpo_override;
 	unsigned int write_data_delay;		/* DQS adjust */
 
+	unsigned int cswl_override;
 	unsigned int wrlvl_override;
 	unsigned int wrlvl_sample;		/* Write leveling */
 	unsigned int wrlvl_start;
Signature · 1 line
1.8.0
author
#13 lore raw

PATCH v5 10/16 arm: ls102xa: Add basic support for LS1021AQDS board

In reply to Alison Wang

From: Wang Huan <[email protected]>

LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console

For the detail board information, please refer to README.

Signed-off-by Alison Wang <[email protected]>
Signed-off-by Jason Jin <[email protected]>
Signed-off-by York Sun <[email protected]>
Signed-off-by Yuan Yao <[email protected]>
Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Change log:
v5: Change eth.c and handle the board muxing between the
RGMII/SGMII phys.
v4: Add more commit messages.
v3: Fix checkpatch error.
Update to Kconfig.
v2: Remove ethaddr/ipaddr setting.
Add board maintainer.
Add serdes and multiple ethernet controllers support.

 arch/arm/Kconfig                              |   4 +
 board/freescale/ls1021aqds/Kconfig            |  23 ++
 board/freescale/ls1021aqds/MAINTAINERS        |   6 +
 board/freescale/ls1021aqds/Makefile           |   9 +
 board/freescale/ls1021aqds/README             | 112 +++++++
 board/freescale/ls1021aqds/ddr.c              | 166 ++++++++++
 board/freescale/ls1021aqds/ddr.h              |  64 ++++
 board/freescale/ls1021aqds/eth.c              | 186 +++++++++++
 board/freescale/ls1021aqds/ls1021aqds.c       | 248 +++++++++++++++
 board/freescale/ls1021aqds/ls1021aqds_qixis.h |  35 +++
 configs/ls1021aqds_nor_defconfig              |   2 +
 include/configs/ls1021aqds.h                  | 424 ++++++++++++++++++++++++++
 12 files changed, 1279 insertions(+)
 create mode 100644 board/freescale/ls1021aqds/Kconfig
 create mode 100644 board/freescale/ls1021aqds/MAINTAINERS
 create mode 100644 board/freescale/ls1021aqds/Makefile
 create mode 100644 board/freescale/ls1021aqds/README
 create mode 100644 board/freescale/ls1021aqds/ddr.c
 create mode 100644 board/freescale/ls1021aqds/ddr.h
 create mode 100644 board/freescale/ls1021aqds/eth.c
 create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c
 create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h
 create mode 100644 configs/ls1021aqds_nor_defconfig
 create mode 100644 include/configs/ls1021aqds.h
arch/arm/Kconfig +4 -0
index e385eda..62b3cc8 100644
@@ -731,6 +731,9 @@ config TARGET_LS2085A_EMU
 config TARGET_LS2085A_SIMU
 	bool "Support ls2085a_simu"
 
+config TARGET_LS1021AQDS
+	bool "Support ls1021aqds_nor"
+
 config TARGET_BALLOON3
 	bool "Support balloon3"
 

@@ -865,6 +868,7 @@ source "board/eukrea/cpu9260/Kconfig"
 source "board/eukrea/cpuat91/Kconfig"
 source "board/faraday/a320evb/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
+source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
board/freescale/ls1021aqds/Kconfig new file +23 -0
new file mode 100644
index 0000000..c28bd2b
@@ -0,0 +1,23 @@
+if TARGET_LS1021AQDS
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "ls1021aqds"
+
+config SYS_VENDOR
+	string
+	default "freescale"
+
+config SYS_SOC
+	string
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	string
+	default "ls1021aqds"
+
+endif
board/freescale/ls1021aqds/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..021d82b
@@ -0,0 +1,6 @@
+LS1021AQDS BOARD
+M:	Alison Wang <[email protected]>
+S:	Maintained
+F:	board/freescale/ls1021aqds/
+F:	include/configs/ls1021aqds.h
+F:	configs/ls1021aqds_nor_defconfig
board/freescale/ls1021aqds/Makefile new file +9 -0
new file mode 100644
index 0000000..3b6903c
@@ -0,0 +1,9 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1021aqds.o
+obj-y += ddr.o
+obj-y += eth.o
board/freescale/ls1021aqds/README new file +112 -0

112 lines not on this page · raw message

board/freescale/ls1021aqds/ddr.c new file +166 -0

166 lines not on this page · raw message

board/freescale/ls1021aqds/ddr.h new file +64 -0

64 lines not on this page · raw message

board/freescale/ls1021aqds/eth.c new file +186 -0

186 lines not on this page · raw message

board/freescale/ls1021aqds/ls1021aqds.c new file +248 -0

248 lines not on this page · raw message

board/freescale/ls1021aqds/ls1021aqds_qixis.h new file +35 -0
new file mode 100644
index 0000000..09b3be2
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1021AQDS_QIXIS_H__
+#define __LS1021AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1021AQDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+#define QIXIS_SRDS1CLK_100		0x0
+
+#endif
configs/ls1021aqds_nor_defconfig new file +2 -0
new file mode 100644
index 0000000..9e42d61
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
include/configs/ls1021aqds.h new file +424 -0

424 lines not on this page · raw message

Signature · 1 line
1.8.0
author
#14 lore raw

PATCH v5 11/16 arm: ls102xa: Add basic support for LS1021ATWR board

In reply to Alison Wang

From: Wang Huan <[email protected]>

LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console

For the detail board information, please refer to README.

Signed-off-by Chen Lu <[email protected]>
Signed-off-by Yuan Yao <[email protected]>
Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: No change.
v4: Add more commit messages.
v3: Fix checkpatch error.
Update to Kconfig.
v2: New file.

 arch/arm/Kconfig                        |   4 +
 board/freescale/ls1021atwr/Kconfig      |  23 ++
 board/freescale/ls1021atwr/MAINTAINERS  |   6 +
 board/freescale/ls1021atwr/Makefile     |   7 +
 board/freescale/ls1021atwr/README       | 109 +++++++
 board/freescale/ls1021atwr/ls1021atwr.c | 494 ++++++++++++++++++++++++++++++++
 configs/ls1021atwr_nor_defconfig        |   2 +
 include/configs/ls1021atwr.h            | 284 ++++++++++++++++++
 8 files changed, 929 insertions(+)
 create mode 100644 board/freescale/ls1021atwr/Kconfig
 create mode 100644 board/freescale/ls1021atwr/MAINTAINERS
 create mode 100644 board/freescale/ls1021atwr/Makefile
 create mode 100644 board/freescale/ls1021atwr/README
 create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c
 create mode 100644 configs/ls1021atwr_nor_defconfig
 create mode 100644 include/configs/ls1021atwr.h
arch/arm/Kconfig +4 -0
index 62b3cc8..d207db7 100644
@@ -734,6 +734,9 @@ config TARGET_LS2085A_SIMU
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds_nor"
 
+config TARGET_LS1021ATWR
+	bool "Support ls1021atwr_nor"
+
 config TARGET_BALLOON3
 	bool "Support balloon3"
 

@@ -869,6 +872,7 @@ source "board/eukrea/cpuat91/Kconfig"
 source "board/faraday/a320evb/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
+source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
board/freescale/ls1021atwr/Kconfig new file +23 -0
new file mode 100644
index 0000000..057808d
@@ -0,0 +1,23 @@
+if TARGET_LS1021ATWR
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "ls1021atwr"
+
+config SYS_VENDOR
+	string
+	default "freescale"
+
+config SYS_SOC
+	string
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	string
+	default "ls1021atwr"
+
+endif
board/freescale/ls1021atwr/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..4e5bc15
@@ -0,0 +1,6 @@
+LS1021ATWR BOARD
+M:	Alison Wang <[email protected]>
+S:	Maintained
+F:	board/freescale/ls1021atwr/
+F:	include/configs/ls1021atwr.h
+F:	configs/ls1021atwr_nor_defconfig
board/freescale/ls1021atwr/Makefile new file +7 -0
new file mode 100644
index 0000000..b5df668
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1021atwr.o
board/freescale/ls1021atwr/README new file +109 -0

109 lines not on this page · raw message

board/freescale/ls1021atwr/ls1021atwr.c new file +494 -0

494 lines not on this page · raw message

configs/ls1021atwr_nor_defconfig new file +2 -0
new file mode 100644
index 0000000..5f465d3
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
include/configs/ls1021atwr.h new file +284 -0

284 lines not on this page · raw message

Signature · 1 line
1.8.0
author
#15 lore raw

PATCH v5 12/16 net: tsec: Remove tx snooping support from LS1

In reply to Alison Wang

From: Claudiu Manoil <[email protected]>

Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a workaround for LS1. It has been observed that currently the Tx stops functioning after a fair amount of Tx traffic with these settings on. These bits are sticky and once set they cannot be reset from Linux, for instance.

Signed-off-by Claudiu Manoil <[email protected]>

---
Change log:
v5: No change.
v4: No change.
v3: New file.

 include/tsec.h | 4 ++++
 1 file changed, 4 insertions(+)
include/tsec.h +4 -0
index 5b74f67..1f0c233 100644
@@ -129,7 +129,11 @@
 
 #define MINFLR_INIT_SETTINGS	0x00000040
 
+#ifdef CONFIG_LS102xA
+#define DMACTRL_INIT_SETTINGS	0x00000003
+#else
 #define DMACTRL_INIT_SETTINGS	0x000000c3
+#endif
 #define DMACTRL_GRS		0x00000010
 #define DMACTRL_GTS		0x00000008
 #define DMACTRL_LE		0x00008000
Signature · 1 line
1.8.4
author
#16 lore raw

PATCH v5 13/16 serial: lpuart: add 32-bit registers lpuart support

In reply to Alison Wang

From: Jingchang Lu <[email protected]>

On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers are 32-bit. This patch adds the support for 32-bit registers on LS102xA.

Signed-off-by Jingchang Lu <[email protected]>
Signed-off-by Yuan Yao <[email protected]>

---
Change log:
v5: No change.
v4: Add commit messages.
v3: New file.

 drivers/serial/serial_lpuart.c | 122 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)
drivers/serial/serial_lpuart.c +122 -0
index da5f9a2..6e639b7 100644
@@ -17,10 +17,34 @@
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
 
+#define STAT_LBKDIF	(1 << 31)
+#define STAT_RXEDGIF	(1 << 30)
+#define STAT_TDRE	(1 << 23)
+#define STAT_RDRF	(1 << 21)
+#define STAT_IDLE	(1 << 20)
+#define STAT_OR		(1 << 19)
+#define STAT_NF		(1 << 18)
+#define STAT_FE		(1 << 17)
+#define STAT_PF		(1 << 16)
+#define STAT_MA1F	(1 << 15)
+#define STAT_MA2F	(1 << 14)
+#define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
+			STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
+
+#define CTRL_TE		(1 << 19)
+#define CTRL_RE		(1 << 18)
+
+#define FIFO_TXFE		0x80
+#define FIFO_RXFE		0x40
+
+#define WATER_TXWATER_OFF	1
+#define WATER_RXWATER_OFF	16
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
 
+#ifndef CONFIG_LPUART_32B_REG
 static void lpuart_serial_setbrg(void)
 {
 	u32 clk = mxc_get_clock(MXC_UART_CLK);

@@ -107,13 +131,111 @@ static struct serial_device lpuart_serial_drv = {
 	.getc = lpuart_serial_getc,
 	.tstc = lpuart_serial_tstc,
 };
+#else
+static void lpuart32_serial_setbrg(void)
+{
+	u32 clk = CONFIG_SYS_CLK_FREQ;
+	u32 sbr;
+
+	if (!gd->baudrate)
+		gd->baudrate = CONFIG_BAUDRATE;
+
+	sbr = (clk / (16 * gd->baudrate));
+	/* place adjustment later - n/32 BRFA */
+
+	out_be32(&base->baud, sbr);
+}
+
+static int lpuart32_serial_getc(void)
+{
+	u32 stat;
+
+	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
+		out_be32(&base->stat, STAT_FLAGS);
+		WATCHDOG_RESET();
+	}
+
+	return in_be32(&base->data) & 0x3ff;
+}
+
+static void lpuart32_serial_putc(const char c)
+{
+	if (c == '\n')
+		serial_putc('\r');
+
+	while (!(in_be32(&base->stat) & STAT_TDRE))
+		WATCHDOG_RESET();
+
+	out_be32(&base->data, c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart32_serial_tstc(void)
+{
+	if ((in_be32(&base->water) >> 24) == 0)
+		return 0;
+
+	return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart32_serial_init(void)
+{
+	u8 ctrl;
+
+	ctrl = in_be32(&base->ctrl);
+	ctrl &= ~CTRL_RE;
+	ctrl &= ~CTRL_TE;
+	out_be32(&base->ctrl, ctrl);
+
+	out_be32(&base->modir, 0);
+	out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+	out_be32(&base->match, 0);
+	/* provide data bits, parity, stop bit, etc */
+
+	serial_setbrg();
+
+	out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
+
+	return 0;
+}
+
+static struct serial_device lpuart32_serial_drv = {
+	.name = "lpuart32_serial",
+	.start = lpuart32_serial_init,
+	.stop = NULL,
+	.setbrg = lpuart32_serial_setbrg,
+	.putc = lpuart32_serial_putc,
+	.puts = default_serial_puts,
+	.getc = lpuart32_serial_getc,
+	.tstc = lpuart32_serial_tstc,
+};
+#endif
+void lpuart32_serial_initialize(void)
+{
+	serial_register(&lpuart32_serial_drv);
+}
 
 void lpuart_serial_initialize(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+	serial_register(&lpuart32_serial_drv);
+#else
 	serial_register(&lpuart_serial_drv);
+#endif
 }
 
 __weak struct serial_device *default_serial_console(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+	return &lpuart32_serial_drv;
+#else
 	return &lpuart_serial_drv;
+#endif
 }
Signature · 1 line
1.8.0
#17 lore raw

PATCH v5 13/16 serial: lpuart: add 32-bit registers lpuart support

Quoted 140 lines · Alison Wang

From: Jingchang Lu <[email protected]>

On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers are 32-bit. This patch adds the support for 32-bit registers on LS102xA.

Signed-off-by Jingchang Lu <[email protected]>
Signed-off-by Yuan Yao <[email protected]>

---
Change log:
v5: No change.
v4: Add commit messages.
v3: New file.

 drivers/serial/serial_lpuart.c | 122 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)
drivers/serial/serial_lpuart.c +104 -0
index da5f9a2..6e639b7 100644
@@ -17,10 +17,34 @@
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
 
+#define STAT_LBKDIF	(1 << 31)
+#define STAT_RXEDGIF	(1 << 30)
+#define STAT_TDRE	(1 << 23)
+#define STAT_RDRF	(1 << 21)
+#define STAT_IDLE	(1 << 20)
+#define STAT_OR		(1 << 19)
+#define STAT_NF		(1 << 18)
+#define STAT_FE		(1 << 17)
+#define STAT_PF		(1 << 16)
+#define STAT_MA1F	(1 << 15)
+#define STAT_MA2F	(1 << 14)
+#define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
+			STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
+
+#define CTRL_TE		(1 << 19)
+#define CTRL_RE		(1 << 18)
+
+#define FIFO_TXFE		0x80
+#define FIFO_RXFE		0x40
+
+#define WATER_TXWATER_OFF	1
+#define WATER_RXWATER_OFF	16
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
 
+#ifndef CONFIG_LPUART_32B_REG
 static void lpuart_serial_setbrg(void)
 {
 	u32 clk = mxc_get_clock(MXC_UART_CLK);

@@ -107,13 +131,111 @@ static struct serial_device lpuart_serial_drv = {
 	.getc = lpuart_serial_getc,
 	.tstc = lpuart_serial_tstc,
 };
+#else
+static void lpuart32_serial_setbrg(void)
+{
+	u32 clk = CONFIG_SYS_CLK_FREQ;
+	u32 sbr;
+
+	if (!gd->baudrate)
+		gd->baudrate = CONFIG_BAUDRATE;
+
+	sbr = (clk / (16 * gd->baudrate));
+	/* place adjustment later - n/32 BRFA */
+
+	out_be32(&base->baud, sbr);
+}
+
+static int lpuart32_serial_getc(void)
+{
+	u32 stat;
+
+	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
+		out_be32(&base->stat, STAT_FLAGS);
+		WATCHDOG_RESET();
+	}
+
+	return in_be32(&base->data) & 0x3ff;
+}
+
+static void lpuart32_serial_putc(const char c)
+{
+	if (c == '\n')
+		serial_putc('\r');
+
+	while (!(in_be32(&base->stat) & STAT_TDRE))
+		WATCHDOG_RESET();
+
+	out_be32(&base->data, c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart32_serial_tstc(void)
+{
+	if ((in_be32(&base->water) >> 24) == 0)
+		return 0;
+
+	return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart32_serial_init(void)
+{
+	u8 ctrl;
+
+	ctrl = in_be32(&base->ctrl);
+	ctrl &= ~CTRL_RE;
+	ctrl &= ~CTRL_TE;
+	out_be32(&base->ctrl, ctrl);
+
+	out_be32(&base->modir, 0);
+	out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+	out_be32(&base->match, 0);
+	/* provide data bits, parity, stop bit, etc */
+
+	serial_setbrg();
+
+	out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
+
+	return 0;
+}
+
+static struct serial_device lpuart32_serial_drv = {
+	.name = "lpuart32_serial",
+	.start = lpuart32_serial_init,
+	.stop = NULL,
+	.setbrg = lpuart32_serial_setbrg,

drivers/serial/serial_lpuart.c static struct serial_device lpuart_serial_drv = { · line 223

Quoted 10 lines
drivers/serial/serial_lpuart.c +10 -0
+	.putc = lpuart32_serial_putc,
+	.puts = default_serial_puts,
+	.getc = lpuart32_serial_getc,
+	.tstc = lpuart32_serial_tstc,
+};
+#endif
+void lpuart32_serial_initialize(void)
+{
+	serial_register(&lpuart32_serial_drv);
+}

This breaks any board without CONFIG_LPUART_32B_REG defined, for example vf610twr. Please fix.

York

author
#18 lore raw

PATCH v5 14/16 video: dcu: Add DCU driver support

In reply to Alison Wang

From: Wang Huan <[email protected]>

This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: Change the patch order.
v4: No change.
v3: New file.

 arch/arm/include/asm/arch-ls102xa/config.h |   4 +
 drivers/video/Makefile                     |   1 +
 drivers/video/fsl_dcu_fb.c                 | 365 +++++++++++++++++++++++++++++
 include/fsl_dcu_fb.h                       |  16 ++
 4 files changed, 386 insertions(+)
 create mode 100644 drivers/video/fsl_dcu_fb.c
 create mode 100644 include/fsl_dcu_fb.h
arch/arm/include/asm/arch-ls102xa/config.h +4 -0
index ddc747f..dfc5668 100644
@@ -21,6 +21,7 @@
 #define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
 
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000

@@ -57,6 +58,9 @@
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_DCU_BE
+
+#define DCU_LAYER_MAX_NUM			16
 
 #define CONFIG_SYS_FSL_SRDS_1
drivers/video/Makefile +1 -0
index 945f35d..3dafef3 100644
@@ -15,6 +15,7 @@ obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
 				exynos_mipi_dsi_lowlevel.o
 obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
 obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
 obj-$(CONFIG_L5F31188) += l5f31188.o
 obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
drivers/video/fsl_dcu_fb.c new file +365 -0

365 lines not on this page · raw message

include/fsl_dcu_fb.h new file +16 -0
new file mode 100644
index 0000000..4263298
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <linux/fb.h>
+
+int fsl_dcu_init(unsigned int xres, unsigned int yres,
+		 unsigned int pixel_format);
+
+/* Prototypes for external board-specific functions */
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		      const char *port, struct fb_videomode *dcu_fb_videomode);
+unsigned int dcu_set_pixel_clock(unsigned int pixclock);
Signature · 1 line
1.8.0
author
#19 lore raw

PATCH v5 15/16 ls102xa: dcu: Add platform support for DCU on LS1021ATWR board

In reply to Alison Wang

From: Wang Huan <[email protected]>

This patch adds the TWR_LCD_RGB card/HDMI options and the common configuration for DCU on LS1021ATWR board.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: Change the patch order.
v4: Add commit messages.
v3: New file.

 board/freescale/ls1021atwr/Makefile     |  1 +
 board/freescale/ls1021atwr/dcu.c        | 47 +++++++++++++++++++++++++++++++++
 board/freescale/ls1021atwr/ls1021atwr.c |  6 +++++
 include/configs/ls1021atwr.h            | 18 +++++++++++++
 4 files changed, 72 insertions(+)
 create mode 100644 board/freescale/ls1021atwr/dcu.c
board/freescale/ls1021atwr/Makefile +1 -0
index b5df668..01296c0 100644
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1021atwr.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
board/freescale/ls1021atwr/dcu.c new file +47 -0

47 lines not on this page · raw message

board/freescale/ls1021atwr/ls1021atwr.c +6 -0
index 7fdcbcd..e4364dd 100644
@@ -264,6 +264,12 @@ int board_early_init_f(void)
 	init_early_memctl_regs();
 #endif
 
+#ifdef CONFIG_FSL_DCU_FB
+	out_be32(&scfg->scfgrevcr, 0xffffffff);
+	out_be32(&scfg->pixclkcr, 0x80000000);
+	out_be32(&scfg->scfgrevcr, 0x00000000);
+#endif
+
 	out_le32(&cci->ctrl_ord, 0x00000008);
 
 	return 0;
include/configs/ls1021atwr.h +18 -0
index f8cbe32..716143c 100644
@@ -177,6 +177,24 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_GENERIC_MMC
 
 /*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DCU_SII9022A
+#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
+#define CONFIG_SYS_I2C_DVI_ADDR		0x39
+#endif
+
+/*
  * eTSEC
  */
 #define CONFIG_TSEC_ENET
Signature · 1 line
1.8.0
#20 lore raw

PATCH v5 15/16 ls102xa: dcu: Add platform support for DCU on LS1021ATWR board

Quoted 36 lines · Alison Wang

From: Wang Huan <[email protected]>

This patch adds the TWR_LCD_RGB card/HDMI options and the common configuration for DCU on LS1021ATWR board.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: Change the patch order.
v4: Add commit messages.
v3: New file.

 board/freescale/ls1021atwr/Makefile     |  1 +
 board/freescale/ls1021atwr/dcu.c        | 47 +++++++++++++++++++++++++++++++++
 board/freescale/ls1021atwr/ls1021atwr.c |  6 +++++
 include/configs/ls1021atwr.h            | 18 +++++++++++++
 4 files changed, 72 insertions(+)
 create mode 100644 board/freescale/ls1021atwr/dcu.c
board/freescale/ls1021atwr/Makefile +1 -0
index b5df668..01296c0 100644
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1021atwr.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
board/freescale/ls1021atwr/dcu.c new file +2 -0
new file mode 100644
index 0000000..8fe4ccb
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.

board/freescale/ls1021atwr/dcu.c line 12

Quoted 10 lines
board/freescale/ls1021atwr/dcu.c new file +10 -0
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"

The order of this patch and 16/16 is wrong. This line fails until next patch is applied. Please reorder the patch to maintain git bisect workable.

York

author
#21 lore raw

PATCH v5 16/16 video: dcu: Add Sii9022A HDMI Transmitter support

In reply to Alison Wang

On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter is used. This patch adds the common setting for this chip.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v5: Change the patch order.
v4: Add commit messages.
v3: New file.

 board/freescale/common/Makefile       |   2 +
 board/freescale/common/dcu_sii9022a.c | 153 ++++++++++++++++++++++++++++++++++
 board/freescale/common/dcu_sii9022a.h |  13 +++
 3 files changed, 168 insertions(+)
 create mode 100644 board/freescale/common/dcu_sii9022a.c
 create mode 100644 board/freescale/common/dcu_sii9022a.h
board/freescale/common/Makefile +2 -0
index 22b57cc..808ddd0 100644
@@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL
 obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
 endif
 
+obj-$(CONFIG_FSL_DCU_SII9022A)    += dcu_sii9022a.o
+
 obj-$(CONFIG_MPC8541CDS)	+= cds_pci_ft.o
 obj-$(CONFIG_MPC8548CDS)	+= cds_pci_ft.o
 obj-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
board/freescale/common/dcu_sii9022a.c new file +153 -0

153 lines not on this page · raw message

board/freescale/common/dcu_sii9022a.h new file +13 -0
new file mode 100644
index 0000000..de76733
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DCU_HDMI_SII9022A__
+#define __DCU_HDMI_SII9022A__
+
+/* Programming of Silicon SII9022A connector HDMI Transmitter*/
+int dcu_set_dvi_encoder(struct fb_videomode *videomode);
+
+#endif
Signature · 1 line
1.8.0