PSCI v0.2 framework for ARMv8

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/include/asm/psci.h |   42 +++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 41 insertions(+), 1 deletions(-)

arch/arm/include/asm/psci.h +41 -1

index 704b4b0..68579cd 100644
@@ -2,6 +2,10 @@
  * Copyright (C) 2013 - ARM Ltd
  * Author: Marc Zyngier <[email protected]>
  *
+ * Copyright (C) 2014 - Freescale Semiconductor Ltd
+ * Author: Arnab Basu <[email protected]>
+ *	   updated file for PSCI v0.2
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.

@@ -18,7 +22,7 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
-/* PSCI interface */
+/* PSCI v0.1 interface */
 #define ARM_PSCI_FN_BASE		0x95c1ba5e
 #define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
 

@@ -27,9 +31,45 @@
 #define ARM_PSCI_FN_CPU_ON		ARM_PSCI_FN(2)
 #define ARM_PSCI_FN_MIGRATE		ARM_PSCI_FN(3)
 
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE		0x84000000
+#define PSCI_0_2_FN(n)			(PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT			0x40000000
+#define PSCI_0_2_FN64_BASE		\
+				(PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n)		(PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION	PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND		PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF		PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON		PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO	PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE		PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE	PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU	PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF		PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET	PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND		PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON			PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO		PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE			PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	PSCI_0_2_FN64(7)
+
+
+/*
+ * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
+ * INVALID_PARAMS, and DENIED defined below are applicable
+ * to PSCI v0.1.
+ */
 #define ARM_PSCI_RET_SUCCESS		0
 #define ARM_PSCI_RET_NI			(-1)
 #define ARM_PSCI_RET_INVAL		(-2)
 #define ARM_PSCI_RET_DENIED		(-3)
+#define PSCI_RET_ALREADY_ON		(-4)
+#define PSCI_RET_ON_PENDING		(-5)
+#define PSCI_RET_INTERNAL_FAILURE	(-6)
+#define PSCI_RET_NOT_PRESENT		(-7)
+#define PSCI_RET_DISABLED		(-8)
 
 #endif /* __ARM_PSCI_H__ */

Signature · 1 line

1.7.7.4

Hello Arnab,

Quoted 76 lines · Arnab Basu

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/include/asm/psci.h |   42 +++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 41 insertions(+), 1 deletions(-)

arch/arm/include/asm/psci.h +41 -1

index 704b4b0..68579cd 100644
@@ -2,6 +2,10 @@
  * Copyright (C) 2013 - ARM Ltd
  * Author: Marc Zyngier <[email protected]>
  *
+ * Copyright (C) 2014 - Freescale Semiconductor Ltd
+ * Author: Arnab Basu <[email protected]>
+ *	   updated file for PSCI v0.2
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.

@@ -18,7 +22,7 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
-/* PSCI interface */
+/* PSCI v0.1 interface */
 #define ARM_PSCI_FN_BASE		0x95c1ba5e
 #define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
 

@@ -27,9 +31,45 @@
 #define ARM_PSCI_FN_CPU_ON		ARM_PSCI_FN(2)
 #define ARM_PSCI_FN_MIGRATE		ARM_PSCI_FN(3)
 
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE		0x84000000
+#define PSCI_0_2_FN(n)			(PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT			0x40000000
+#define PSCI_0_2_FN64_BASE		\
+				(PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n)		(PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION	PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND		PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF		PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON		PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO	PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE		PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE	PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU	PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF		PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET	PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND		PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON			PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO		PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE			PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	PSCI_0_2_FN64(7)
+
+
+/*
+ * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
+ * INVALID_PARAMS, and DENIED defined below are applicable
+ * to PSCI v0.1.
+ */
 #define ARM_PSCI_RET_SUCCESS		0
 #define ARM_PSCI_RET_NI			(-1)
 #define ARM_PSCI_RET_INVAL		(-2)
 #define ARM_PSCI_RET_DENIED		(-3)
+#define PSCI_RET_ALREADY_ON		(-4)
+#define PSCI_RET_ON_PENDING		(-5)
+#define PSCI_RET_INTERNAL_FAILURE	(-6)
+#define PSCI_RET_NOT_PRESENT		(-7)
+#define PSCI_RET_DISABLED		(-8)
 

Quoted 3 lines

arch/arm/include/asm/psci.h +0 -0

 #endif /* __ARM_PSCI_H__ */

Signature · 1 line

1.7.7.4

Applied, with apologies for the delay. This patch will appear in 2015.01.

Amicalement,

Signature · 1 line

Albert.

Both ARMv7 and ARMv8 need to patch the device tree but the kind of patching done is different. This creates a function that can be defined by each architecture to handle the differences

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/cpu/armv7/virt-dt.c |    7 ++++++-
 arch/arm/lib/bootm-fdt.c     |   11 ++++++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/virt-dt.c +6 -1

index 0b0d6a7..3fbec39 100644
@@ -88,7 +88,7 @@ static int fdt_psci(void *fdt)
 	return 0;
 }
 
-int armv7_update_dt(void *fdt)
+static int armv7_update_dt(void *fdt)
 {
 #ifndef CONFIG_ARMV7_SECURE_BASE
 	/* secure code lives in RAM, keep it alive */

@@ -98,3 +98,8 @@ int armv7_update_dt(void *fdt)
 
 	return fdt_psci(fdt);
 }
+
+int cpu_update_dt(void *fdt)
+{
+	return armv7_update_dt(fdt);
+}

arch/arm/lib/bootm-fdt.c +8 -3

index d4f1578..daabc03 100644
@@ -21,6 +21,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+__weak int cpu_update_dt(void *fdt)
+{
+	return 0;
+}
+
 int arch_fixup_fdt(void *blob)
 {
 	bd_t *bd = gd->bd;

@@ -34,11 +39,11 @@ int arch_fixup_fdt(void *blob)
 	}
 
 	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+
 	if (ret)
 		return ret;
 
-	ret = armv7_update_dt(blob);
-#endif
+	ret = cpu_update_dt(blob);
+
 	return ret;
 }

Signature · 1 line

1.7.7.4

Hi Arnab,

Quoted 3 lines · Arnab Basu

Both ARMv7 and ARMv8 need to patch the device tree but the kind of patching done is different. This creates a function that can be defined by each architecture to handle the differences

I have no problem with the patch, but what is it that we need to do differently for ARMv7 and ARMv8?

Mark.

Hi Mark

Quoted 7 lines · Mark Rutland

Hi Arnab,

Quoted 3 lines · Arnab Basu

Both ARMv7 and ARMv8 need to patch the device tree but the kind of patching done is different. This creates a function that can be defined by each architecture to handle the differences

Quoted 3 lines

I have no problem with the patch, but what is it that we need to do differently for ARMv7 and ARMv8?

In ARMv7 there does not seem to be any code around to set "enable-method" to "spin-table". I guess it is assumed that DTs already come with this set.

For ARMv8 we would like to assume that "enable-method" is missing from the cpu node and will be set either to "spin-table" or "psci" by the boot loader.

So the difference is, for ARMv7 the "enable-method" is only modified in case of PSCI, whereas for ARMv8 it is always modified.

This creates the function cpu_update_dt for ARMv8 which currently patches the cpu node in the device table and sets enable-method to spin-table.

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc York Sun <[email protected]>

---

-----Original Message-----
From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
Sent: Monday, October 27, 2014 2:36 AM
To: Basu Arnab-B45036
Cc: marc.zyngier at arm.com; mark.rutland at arm.com; Sun York-R58495; Yoder Stuart-B08248; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 3/8] ARMv8/fsl-lsch3: Refactor spin-table code

Hello Arnab,

Quoted 4 lines · Arnab Basu

This creates the function cpu_update_dt for ARMv8 which currently patches the cpu node in the device table and sets enable-method to spin-table.

Quoted 4 lines

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc York Sun <[email protected]>

---

This patch fails to apply cleanly. Can you please rebase the series on top of current u-boot/master?

Amicalement,
--
Albert.

A separate linker section makes it possible to keep this code either in DDR or in some secure memory location provided specifically for the purpose.

So far no one is using this section.

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/config.mk            |    2 +-
 arch/arm/cpu/armv8/u-boot.lds |   30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletions(-)

arch/arm/config.mk +1 -1

index c339e6d..9272e9c 100644
@@ -111,7 +111,7 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
 endif

arch/arm/cpu/armv8/u-boot.lds +17 -0

index 4c12222..bd95fff 100644
@@ -8,6 +8,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <config.h>
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)

@@ -23,6 +25,34 @@ SECTIONS
 		*(.text*)
 	}
 
+#ifdef CONFIG_ARMV8_PSCI
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#endif
+
+	.__secure_start : {
+		. = ALIGN(0x1000);
+		*(.__secure_start)
+	}
+
+	.secure_text CONFIG_ARMV8_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)

Hi Arnab,

Quoted 63 lines · Arnab Basu

A separate linker section makes it possible to keep this code either in DDR or in some secure memory location provided specifically for the purpose.

So far no one is using this section.

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/config.mk            |    2 +-
 arch/arm/cpu/armv8/u-boot.lds |   30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletions(-)

arch/arm/config.mk +1 -1

index c339e6d..9272e9c 100644
@@ -111,7 +111,7 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
 endif

arch/arm/cpu/armv8/u-boot.lds +21 -0

index 4c12222..bd95fff 100644
@@ -8,6 +8,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <config.h>
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)

@@ -23,6 +25,34 @@ SECTIONS
 		*(.text*)
 	}
 
+#ifdef CONFIG_ARMV8_PSCI
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#endif
+
+	.__secure_start : {
+		. = ALIGN(0x1000);
+		*(.__secure_start)
+	}
+
+	.secure_text CONFIG_ARMV8_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	. = LOADADDR(.__secure_start) +
+		SIZEOF(.__secure_start) +

arch/arm/cpu/armv8/u-boot.lds SECTIONS · line 52

Quoted 6 lines

arch/arm/cpu/armv8/u-boot.lds +6 -0

+		SIZEOF(.secure_text);
+
+	__secure_end_lma = .;
+	.__secure_end : AT(__secure_end_lma) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */

Can you explain in more detail what issue this fixes?

Quoted 68 lines · Albert ARIBAUD

Hi Arnab,

Quoted 63 lines · Arnab Basu

A separate linker section makes it possible to keep this code either in DDR or in some secure memory location provided specifically for the purpose.

So far no one is using this section.

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/config.mk            |    2 +-
 arch/arm/cpu/armv8/u-boot.lds |   30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletions(-)

arch/arm/config.mk +1 -1

index c339e6d..9272e9c 100644
@@ -111,7 +111,7 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
 endif

arch/arm/cpu/armv8/u-boot.lds +21 -0

index 4c12222..bd95fff 100644
@@ -8,6 +8,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <config.h>
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)

@@ -23,6 +25,34 @@ SECTIONS
 		*(.text*)
 	}
 
+#ifdef CONFIG_ARMV8_PSCI
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#endif
+
+	.__secure_start : {
+		. = ALIGN(0x1000);
+		*(.__secure_start)
+	}
+
+	.secure_text CONFIG_ARMV8_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	. = LOADADDR(.__secure_start) +
+		SIZEOF(.__secure_start) +

Quoted 8 lines

arch/arm/cpu/armv8/u-boot.lds SECTIONS · line 52

Quoted 6 lines

arch/arm/cpu/armv8/u-boot.lds +6 -0

+		SIZEOF(.secure_text);
+
+	__secure_end_lma = .;
+	.__secure_end : AT(__secure_end_lma) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */

Can you explain in more detail what issue this fixes?

If you use AT to force a new load address (LMA), you must ensure that you actually output something at this address. Here, if *(.__secure_end) ends up being empty, whatever follows would be as if the AT never happened, ending up at the wrong LMA.

The workaround is to force the output of a dummy value in all cases, ensuring that the rest of the text is at a sensible LMA. This is an issue that has been in GNU ld for years, and this workaround is a copy/paste of the same one in the ARMv7 ld script.

Thanks,

	M.

Hi Marc,

Quoted 83 lines · Marc Zyngier

Quoted 68 lines · Albert ARIBAUD

Hi Arnab,

Quoted 63 lines · Arnab Basu

A separate linker section makes it possible to keep this code either in DDR or in some secure memory location provided specifically for the purpose.

So far no one is using this section.

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/config.mk            |    2 +-
 arch/arm/cpu/armv8/u-boot.lds |   30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletions(-)

arch/arm/config.mk +1 -1

index c339e6d..9272e9c 100644
@@ -111,7 +111,7 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
 endif

arch/arm/cpu/armv8/u-boot.lds +21 -0

index 4c12222..bd95fff 100644
@@ -8,6 +8,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <config.h>
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)

@@ -23,6 +25,34 @@ SECTIONS
 		*(.text*)
 	}
 
+#ifdef CONFIG_ARMV8_PSCI
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#endif
+
+	.__secure_start : {
+		. = ALIGN(0x1000);
+		*(.__secure_start)
+	}
+
+	.secure_text CONFIG_ARMV8_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	. = LOADADDR(.__secure_start) +
+		SIZEOF(.__secure_start) +

Quoted 8 lines

arch/arm/cpu/armv8/u-boot.lds SECTIONS · line 52

Quoted 6 lines

arch/arm/cpu/armv8/u-boot.lds +6 -0

+		SIZEOF(.secure_text);
+
+	__secure_end_lma = .;
+	.__secure_end : AT(__secure_end_lma) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */

Can you explain in more detail what issue this fixes?

If you use AT to force a new load address (LMA), you must ensure that you actually output something at this address. Here, if *(.__secure_end) ends up being empty, whatever follows would be as if the AT never happened, ending up at the wrong LMA.

Quoted 4 lines

The workaround is to force the output of a dummy value in all cases, ensuring that the rest of the text is at a sensible LMA. This is an issue that has been in GNU ld for years, and this workaround is a copy/paste of the same one in the ARMv7 ld script.

I see. Does the ld bug have an identifier that we could mention in a comment in the linker script as a reference?

Quoted 3 lines

Thanks,

	M.

Amicalement,

Hi Albert,

Quoted 109 lines · Albert ARIBAUD

Hi Marc,

Quoted 1 line · Marc Zyngier

On Thu, Sep 18 2014 at 10:12:17 AM, Albert ARIBAUD

Quoted 6 lines · <[email protected]> wrote:

Quoted 6 lines

Hi Arnab,

Quoted 1 line · Arnab Basu

A separate linker section makes it possible to keep this code

either

Quoted 1 line

Quoted 1 line

Quoted 1 line

in DDR or in some secure memory location provided specifically

for the

Quoted 10 lines

Quoted 10 lines

Quoted 10 lines

purpose.

So far no one is using this section.

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/config.mk            |    2 +-
 arch/arm/cpu/armv8/u-boot.lds |   30 

++++++++++++++++++++++++++++++

Quoted 11 lines

Quoted 11 lines

arch/arm/config.mk endif · line 114

Quoted 11 lines

 2 files changed, 31 insertions(+), 1 deletions(-)

arch/arm/config.mk +0 -1

index c339e6d..9272e9c 100644
@@ -111,7 +111,7 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list 

-j .rela.dyn

Quoted 1 line

Quoted 1 line

arch/arm/config.mk endif · line 114

Quoted 1 line

arch/arm/config.mk +1 -0

+OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .data 

-j .u_boot_list -j .rela.dyn

Quoted 2 lines

Quoted 2 lines

arch/arm/config.mk endif · line 116

Quoted 2 lines

arch/arm/config.mk +0 -0

 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash 

-j .data -j .got.plt -j .u_boot_list -j .rel.dyn

Quoted 2 lines

Quoted 2 lines

Review

Quoted 2 lines

arch/arm/config.mk +0 -0

 endif

(quoted diff) +0 -0

b/arch/arm/cpu/armv8/u-boot.lds

Quoted 10 lines

Quoted 10 lines

arch/arm/cpu/armv8/u-boot.lds line 13

Quoted 10 lines

index 4c12222..bd95fff 100644

arch/arm/cpu/armv8/u-boot.lds +2 -0

@@ -8,6 +8,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <config.h>
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", 

"elf64-littleaarch64")

Quoted 34 lines

Quoted 25 lines

Quoted 25 lines

arch/arm/cpu/armv8/u-boot.lds +19 -0

 OUTPUT_ARCH(aarch64)
 ENTRY(_start)

@@ -23,6 +25,34 @@ SECTIONS
 		*(.text*)
 	}
 
+#ifdef CONFIG_ARMV8_PSCI
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#endif
+
+	.__secure_start : {
+		. = ALIGN(0x1000);
+		*(.__secure_start)
+	}
+
+	.secure_text CONFIG_ARMV8_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	. = LOADADDR(.__secure_start) +
+		SIZEOF(.__secure_start) +

Quoted 8 lines

arch/arm/cpu/armv8/u-boot.lds SECTIONS · line 52

Quoted 6 lines

arch/arm/cpu/armv8/u-boot.lds +6 -0

+		SIZEOF(.secure_text);
+
+	__secure_end_lma = .;
+	.__secure_end : AT(__secure_end_lma) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */

Can you explain in more detail what issue this fixes?

Quoted 1 line

If you use AT to force a new load address (LMA), you must ensure

that

Quoted 1 line

you actually output something at this address. Here, if

*(.__secure_end)

Quoted 5 lines

ends up being empty, whatever follows would be as if the AT never happened, ending up at the wrong LMA.

The workaround is to force the output of a dummy value in all cases, ensuring that the rest of the text is at a sensible LMA.

This is

Quoted 1 line

an issue that has been in GNU ld for years, and this workaround is

a

Quoted 1 line

copy/paste of the same one in the ARMv7 ld script.

I see. Does the ld bug have an identifier that we could mention in a comment in the linker script as a reference?

Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented).

This is largely ported from the similar code that exists for ARMv7

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/cpu/armv8/Makefile |    1 +
 arch/arm/cpu/armv8/psci.S   |  171 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 172 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/psci.S

arch/arm/cpu/armv8/Makefile +1 -0

index 4f0ea87..8f6988d 100644
@@ -15,3 +15,4 @@ obj-y	+= cache.o
 obj-y	+= tlb.o
 obj-y	+= transition.o
 obj-y	+= cpu-dt.o
+obj-$(CONFIG_ARMV8_PSCI)	+= psci.o

arch/arm/cpu/armv8/psci.S new file +43 -0

new file mode 100644
index 0000000..5f4e3b2
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2014
+ * Arnab Basu <[email protected]>
+ *
+ * Based on arch/arm/cpu/armv7/psci.S
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+.pushsection ._secure.text, "ax"
+
+ENTRY(psci_0_2_cpu_suspend_64)
+ENTRY(psci_0_2_cpu_on_64)
+ENTRY(psci_0_2_affinity_info_64)
+ENTRY(psci_0_2_migrate_64)
+ENTRY(psci_0_2_migrate_info_up_cpu_64)
+	mov	x0, #ARM_PSCI_RET_NI	/* Return -1 (Not Implemented) */
+	ret
+ENDPROC(psci_0_2_cpu_suspend_64)
+ENDPROC(psci_0_2_cpu_on_64)
+ENDPROC(psci_0_2_affinity_info_64)
+ENDPROC(psci_0_2_migrate_64)
+ENDPROC(psci_0_2_migrate_info_up_cpu_64)
+.weak psci_0_2_cpu_suspend_64
+.weak psci_0_2_cpu_on_64
+.weak psci_0_2_affinity_info_64
+.weak psci_0_2_migrate_64
+.weak psci_0_2_migrate_info_up_cpu_64
+
+ENTRY(psci_0_2_psci_version)
+	mov	x0, #2			/* Return Major = 0, Minor = 2*/
+	ret
+ENDPROC(psci_0_2_psci_version)
+
+.align 4
+_psci_0_2_table:
+	.quad	PSCI_0_2_FN_PSCI_VERSION
+	.quad	psci_0_2_psci_version
+	.quad	PSCI_0_2_FN64_CPU_SUSPEND
+	.quad	psci_0_2_cpu_suspend_64

arch/arm/cpu/armv8/psci.S new file +8 -0

+.macro	psci_enter
+	stp	x29, x30, [sp, #-16]!
+	stp	x27, x28, [sp, #-16]!
+	stp	x25, x26, [sp, #-16]!
+	stp	x23, x24, [sp, #-16]!
+	stp	x21, x22, [sp, #-16]!
+	stp	x19, x20, [sp, #-16]!
+	stp	x17, x18, [sp, #-16]!

arch/arm/cpu/armv8/psci.S new file +11 -0

+	mrs	x4, scr_el3
+	orr	x4, x4, #1
+	msr	scr_el3, x4
+
+	ldp	x5, x4, [sp], #16
+	msr	elr_el3, x5
+	ldp	x5, x6, [sp], #16
+	ldp	x7, x8, [sp], #16
+	ldp	x9, x10, [sp], #16
+	ldp	x11, x12, [sp], #16
+	ldp	x13, x14, [sp], #16

arch/arm/cpu/armv8/psci.S new file +39 -0

+	b.eq	smc_found
+	ldr	x4, [sp], #8
+	b	default_psci_vector
+smc_found:
+	ldr     x4, [sp], #8
+	b	_smc_psci
+
+/*
+ * PSCI Exception vectors.
+ */
+	.align	11
+	.globl	psci_vectors
+psci_vectors:
+	.align	7
+	b	default_psci_vector	/* Current EL Synchronous Thread */
+	.align	7
+	b	default_psci_vector	/* Current EL IRQ Thread */
+	.align	7
+	b	default_psci_vector	/* Current EL FIQ Thread */
+	.align	7
+	b	default_psci_vector	/* Current EL Error Thread */
+	.align	7
+	b	default_psci_vector	/* Current EL Synchronous Handler */
+	.align	7
+	b	default_psci_vector	/* Current EL IRQ Handler */
+	.align	7
+	b	default_psci_vector	/* Current EL FIQ Handler */
+	.align	7
+	b	default_psci_vector	/* Current EL Error Handler */
+	.align	7
+	b	__handle_sync		/* Lower EL Synchronous (64b) */
+	.align	7
+	b	default_psci_vector	/* Lower EL IRQ (64b) */
+	.align	7
+	b	default_psci_vector	/* Lower EL FIQ (64b) */
+	.align	7
+	b	default_psci_vector	/* Lower EL Error (64b) */
+
+.popsection

Signature · 1 line

1.7.7.4

Set the enable-method in the cpu node to psci, create the psci device tree node and also add a reserve section for the psci code that lives in in normal RAM, so that the kernel leaves it alone

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/cpu/armv8/cpu-dt.c   |   67 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/system.h |    4 ++
 2 files changed, 71 insertions(+), 0 deletions(-)

arch/arm/cpu/armv8/cpu-dt.c +0 -0

index 9792bc0..c2c8fe7 100644
@@ -9,7 +9,69 @@
 #include <fdt_support.h>
 
 #ifdef CONFIG_MP

arch/arm/cpu/armv8/cpu-dt.c +19 -0

+static int cpu_update_dt_psci(void *fdt)
+{
+	int nodeoff;
+	int tmp;
+
+	psci_reserve_mem(fdt);
+
+	nodeoff = fdt_path_offset(fdt, "/cpus");
+	if (nodeoff < 0) {
+		printf("couldn't find /cpus\n");
+		return nodeoff;
+	}
+
+	/* add 'enable-method = "psci"' to each cpu node */
+	for (tmp = fdt_first_subnode(fdt, nodeoff);
+	     tmp >= 0;
+	     tmp = fdt_next_subnode(fdt, tmp)) {
+		const struct fdt_property *prop;
+		int len;

arch/arm/cpu/armv8/cpu-dt.c +9 -0

+	if (nodeoff < 0) {
+		nodeoff = fdt_path_offset(fdt, "/");
+		if (nodeoff < 0)
+			return nodeoff;
+
+		nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
+		if (nodeoff < 0)
+			return nodeoff;
+	}

Hi,

Quoted 20 lines · Arnab Basu

Set the enable-method in the cpu node to psci, create the psci device tree node and also add a reserve section for the psci code that lives in in normal RAM, so that the kernel leaves it alone

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
  arch/arm/cpu/armv8/cpu-dt.c   |   67 +++++++++++++++++++++++++++++++++++++++++
  arch/arm/include/asm/system.h |    4 ++
  2 files changed, 71 insertions(+), 0 deletions(-)

arch/arm/cpu/armv8/cpu-dt.c +0 -0

index 9792bc0..c2c8fe7 100644
@@ -9,7 +9,69 @@
  #include <fdt_support.h>
 
  #ifdef CONFIG_MP

arch/arm/cpu/armv8/cpu-dt.c line 21

Quoted 10 lines

arch/arm/cpu/armv8/cpu-dt.c +9 -0

+#ifdef CONFIG_ARMV8_PSCI
 
+static void psci_reserve_mem(void *fdt)
+{
+#ifndef CONFIG_ARMV8_SECURE_BASE
+	/* secure code lives in RAM, keep it alive */
+	fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+			__secure_end - __secure_start);
+#endif
+}

With PSCI I'd be worried about telling the OS about this memory at all.

If the OS maps the memory we could encounter issues with mismatched aliases and/or unexpected hits in the D-cache, which can result in a loss of ordering and/or visbility guarantees, which could break the PSCI implementation.

With the KVM or trusted firmware PSCI implementations the (guest) OS cannot map the implementation's memory, preventing such problems. The arm64 Linux boot-wrapper is dodgy in this regard currently.

Quoted 24 lines

arch/arm/cpu/armv8/cpu-dt.c +24 -0

+static int cpu_update_dt_psci(void *fdt)
+{
+	int nodeoff;
+	int tmp;
+
+	psci_reserve_mem(fdt);
+
+	nodeoff = fdt_path_offset(fdt, "/cpus");
+	if (nodeoff < 0) {
+		printf("couldn't find /cpus\n");
+		return nodeoff;
+	}
+
+	/* add 'enable-method = "psci"' to each cpu node */
+	for (tmp = fdt_first_subnode(fdt, nodeoff);
+	     tmp >= 0;
+	     tmp = fdt_next_subnode(fdt, tmp)) {
+		const struct fdt_property *prop;
+		int len;
+
+		prop = fdt_get_property(fdt, tmp, "device_type", &len);
+		if (!prop)
+			continue;
+		if (len < 4)

arch/arm/cpu/armv8/cpu-dt.c line 51

Quoted 5 lines

arch/arm/cpu/armv8/cpu-dt.c +5 -0

+			continue;
+		if (strcmp(prop->data, "cpu"))
+			continue;
+
+		fdt_setprop_string(fdt, tmp, "enable-method", "psci");

Do we need to check the return code here, as we do when setting up the psci node?

arch/arm/cpu/armv8/cpu-dt.c line 54

Quoted 3 lines

arch/arm/cpu/armv8/cpu-dt.c +3 -0

+	}
+
+	nodeoff = fdt_path_offset(fdt, "/psci");

We might need to search by compatible string. All psci nodes so far have been called /psci, but that's not guaranteed. Linux looks for nodes compatible with "arm,psci" and/or "arm,psci-0.2".

Quoted 13 lines

arch/arm/cpu/armv8/cpu-dt.c +13 -0

+	if (nodeoff < 0) {
+		nodeoff = fdt_path_offset(fdt, "/");
+		if (nodeoff < 0)
+			return nodeoff;
+
+		nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
+		if (nodeoff < 0)
+			return nodeoff;
+	}
+
+	tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci-0.2");
+	if (tmp)
+		return tmp;

arch/arm/cpu/armv8/cpu-dt.c line 73

Quoted 6 lines

arch/arm/cpu/armv8/cpu-dt.c +6 -0

+	tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
+	if (tmp)
+		return tmp;
+
+	return 0;
+}

Otherwise this looks fine.

Mark.

Quoted 21 lines

Quoted 8 lines

arch/arm/cpu/armv8/cpu-dt.c +0 -0

index 9792bc0..c2c8fe7 100644
@@ -9,7 +9,69 @@
  #include <fdt_support.h>
 
  #ifdef CONFIG_MP

arch/arm/cpu/armv8/cpu-dt.c line 21

Quoted 10 lines

arch/arm/cpu/armv8/cpu-dt.c +9 -0

+#ifdef CONFIG_ARMV8_PSCI
 
+static void psci_reserve_mem(void *fdt)
+{
+#ifndef CONFIG_ARMV8_SECURE_BASE
+	/* secure code lives in RAM, keep it alive */
+	fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+			__secure_end - __secure_start);
+#endif
+}

With PSCI I'd be worried about telling the OS about this memory at all.

Quoted 9 lines

If the OS maps the memory we could encounter issues with mismatched aliases and/or unexpected hits in the D-cache, which can result in a loss of ordering and/or visbility guarantees, which could break the PSCI implementation.

With the KVM or trusted firmware PSCI implementations the (guest) OS cannot map the implementation's memory, preventing such problems. The arm64 Linux boot-wrapper is dodgy in this regard currently.

The idea here is that if there is no PSCI specific (most likely secure) memory allocated in the system, the macro "CONFIG_ARMV8_SECURE_BASE" will not be defined. In this case the PSCI vector table and its support code will be in DDR and will be protected from Linux using memreserve.

If this macro is defined the assumption is that it points to some non-ddr location, say secure OCRAM. In this case U-Boot will copy the PSCI vector table and its support code to that region and we are hoping that this address space is not visible to the OS in the first place.

This is my understanding of the code, maybe Marc would like to comment on if this was the thinking in ARMv7.

Quoted 8 lines

arch/arm/cpu/armv8/cpu-dt.c line 54

Quoted 3 lines

arch/arm/cpu/armv8/cpu-dt.c +3 -0

+	}
+
+	nodeoff = fdt_path_offset(fdt, "/psci");

We might need to search by compatible string. All psci nodes so far have been called /psci, but that's not guaranteed. Linux looks for nodes compatible with "arm,psci" and/or "arm,psci-0.2".

I see that it is called "Main node" in the kernel documentation. Any reason it's name has not been fixed to "psci"? Is it too late to do that and save myself some work here? :)

Hi,

Quoted 31 lines

Quoted 21 lines

Quoted 8 lines

arch/arm/cpu/armv8/cpu-dt.c +0 -0

index 9792bc0..c2c8fe7 100644
@@ -9,7 +9,69 @@
  #include <fdt_support.h>
 
  #ifdef CONFIG_MP

arch/arm/cpu/armv8/cpu-dt.c line 21

Quoted 10 lines

arch/arm/cpu/armv8/cpu-dt.c +9 -0

+#ifdef CONFIG_ARMV8_PSCI
 
+static void psci_reserve_mem(void *fdt)
+{
+#ifndef CONFIG_ARMV8_SECURE_BASE
+	/* secure code lives in RAM, keep it alive */
+	fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+			__secure_end - __secure_start);
+#endif
+}

With PSCI I'd be worried about telling the OS about this memory at all.

Quoted 9 lines

If the OS maps the memory we could encounter issues with mismatched aliases and/or unexpected hits in the D-cache, which can result in a loss of ordering and/or visbility guarantees, which could break the PSCI implementation.

With the KVM or trusted firmware PSCI implementations the (guest) OS cannot map the implementation's memory, preventing such problems. The arm64 Linux boot-wrapper is dodgy in this regard currently.

Quoted 4 lines

The idea here is that if there is no PSCI specific (most likely secure) memory allocated in the system, the macro "CONFIG_ARMV8_SECURE_BASE" will not be defined. In this case the PSCI vector table and its support code will be in DDR and will be protected from Linux using memreserve.

Sure, this will prevent the OS from explicitly modifying this memory.

However, the OS will still map the memory. This renders the protection incomplete due to the possibility of mismatched attributes and/or unexpected cache hits resulting in nasty coherency problems. We are likely to get away with this most of the time (if the kernel and U-Boot use the same attributes), but it would be very easy to blow things up accidentally.

The only way to prevent that is to completely remove a portion of the memory from the view of the OS, such that it doesn't map the memory at all.

Quoted 4 lines

The idea here is that if there is no PSCI specific (most likely secure) memory allocated in the system, the macro "CONFIG_ARMV8_SECURE_BASE" will not be defined. In this case the PSCI vector table and its support code will be in DDR and will be protected from Linux using memreserve.

Sure, this will prevent the OS from explicitly modifying this memory.

However, the OS will still map the memory. This renders the protection incomplete due to the possibility of mismatched attributes and/or unexpected cache hits resulting in nasty coherency problems. We are likely to get away with this most of the time (if the kernel and U-Boot use the same attributes), but it would be very easy to blow things up accidentally.

The only way to prevent that is to completely remove a portion of the memory from the view of the OS, such that it doesn't map the memory at all.

Quoted 14 lines

Quoted 4 lines

The idea here is that if there is no PSCI specific (most likely secure) memory allocated in the system, the macro "CONFIG_ARMV8_SECURE_BASE" will not be defined. In this case the PSCI vector table and its support code will be in DDR and will be protected from Linux using memreserve.

Sure, this will prevent the OS from explicitly modifying this memory.

However, the OS will still map the memory. This renders the protection incomplete due to the possibility of mismatched attributes and/or unexpected cache hits resulting in nasty coherency problems. We are likely to get away with this most of the time (if the kernel and U-Boot use the same attributes), but it would be very easy to blow things up accidentally.

Quoted 3 lines

The only way to prevent that is to completely remove a portion of the memory from the view of the OS, such that it doesn't map the memory at all.

Can't this be done by simply removing that secure portion of memory from the memory advertised in the memory node of the device tree passed to the non-secure OS? ...should prevent the OS from mapping the memory.

Enable the SMC instruction so that the kernel can use the psci code

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/include/asm/macro.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

arch/arm/include/asm/macro.h +0 -0

index 0009c28..94a1e68 100644

-----Original Message-----
From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
Sent: Thursday, September 18, 2014 2:48 PM
To: Basu Arnab-B45036
Cc: marc.zyngier at arm.com; mark.rutland at arm.com; Sun York-R58495; Yoder Stuart-B08248; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 8/8] ARMv8: PSCI: Enable SMC

Hi Arnab,

Quoted 16 lines · Arnab Basu

Enable the SMC instruction so that the kernel can use the psci code

Signed-off-by Arnab Basu <[email protected]>

Reviewed-by Bhupesh Sharma <[email protected]>

Cc Marc Zyngier <[email protected]>

---
 arch/arm/include/asm/macro.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

(quoted diff) +0 -0

b/arch/arm/include/asm/macro.h index 0009c28..94a1e68 100644

arch/arm/include/asm/macro.h +0 -0

@@ -106,7 +106,11 @@ lr	.req	x30
 .endm
 

arch/arm/include/asm/macro.h lr .req x30 · line 112

Quoted 5 lines

arch/arm/include/asm/macro.h +3 -0

 .macro armv8_switch_to_el2_m, xreg1
+#ifdef CONFIG_ARMV8_PSCI
+	mov	\xreg1, #0x531	/* Non-secure EL0/EL1 | HVC | 64bit EL2 */
+#else
 	mov	\xreg1, #0x5b1	/* Non-secure EL0/EL1 | HVC | 64bit EL2 */

The 'mov' lines have different constant arguments in the instruction; their explanatory comments should not be the same.

arch/arm/include/asm/macro.h lr .req x30 · line 116

Quoted 4 lines

arch/arm/include/asm/macro.h +1 -0

+#endif
 	msr	scr_el3, \xreg1
 	msr	cptr_el3, xzr	/* Disable coprocessor traps to EL3 */
 	mov	\xreg1, #0x33ff

Amicalement,
--
Albert.

This series of patches creates a generic PSCI v0.2 framework for ARMv8.

The first 3 patches refactor existing code so that ARMv7 PSCI, ARMv8 spin-table and ARMv8 PSCI can coexist.

The next 5 patches create a generic framework for PSCI v0.2 in ARMv8.

The implementation is modelled on the pre-existing PSCI v0.1 support in ARMv7.

PSCI support patches for the ARMv8 Foundation model will follow shortly.

Arnab Basu (8):
ARM: PSCI: Update psci.h for psci v0.2
ARM: PSCI: Alow arch specific DT patching ARMv8/fsl-lsch3: Refactor spin-table code
ARMv8: PSCI: Add linker section to hold PSCI code
ARMv8: PCSI: Add generic ARMv8 PSCI code
ARMv8: PSCI: Fixup the device tree for PSCI v0.2
ARMv8: PSCI: Setup ARMv8 PSCI
ARMv8: PSCI: Enable SMC

  arch/arm/config.mk                 |    2 +-
  arch/arm/cpu/armv7/virt-dt.c       |    7 +-
  arch/arm/cpu/armv8/Makefile        |    2 +
  arch/arm/cpu/armv8/cpu-dt.c        |  128 ++++++++++++++++++++++++++
  arch/arm/cpu/armv8/cpu.c           |   23 +++++
  arch/arm/cpu/armv8/fsl-lsch3/fdt.c |   46 +++------
  arch/arm/cpu/armv8/psci.S          |  177 ++++++++++++++++++++++++++++++++++++
  arch/arm/cpu/armv8/u-boot.lds      |   30 ++++++
  arch/arm/include/asm/macro.h       |    4 +
  arch/arm/include/asm/psci.h        |   42 ++++++++-
  arch/arm/include/asm/system.h      |    7 ++
  arch/arm/lib/bootm-fdt.c           |   11 ++-
  arch/arm/lib/bootm.c               |    3 +
  13 files changed, 446 insertions(+), 36 deletions(-)

create mode 100644 arch/arm/cpu/armv8/cpu-dt.c
create mode 100644 arch/arm/cpu/armv8/psci.S

This series of patches creates a generic PSCI v0.2 framework for ARMv8.

The first 3 patches refactor existing code so that ARMv7 PSCI, ARMv8 spin-table and ARMv8 PSCI can coexist.

The next 5 patches create a generic framework for PSCI v0.2 in ARMv8.

The implementation is modelled on the pre-existing PSCI v0.1 support in ARMv7.

PSCI support patches for the ARMv8 Foundation model will follow shortly.

Quoted 10 lines · Arnab Basu

This series of patches creates a generic PSCI v0.2 framework for ARMv8.

The first 3 patches refactor existing code so that ARMv7 PSCI, ARMv8 spin-table and ARMv8 PSCI can coexist.

The next 5 patches create a generic framework for PSCI v0.2 in ARMv8.

The implementation is modelled on the pre-existing PSCI v0.1 support in ARMv7.

Quoted 2 lines

PSCI support patches for the ARMv8 Foundation model will follow shortly.

What's the status of this effort? I'll look into v0.2 support for v7 soon, so I was wondering if there is something recent to possibly build upon / derive from.