Skip to contentSkip to conversation

Commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke mpc85xx

U-Boot York Sun 3 participants 9 messages Oct 1, 2014 – Oct 2, 2014

lore
Share & tools
lore

York Sun

author
#0 lore raw

Simon,

I didn't notice until today the commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke at least T4240QDS. I have narrowed down to these two lines in common/board_r.c

initr_barrier,
initr_malloc,

If I move these two lines below this part

#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif

U-boot boots OK on T4240QDS (I can see the prompt). But if I move them anywhere above this initr_unlock_ram_in_cache, it hangs the core when initializing PCI. It may break other mpc85xx platforms but I didn't have time to check more today. I haven't figured out why you have to move these two lines up. Please take a close look.

Thanks,

York

#1 lore raw

Hi York,

Quoted 17 lines · York Sun

Simon,

I didn't notice until today the commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke at least T4240QDS. I have narrowed down to these two lines in common/board_r.c

initr_barrier,
initr_malloc,

If I move these two lines below this part

#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif

Quoted 5 lines

U-boot boots OK on T4240QDS (I can see the prompt). But if I move them anywhere above this initr_unlock_ram_in_cache, it hangs the core when initializing PCI. It may break other mpc85xx platforms but I didn't have time to check more today. I haven't figured out why you have to move these two lines up. Please take a close look.

I could adjust this so that the ordering changes only when driver model is used.

This would be a case of putting '#ifdef CONFIG_DM' around the first section, then repeating it later with '#ifndef CONFIG_DM'. You can see that I did this for stdio out of an abundance of caution.

However, in the interests of supporting driver model on these platforms I wonder if it might be possible to move the cache logic earlier. I suspect that the unlock/invalidate should happen before post-relocation RAM is used.

Please take a look and let me know if that might be possible. Otherwise we'll have to go with the fallback.

BTW I don't have any of these boards. If there is one that is readily and cheaply available, or if you have an old one you can send me, I'd be happy to test on this and take a closer look at driver model support.

Regards,
Simon

author
#2 lore raw
Quoted 33 lines · Simon Glass

Hi York,

Quoted 17 lines · York Sun

Simon,

I didn't notice until today the commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke at least T4240QDS. I have narrowed down to these two lines in common/board_r.c

initr_barrier,
initr_malloc,

If I move these two lines below this part

#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif

Quoted 5 lines

U-boot boots OK on T4240QDS (I can see the prompt). But if I move them anywhere above this initr_unlock_ram_in_cache, it hangs the core when initializing PCI. It may break other mpc85xx platforms but I didn't have time to check more today. I haven't figured out why you have to move these two lines up. Please take a close look.

I could adjust this so that the ordering changes only when driver model is used.

This would be a case of putting '#ifdef CONFIG_DM' around the first section, then repeating it later with '#ifndef CONFIG_DM'. You can see that I did this for stdio out of an abundance of caution.

Quoted 7 lines

However, in the interests of supporting driver model on these platforms I wonder if it might be possible to move the cache logic earlier. I suspect that the unlock/invalidate should happen before post-relocation RAM is used.

Please take a look and let me know if that might be possible. Otherwise we'll have to go with the fallback.

I can change init sequence as far as I put initr_unlock_ram_in_cache before initr_malloc, T4240QDS still boots.

I examine the code but don't understand why I have to do so. P4080DS doesn't suffer this issue. I am going to seek some help from Scott and other in-house experts.

Quoted 5 lines

BTW I don't have any of these boards. If there is one that is readily and cheaply available, or if you have an old one you can send me, I'd be happy to test on this and take a closer look at driver model support.

I checked but we don't have surplus. This board is relatively new and it sells for $4000. I will keep an eye on it.

York

#3 lore raw

Hi York,

Quoted 54 lines · York Sun
Quoted 25 lines · Simon Glass

Hi York,

Quoted 21 lines · York Sun

Simon,

I didn't notice until today the commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke at least T4240QDS. I have narrowed down to these two lines in common/board_r.c

initr_barrier,
initr_malloc,

If I move these two lines below this part

#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif

U-boot boots OK on T4240QDS (I can see the prompt). But if I move them anywhere above this initr_unlock_ram_in_cache, it hangs the core when initializing PCI. It may break other mpc85xx platforms but I didn't have time to check more today. I haven't figured out why you have to move

these

Quoted 3 lines
Quoted 1 line

two lines up. Please take a close look.

I could adjust this so that the ordering changes only when driver model

is used.

Quoted 5 lines

This would be a case of putting '#ifdef CONFIG_DM' around the first section, then repeating it later with '#ifndef CONFIG_DM'. You can see that I did this for stdio out of an abundance of caution.

Quoted 7 lines

However, in the interests of supporting driver model on these platforms I wonder if it might be possible to move the cache logic earlier. I suspect that the unlock/invalidate should happen before post-relocation RAM is used.

Please take a look and let me know if that might be possible. Otherwise we'll have to go with the fallback.

I can change init sequence as far as I put initr_unlock_ram_in_cache before initr_malloc, T4240QDS still boots.

I examine the code but don't understand why I have to do so. P4080DS doesn't
suffer this issue. I am going to seek some help from Scott and other in-house
experts.

Quoted 1 line
Quoted 9 lines
Quoted 4 lines

BTW I don't have any of these boards. If there is one that is readily and cheaply available, or if you have an old one you can send me, I'd be happy to test on this and take a closer look at driver model support.

I checked but we don't have surplus. This board is relatively new and it sells
for $4000. I will keep an eye on it.

Gosh. Is there something else relatively common in the PPC world that sells for $100-200?

Regards,
Simon

author
#4 lore raw
Quoted 4 lines · Simon Glass

Gosh. Is there something else relatively common in the PPC world that sells for $100-200?

Unlikely. This is high end SoC.

York

#5 lore raw

Hi York,

Quoted 7 lines · York Sun
Quoted 4 lines · Simon Glass

Gosh. Is there something else relatively common in the PPC world that sells for $100-200?

Unlikely. This is high end SoC.

Well is there is some PPC board that is supported by U-Boot, relatively recent? Not high-end?

Regards,
Simon

author
#6 lore raw
Quoted 5 lines · Simon Glass

Hi York,

Quoted 2 lines · York Sun
Quoted 1 line · Simon Glass
Quoted 9 lines
Quoted 5 lines
Quoted 3 lines

Gosh. Is there something else relatively common in the PPC world that sells for $100-200?

Unlikely. This is high end SoC.

Well is there is some PPC board that is supported by U-Boot, relatively recent? Not high-end?

The most recent T1040RDB costs about $1250 according to searching online. $100-$200 is not the range for recent mpc85xx boards.

York

#7 lore raw
In reply to York Sun
Quoted 39 lines · York Sun
Quoted 38 lines · Simon Glass

Hi York,

Quoted 17 lines · York Sun

Simon,

I didn't notice until today the commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 broke at least T4240QDS. I have narrowed down to these two lines in common/board_r.c

initr_barrier,
initr_malloc,

If I move these two lines below this part

#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif

Quoted 5 lines

U-boot boots OK on T4240QDS (I can see the prompt). But if I move them anywhere above this initr_unlock_ram_in_cache, it hangs the core when initializing PCI. It may break other mpc85xx platforms but I didn't have time to check more today. I haven't figured out why you have to move these two lines up. Please take a close look.

I could adjust this so that the ordering changes only when driver model is used.

This would be a case of putting '#ifdef CONFIG_DM' around the first section, then repeating it later with '#ifndef CONFIG_DM'. You can see that I did this for stdio out of an abundance of caution.

However, in the interests of supporting driver model on these platforms I wonder if it might be possible to move the cache logic earlier. I suspect that the unlock/invalidate should happen before post-relocation RAM is used.

Quoted 5 lines
Quoted 2 lines

Please take a look and let me know if that might be possible. Otherwise we'll have to go with the fallback.

I can change init sequence as far as I put initr_unlock_ram_in_cache before initr_malloc, T4240QDS still boots.

Yes, we shouldn't have any reason to keep the cache locked that long.

Quoted 3 lines

I examine the code but don't understand why I have to do so. P4080DS doesn't suffer this issue. I am going to seek some help from Scott and other in-house experts.

My guess is that it has to do with the way caches work on e6500. We try to lock lines in L1, but L1 can't hold dirty lines, so perhaps the hang comes when the DDR activity evicts the dirty lines from L2 (where they weren't locked).

-Scott

author
#8 lore raw
Quoted 6 lines · Scott Wood
Quoted 3 lines

I can change init sequence as far as I put initr_unlock_ram_in_cache before initr_malloc, T4240QDS still boots.

Yes, we shouldn't have any reason to keep the cache locked that long.

Quoted 9 lines
Quoted 3 lines

I examine the code but don't understand why I have to do so. P4080DS doesn't suffer this issue. I am going to seek some help from Scott and other in-house experts.

My guess is that it has to do with the way caches work on e6500. We try to lock lines in L1, but L1 can't hold dirty lines, so perhaps the hang comes when the DDR activity evicts the dirty lines from L2 (where they weren't locked).

Scott,

Thanks for looking into this. I can propose a fix, but first I will have to do a thorough test on all varieties of 85xx board we have.

York