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armv7: s5pc1xx: improve cache handling

PATCH New Robert Baldyga 2 participants 2 messages Sep 19, 2014 – Oct 8, 2014 Arm (32-bit)

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PATCH 1/1 armv7: s5pc1xx: improve cache handling

Move cache handling code to C file, and add enable_caches() and disable_caches() functions.

---
 arch/arm/cpu/armv7/s5pc1xx/cache.S | 30 ------------------------
 arch/arm/cpu/armv7/s5pc1xx/cache.c | 47 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 30 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.S
 create mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.c
arch/arm/cpu/armv7/s5pc1xx/cache.S deleted +0 -30
deleted file mode 100644
index 3089592..0000000
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <[email protected]>
- *
- * based on arch/arm/cpu/armv7/omap3/cache.S
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-.align 5
-
-#include <linux/linkage.h>
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-ENTRY(v7_outer_cache_enable)
-	push	{r0, r1, r2, lr}
-	mrc	15, 0, r3, cr1, cr0, 1
-	orr	r3, r3, #2
-	mcr	15, 0, r3, cr1, cr0, 1
-	pop	{r1, r2, r3, pc}
-ENDPROC(v7_outer_cache_enable)
-
-ENTRY(v7_outer_cache_disable)
-	push	{r0, r1, r2, lr}
-	mrc	15, 0, r3, cr1, cr0, 1
-	bic	r3, r3, #2
-	mcr	15, 0, r3, cr1, cr0, 1
-	pop	{r1, r2, r3, pc}
-ENDPROC(v7_outer_cache_disable)
-#endif
arch/arm/cpu/armv7/s5pc1xx/cache.c new file +47 -0

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1.9.1
#1 lore raw

PATCH 1/1 armv7: s5pc1xx: improve cache handling

Quoted 11 lines · Robert Baldyga

Move cache handling code to C file, and add enable_caches() and disable_caches() functions.

---
 arch/arm/cpu/armv7/s5pc1xx/cache.S | 30 ------------------------
 arch/arm/cpu/armv7/s5pc1xx/cache.c | 47 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 30 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.S
 create mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.c

applied to u-boot-samsung.

Thanks,
Minkyu Kang.