cpufreq: use generic cpufreq drivers for exynos platforms

PATCH Superseded Thomas Abraham 7 participants 21 messages Oct 20, 2014 – Nov 25, 2014

Subsystems (7)

Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +3 more subsystems

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Thomas Abraham

author

2014-10-20 11:29 UTC #0 lore raw

v11 cover cpufreq: use generic cpufreq drivers for exynos platforms

Changes since v10:
- Rebased on top of v3.18-rc1

This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver.

This patch series is based and tested on v3.18-rc1 and depends on the patch
- "clk: exynos4: remove duplicate div_core2 divider clock instantiation"
(http://www.mail-archive.com/[email protected]/msg34859.html)
This patch has been merged in "arm-soc/samsung/dt3" branch of arm-soc tree.

Thomas Abraham

author

2014-10-20 11:29 UTC #1 lore raw

PATCH v11 1/6 clk: samsung: add infrastructure to register cpu clocks

The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms.

Signed-off-by Thomas Abraham <[email protected]>

Reviewed-by Tomasz Figa <[email protected]>

Acked-by Mike Turquette <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Tested-by Chander Kashyap <[email protected]>

---
 drivers/clk/samsung/Makefile  |    2 +-
 drivers/clk/samsung/clk-cpu.c |  335 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-cpu.h |   91 +++++++++++
 3 files changed, 427 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/samsung/clk-cpu.c
 create mode 100644 drivers/clk/samsung/clk-cpu.h

drivers/clk/samsung/Makefile +1 -1

index 6fb4bc6..8909c93 100644
@@ -2,7 +2,7 @@
 # Samsung Clock specific Makefile
 #
 
-obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o clk-cpu.o
 obj-$(CONFIG_SOC_EXYNOS3250)	+= clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o

drivers/clk/samsung/clk-cpu.c new file +335 -0

335 lines not on this page · raw message

drivers/clk/samsung/clk-cpu.h new file +91 -0

91 lines not on this page · raw message

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2014-10-20 11:29 UTC #2 lore raw

PATCH v11 2/6 clk: samsung: add cpu clock configuration data and instantiate cpu clock

With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210, Exynos5250 and Exynos5420.

Cc Tomasz Figa <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Mike Turquette <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Tested-by Chander Kashyap <[email protected]>

---
 drivers/clk/samsung/clk-exynos4.c      |   15 ++++++++++
 drivers/clk/samsung/clk-exynos5250.c   |   25 +++++++++++++++++
 drivers/clk/samsung/clk-exynos5420.c   |   45 ++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/exynos5250.h |    1 +
 include/dt-bindings/clock/exynos5420.h |    2 +
 5 files changed, 88 insertions(+), 0 deletions(-)

drivers/clk/samsung/clk-exynos4.c +15 -0

index 940f028..9af5767 100644
@@ -19,6 +19,7 @@
 #include <linux/syscore_ops.h>
 
 #include "clk.h"
+#include "clk-cpu.h"
 
 /* Exynos4 clock controller register offsets */
 #define SRC_LEFTBUS		0x4200

@@ -1354,6 +1355,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
 			VPLL_LOCK, VPLL_CON0, NULL),
 };
 
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+	{ 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+	{ 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+	{  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+	{  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+	{  0 },
+};
+
 static void __init exynos4_core_down_clock(enum exynos4_soc soc)
 {
 	unsigned int tmp;

@@ -1457,6 +1468,10 @@ static void __init exynos4_clk_init(struct device_node *np,
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4210_fixed_factor_clks,
 			ARRAY_SIZE(exynos4210_fixed_factor_clks));
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+			e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
 	} else {
 		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
 			ARRAY_SIZE(exynos4x12_mux_clks));

drivers/clk/samsung/clk-exynos5250.c +25 -0

index 70ec3d2..e19e365 100644
@@ -19,6 +19,7 @@
 #include <linux/syscore_ops.h>
 
 #include "clk.h"
+#include "clk-cpu.h"
 
 #define APLL_LOCK		0x0
 #define APLL_CON0		0x100

@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
 		VPLL_LOCK, VPLL_CON0, NULL),
 };
 
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
+	{ 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+	{ 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+	{ 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+	{ 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+	{ 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+	{  0 },
+};
+
 static const struct of_device_id ext_clk_match[] __initconst = {
 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
 	{ },

@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
 			ARRAY_SIZE(exynos5250_div_clks));
 	samsung_clk_register_gate(ctx, exynos5250_gate_clks,
 			ARRAY_SIZE(exynos5250_gate_clks));
+	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
+			CLK_CPU_HAS_DIV1);
 
 	/*
 	 * Enable arm clock down (in idle) and set arm divider

drivers/clk/samsung/clk-exynos5420.c +45 -0

63 lines not on this page · raw message

include/dt-bindings/clock/exynos5250.h +1 -0

index 4273891..8183d1c 100644
@@ -21,6 +21,7 @@
 #define CLK_FOUT_CPLL		6
 #define CLK_FOUT_EPLL		7
 #define CLK_FOUT_VPLL		8
+#define CLK_ARM_CLK		9
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_CAM_BAYER	128

include/dt-bindings/clock/exynos5420.h +2 -0

index 8dc0913..ec0af64 100644
@@ -25,6 +25,8 @@
 #define CLK_FOUT_MPLL		10
 #define CLK_FOUT_BPLL		11
 #define CLK_FOUT_KPLL		12
+#define CLK_ARM_CLK		13
+#define CLK_KFC_CLK		14
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_UART0		128

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2014-10-20 11:30 UTC #3 lore raw

PATCH v11 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property

For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers.

Cc Kukjin Kim <[email protected]>

Cc Doug Anderson <[email protected]>

Cc Javier Martinez Canillas <[email protected]>

Cc Andreas Faerber <[email protected]>

Cc Sachin Kamat <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Reviewed-by Andreas Farber <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Tested-by Chander Kashyap <[email protected]>

---
 arch/arm/boot/dts/exynos4210-origen.dts         |    4 ++
 arch/arm/boot/dts/exynos4210-trats.dts          |    4 ++
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    4 ++
 arch/arm/boot/dts/exynos4210.dtsi               |   14 ++++++++-
 arch/arm/boot/dts/exynos5250-arndale.dts        |    4 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    4 ++
 arch/arm/boot/dts/exynos5250-snow.dts           |    4 ++
 arch/arm/boot/dts/exynos5250.dtsi               |   25 ++++++++++++++-
 arch/arm/boot/dts/exynos5420.dtsi               |   38 +++++++++++++++++++++++
 9 files changed, 99 insertions(+), 2 deletions(-)

arch/arm/boot/dts/exynos4210-origen.dts +4 -0

index f767c42..887dded 100644
@@ -334,3 +334,7 @@
 		};
 	};
 };
+
+&cpu0 {
+	cpu0-supply = <&buck1_reg>;
+};

arch/arm/boot/dts/exynos4210-trats.dts +4 -0

index f516da9..66119dd 100644
@@ -446,3 +446,7 @@
 		};
 	};
 };
+
+&cpu0 {
+	cpu0-supply = <&varm_breg>;
+};

arch/arm/boot/dts/exynos4210-universal_c210.dts +4 -0

index d50eb3a..bf0a39c 100644
@@ -492,3 +492,7 @@
 &mdma1 {
 	reg = <0x12840000 0x1000>;
 };
+
+&cpu0 {
+	cpu0-supply = <&vdd_arm_reg>;
+};

arch/arm/boot/dts/exynos4210.dtsi +13 -1

index bcc9e63..69bac07 100644
@@ -35,10 +35,22 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@900 {
+		cpu0: cpu@900 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0x900>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu";
+			clock-latency = <160000>;
+
+			operating-points = <
+				1200000 1250000
+				1000000 1150000
+				800000	1075000
+				500000	975000
+				400000	975000
+				200000	950000
+			>;
 		};
 
 		cpu@901 {

arch/arm/boot/dts/exynos5250-arndale.dts +4 -0

index 7e728a1..ac07cdf 100644
@@ -548,6 +548,10 @@
 	cap-sd-highspeed;
 };
 
+&cpu0 {
+	cpu0-supply = <&buck2_reg>;
+};
+
 &rtc {
 	status = "okay";
 };

arch/arm/boot/dts/exynos5250-smdk5250.dts +4 -0

index bc27cc2..d91db82 100644
@@ -410,3 +410,7 @@
 		};
 	};
 };
+
+&cpu0 {
+	cpu0-supply = <&buck2_reg>;
+};

arch/arm/boot/dts/exynos5250-snow.dts +4 -0

index f9bc04b..8459fb6 100644
@@ -599,6 +599,10 @@
 	};
 };
 
+&cpu0 {
+	cpu0-supply = <&buck2_reg>;
+};
+
 &rtc {
 	status = "okay";
 	clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;

arch/arm/boot/dts/exynos5250.dtsi +24 -1

index 012b021..bccdd22 100644
@@ -58,11 +58,34 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 			clock-frequency = <1700000000>;
+
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu";
+			clock-latency = <140000>;
+
+			operating-points = <
+				1700000 1300000
+				1600000 1250000
+				1500000 1225000
+				1400000 1200000
+				1300000 1150000
+				1200000 1125000
+				1100000 1100000
+				1000000 1075000
+				 900000 1050000
+				 800000 1025000
+				 700000 1012500
+				 600000 1000000
+				 500000  975000
+				 400000  950000
+				 300000  937500
+				 200000  925000
+			>;
 		};
 		cpu@1 {
 			device_type = "cpu";

arch/arm/boot/dts/exynos5420.dtsi +38 -0

index 8617a03..1df164e 100644
@@ -59,8 +59,26 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu-cluster.0";
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <140000>;
+
+			operating-points = <
+				1800000 1250000
+				1700000 1212500
+				1600000 1175000
+				1500000 1137500
+				1400000 1112500
+				1300000 1062500
+				1200000 1037500
+				1100000 1012500
+				1000000 987500
+				 900000 962500
+				 800000 937500
+				 700000 912500
+			>;
 		};
 
 		cpu1: cpu@1 {

@@ -69,6 +87,7 @@
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <140000>;
 		};
 
 		cpu2: cpu@2 {

@@ -77,6 +96,7 @@
 			reg = <0x2>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <140000>;
 		};
 
 		cpu3: cpu@3 {

@@ -85,14 +105,29 @@
 			reg = <0x3>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <140000>;
 		};
 
 		cpu4: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
+			clocks = <&clock CLK_KFC_CLK>;
+			clock-names = "cpu-cluster.1";
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <140000>;
+
+			operating-points = <
+				1300000 1275000
+				1200000 1212500
+				1100000 1162500
+				1000000 1112500
+				 900000 1062500
+				 800000 1025000
+				 700000 975000
+				 600000 937500
+			>;
 		};
 
 		cpu5: cpu@101 {

@@ -101,6 +136,7 @@
 			reg = <0x101>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <140000>;
 		};
 
 		cpu6: cpu@102 {

@@ -109,6 +145,7 @@
 			reg = <0x102>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <140000>;
 		};
 
 		cpu7: cpu@103 {

@@ -117,6 +154,7 @@
 			reg = <0x103>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <140000>;
 		};
 	};

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2014-10-20 11:30 UTC #4 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.

Cc Kukjin Kim <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Reviewed-by Tomasz Figa <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Tested-by Chander Kashyap <[email protected]>

---
 arch/arm/mach-exynos/exynos.c |   24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)

arch/arm/mach-exynos/exynos.c +23 -1

index 6b283eb..a1be294 100644
@@ -282,6 +282,28 @@ static void __init exynos_init_irq(void)
 	exynos_map_pmu();
 }
 
+static const struct of_device_id exynos_cpufreq_matches[] = {
+	{ .compatible = "samsung,exynos5420", .data = "arm-bL-cpufreq-dt" },
+	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+	{ .compatible = "samsung,exynos4210", .data = "cpufreq-dt" },
+	{ .compatible = "samsung,exynos5440", .data = "exynos5440-cpufreq" },
+	{ /* sentinel */ }
+};
+
+static void __init exynos_cpufreq_init(void)
+{
+	struct device_node *root = of_find_node_by_path("/");
+	const struct of_device_id *match;
+
+	match = of_match_node(exynos_cpufreq_matches, root);
+	if (!match) {
+		platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
+		return;
+	}
+
+	platform_device_register_simple(match->data, -1, NULL, 0);
+}
+
 static void __init exynos_dt_machine_init(void)
 {
 	struct device_node *i2c_np;

@@ -321,7 +343,7 @@ static void __init exynos_dt_machine_init(void)
 			of_machine_is_compatible("samsung,exynos5250"))
 		platform_device_register(&exynos_cpuidle);
 
-	platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
+	exynos_cpufreq_init();
 
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2014-10-20 11:30 UTC #5 lore raw

PATCH v11 5/6 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support

Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed.

Cc Bartlomiej Zolnierkiewicz <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Viresh Kumar <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Tested-by Chander Kashyap <[email protected]>

---
 drivers/cpufreq/Kconfig.arm |   22 ----------------------
 drivers/cpufreq/Makefile    |    2 --
 2 files changed, 0 insertions(+), 24 deletions(-)

drivers/cpufreq/Kconfig.arm +0 ~~-22~~

index 83a75dc..701f5ca 100644
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
 config ARM_EXYNOS_CPUFREQ
 	bool
 
-config ARM_EXYNOS4210_CPUFREQ
-	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS4210
-	  SoC (S5PV310 or S5PC210).
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS4X12_CPUFREQ
 	bool "SAMSUNG EXYNOS4x12"
 	depends on SOC_EXYNOS4212 || SOC_EXYNOS4412

@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
 
 	  If in doubt, say N.
 
-config ARM_EXYNOS5250_CPUFREQ
-	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS5250
-	  SoC.
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS5440_CPUFREQ
 	bool "SAMSUNG EXYNOS5440"
 	depends on SOC_EXYNOS5440

drivers/cpufreq/Makefile +0 -2

index 40c53dc..74e55f9 100644
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ)		+= arm_big_little_dt.o
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci-cpufreq.o
 obj-$(CONFIG_UX500_SOC_DB8500)		+= dbx500-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)	+= exynos5440-cpufreq.o
 obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ)	+= highbank-cpufreq.o
 obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2014-10-20 11:31 UTC #6 lore raw

PATCH v11 6/6 clk: samsung: remove unused clock aliases and update clock flags

With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags.

Cc Tomasz Figa <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Viresh Kumar <[email protected]>

Acked-by Mike Turquette <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Tested-by Chander Kashyap <[email protected]>

---
 drivers/clk/samsung/clk-exynos4.c    |   48 +++++++++++++++++-----------------
 drivers/clk/samsung/clk-exynos5250.c |   19 ++++++++-----
 drivers/clk/samsung/clk-exynos5420.c |   27 ++++++++++++------
 3 files changed, 53 insertions(+), 41 deletions(-)

drivers/clk/samsung/clk-exynos4.c +24 ~~-24~~

index 9af5767..3731fc7 100644
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
 	MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
 	MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
-	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
+	MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0,
+			CLK_MUX_READ_ONLY),
 	MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
 	MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
 	MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),

@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
 			CLKOUT_CMU_RIGHTBUS, 8, 6),
 
-	DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
-	DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
-	DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
-	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
-	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
-	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
-	DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
-	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
-	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+	DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_periph", "div_core2", DIV_CPU0, 12, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_atb", "mout_core", DIV_CPU0, 16, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
 
 	DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),

@@ -769,7 +779,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
 	DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
 	DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
-	DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+	DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
 			CLK_SET_RATE_PARENT, 0),
 	DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,

@@ -1186,17 +1197,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 		0),
 };
 
-static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
 	ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
 	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
 	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
-};
-
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
-	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
-};
-
-static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
 	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
 };

@@ -1463,8 +1467,6 @@ static void __init exynos4_clk_init(struct device_node *np,
 			ARRAY_SIZE(exynos4210_div_clks));
 		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
 			ARRAY_SIZE(exynos4210_gate_clks));
-		samsung_clk_register_alias(ctx, exynos4210_aliases,
-			ARRAY_SIZE(exynos4210_aliases));
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4210_fixed_factor_clks,
 			ARRAY_SIZE(exynos4210_fixed_factor_clks));

@@ -1486,9 +1488,6 @@ static void __init exynos4_clk_init(struct device_node *np,
 			ARRAY_SIZE(exynos4x12_fixed_factor_clks));
 	}
 
-	samsung_clk_register_alias(ctx, exynos4_aliases,
-			ARRAY_SIZE(exynos4_aliases));
-
 	exynos4_core_down_clock(soc);
 	exynos4_clk_sleep_init();

@@ -1499,6 +1498,7 @@ static void __init exynos4_clk_init(struct device_node *np,
 		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
 		_get_rate("sclk_apll"),	_get_rate("sclk_mpll"),
 		_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
+		exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
 		_get_rate("div_core2"));
 }

drivers/clk/samsung/clk-exynos5250.c +11 -8

index e19e365..1d958f1 100644
@@ -291,14 +291,14 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	/*
 	 * CMU_CPU
 	 */
-	MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
-					CLK_SET_RATE_PARENT, 0, "mout_apll"),
-	MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, CLK_MUX_READ_ONLY),
 
 	/*
 	 * CMU_CORE
 	 */
-	MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
+	MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
 
 	/*
 	 * CMU_TOP

@@ -380,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
 	/*
 	 * CMU_CPU
 	 */
-	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
-	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+	DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	/*
 	 * CMU_TOP

@@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
 	samsung_clk_of_add_provider(np, ctx);
 
 	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
-			_get_rate("div_arm2"));
+			_get_rate("armclk"));
 }
 CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);

drivers/clk/samsung/clk-exynos5420.c +18 -9

index d7ef36a..fcf365d 100644
@@ -617,10 +617,14 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 	MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 
-	MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
-	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
-	MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
-	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+				CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0,
+				CLK_MUX_READ_ONLY),
+	MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+				CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, 0,
+				CLK_MUX_READ_ONLY),
 
 	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 	MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),

@@ -776,11 +780,16 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 };
 
 static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
-	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
-	DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
-	DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
-	DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
+	DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "armclk2", "div_arm", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
 	DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),

Signature · 1 line

1.6.6.rc2

Viresh Kumar

maintainer

2014-10-20 11:32 UTC #7 lore raw

PATCH v11 5/6 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support

In reply to Thomas Abraham

Quoted 9 lines · Thomas Abraham

Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed.
Cc Bartlomiej Zolnierkiewicz <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Acked-by Viresh Kumar <[email protected]>
Tested-by Javier Martinez Canillas <[email protected]>
Tested-by Chander Kashyap <[email protected]>

Quoted 4 lines

---
 drivers/cpufreq/Kconfig.arm |   22 ----------------------
 drivers/cpufreq/Makefile    |    2 --
 2 files changed, 0 insertions(+), 24 deletions(-)

Looks like you forgot removing drivers ;)

Thomas Abraham

2014-10-20 11:38 UTC #8 lore raw

PATCH v11 5/6 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support

Quoted 15 lines · Viresh Kumar

Quoted 9 lines · Thomas Abraham
Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed.
Cc Bartlomiej Zolnierkiewicz <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Acked-by Viresh Kumar <[email protected]>
Tested-by Javier Martinez Canillas <[email protected]>
Tested-by Chander Kashyap <[email protected]>
Quoted 4 lines
---
 drivers/cpufreq/Kconfig.arm |   22 ----------------------
 drivers/cpufreq/Makefile    |    2 --
 2 files changed, 0 insertions(+), 24 deletions(-)

Quoted 1 line

Looks like you forgot removing drivers ;)

Sorry, missed it while doing the rebase. I will fix and send an updated patch.

Thanks,
Thomas.

Quoted 4 lines

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Thomas Abraham

author

2014-10-20 11:58 UTC #9 lore raw

PATCH v11 5/6 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support

Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed.

Cc Bartlomiej Zolnierkiewicz <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Viresh Kumar <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Tested-by Chander Kashyap <[email protected]>

---
 drivers/cpufreq/Kconfig.arm          |   22 ----
 drivers/cpufreq/Makefile             |    2 -
 drivers/cpufreq/exynos4210-cpufreq.c |  184 -----------------------------
 drivers/cpufreq/exynos5250-cpufreq.c |  210 ----------------------------------
 4 files changed, 0 insertions(+), 418 deletions(-)
 delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
 delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c

drivers/cpufreq/Kconfig.arm +0 ~~-22~~

index 83a75dc..701f5ca 100644
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
 config ARM_EXYNOS_CPUFREQ
 	bool
 
-config ARM_EXYNOS4210_CPUFREQ
-	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS4210
-	  SoC (S5PV310 or S5PC210).
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS4X12_CPUFREQ
 	bool "SAMSUNG EXYNOS4x12"
 	depends on SOC_EXYNOS4212 || SOC_EXYNOS4412

@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
 
 	  If in doubt, say N.
 
-config ARM_EXYNOS5250_CPUFREQ
-	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250
-	default y
-	select ARM_EXYNOS_CPUFREQ
-	help
-	  This adds the CPUFreq driver for Samsung EXYNOS5250
-	  SoC.
-
-	  If in doubt, say N.
-
 config ARM_EXYNOS5440_CPUFREQ
 	bool "SAMSUNG EXYNOS5440"
 	depends on SOC_EXYNOS5440

drivers/cpufreq/Makefile +0 -2

index 40c53dc..74e55f9 100644
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ)		+= arm_big_little_dt.o
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci-cpufreq.o
 obj-$(CONFIG_UX500_SOC_DB8500)		+= dbx500-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)	+= exynos5440-cpufreq.o
 obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ)	+= highbank-cpufreq.o
 obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o

drivers/cpufreq/exynos4210-cpufreq.c deleted +0 ~~-184~~

184 lines not on this page · raw message

drivers/cpufreq/exynos5250-cpufreq.c deleted +0 ~~-210~~

210 lines not on this page · raw message

Signature · 1 line

1.6.6.rc2

Amit Kucheria

2014-11-12 06:03 UTC #10 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

In reply to Thomas Abraham

Hi Thomas,

Quoted 20 lines · Thomas Abraham

The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.
Suggested-by Tomasz Figa <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Reviewed-by Tomasz Figa <[email protected]>
Tested-by Javier Martinez Canillas <[email protected]>
Tested-by Chander Kashyap <[email protected]>
---
 arch/arm/mach-exynos/exynos.c |   24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/exynos.c +0 -0
index 6b283eb..a1be294 100644

arch/arm/mach-exynos/exynos.c static void __init exynos_init_irq(void) · line 286

Quoted 5 lines

arch/arm/mach-exynos/exynos.c +2 -0

@@ -282,6 +282,28 @@ static void __init exynos_init_irq(void)
        exynos_map_pmu();
 }
 
+static const struct of_device_id exynos_cpufreq_matches[] = {
+       { .compatible = "samsung,exynos5420", .data = "arm-bL-cpufreq-dt" },

While you're at it, can you add this to so we don't have to patch kernels for the Chromebook2 and Odroid-XU3?

      { .compatible = "samsung,exynos5422", .data = "arm-bL-cpufreq-dt" },
      { .compatible = "samsung,exynos5800", .data = "arm-bL-cpufreq-dt" },

Quoted 4 lines

arch/arm/mach-exynos/exynos.c +4 -0

+       { .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+       { .compatible = "samsung,exynos4210", .data = "cpufreq-dt" },
+       { .compatible = "samsung,exynos5440", .data = "exynos5440-cpufreq" },
+       { /* sentinel */ }

Thomas Abraham

2014-11-21 14:32 UTC #11 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

Hi Amit,

Quoted 26 lines · Amit Kucheria

Hi Thomas,
Quoted 23 lines · Thomas Abraham
The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.
Suggested-by Tomasz Figa <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Reviewed-by Tomasz Figa <[email protected]>
Tested-by Javier Martinez Canillas <[email protected]>
Tested-by Chander Kashyap <[email protected]>
---
 arch/arm/mach-exynos/exynos.c |   24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/exynos.c +0 -0
index 6b283eb..a1be294 100644
@@ -282,6 +282,28 @@ static void __init exynos_init_irq(void)
        exynos_map_pmu();
 }
 

Quoted 9 lines

arch/arm/mach-exynos/exynos.c static void __init exynos_init_irq(void) · line 286
Quoted 2 lines
arch/arm/mach-exynos/exynos.c +2 -0
+static const struct of_device_id exynos_cpufreq_matches[] = {
+       { .compatible = "samsung,exynos5420", .data = "arm-bL-cpufreq-dt" },
While you're at it, can you add this to so we don't have to patch kernels for the Chromebook2 and Odroid-XU3?
      { .compatible = "samsung,exynos5422", .data = "arm-bL-cpufreq-dt" },
      { .compatible = "samsung,exynos5800", .data = "arm-bL-cpufreq-dt" },

Okay, I this has been included in the updated patches [1]

[1] http://www.spinics.net/lists/arm-kernel/msg380011.html

Thanks,
Thomas.

Quoted 10 lines

arch/arm/mach-exynos/exynos.c static void __init exynos_init_irq(void) · line 290
Quoted 5 lines
arch/arm/mach-exynos/exynos.c +4 -0
+       { .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+       { .compatible = "samsung,exynos4210", .data = "cpufreq-dt" },
+       { .compatible = "samsung,exynos5440", .data = "exynos5440-cpufreq" },
+       { /* sentinel */ }
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Kevin Hilman

2014-11-19 17:30 UTC #12 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

In reply to Thomas Abraham

Hi Thomas,

Quoted 11 lines · Thomas Abraham

The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.
Suggested-by Tomasz Figa <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Reviewed-by Tomasz Figa <[email protected]>
Tested-by Javier Martinez Canillas <[email protected]>
Tested-by Chander Kashyap <[email protected]>

What's the status of the exynos5 CPUfreq support for upstream? This was pretty broadly reviewed and tested, but I still don't see this either in linux-next or Kukjin's for-next.

Kevin

Thomas Abraham

2014-11-21 14:31 UTC #13 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

Hi Kevin,

Quoted 15 lines · Kevin Hilman

Hi Thomas,
Quoted 11 lines · Thomas Abraham
The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.
Suggested-by Tomasz Figa <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Reviewed-by Tomasz Figa <[email protected]>
Tested-by Javier Martinez Canillas <[email protected]>
Tested-by Chander Kashyap <[email protected]>

Quoted 3 lines

What's the status of the exynos5 CPUfreq support for upstream? This was pretty broadly reviewed and tested, but I still don't see this either in linux-next or Kukjin's for-next.

The rebased version of the patches have been posted [1]. My apologies for the delay in following up on this patch series.

Thanks,
Thomas.

[1] http://www.spinics.net/lists/arm-kernel/msg380011.html

Quoted 7 lines

Kevin
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Sudeep Holla

2014-11-19 19:28 UTC #14 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

In reply to Thomas Abraham

Quoted 20 lines · Thomas Abraham

The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.
Suggested-by Tomasz Figa <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
Reviewed-by Tomasz Figa <[email protected]>
Tested-by Javier Martinez Canillas <[email protected]>
Tested-by Chander Kashyap <[email protected]>
---
  arch/arm/mach-exynos/exynos.c |   24 +++++++++++++++++++++++-
  1 files changed, 23 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/exynos.c +0 -0
index 6b283eb..a1be294 100644

arch/arm/mach-exynos/exynos.c static void __init exynos_init_irq(void) · line 286

Quoted 5 lines

arch/arm/mach-exynos/exynos.c +2 -0

@@ -282,6 +282,28 @@ static void __init exynos_init_irq(void)
  	exynos_map_pmu();
  }
 
+static const struct of_device_id exynos_cpufreq_matches[] = {
+	{ .compatible = "samsung,exynos5420", .data = "arm-bL-cpufreq-dt" },

Sorry for raising this issue always with Exynos cpufreq drivers. IMO the bindings for "arm-bL-cpufreq-dt" is broken. Currently no one is using it and it's better to fix it before we have a real user of it.

If you look at the binding document for it[1], it has a fixme which shouldn't have been there at first place. It assumes the ordering of CPU's specified in the DT and the logical index allocation to them.

It even breaks for hotplug especially if you hotplug-in back in different order. We can work around that probably, but it's better to fix the binding. I failed to grab much attention in my previous attempts to address this[2]. Viresh also started a discussion more recently[3].

Regards,
Sudeep

[1] Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
[2] http://www.spinics.net/lists/arm-kernel/msg303977.html
[3] https://lkml.org/lkml/2014/6/25/152

Viresh Kumar

maintainer

2014-11-20 03:48 UTC #15 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

Oh, you are still alive? I thought you were about to get married :) Just kidding !!

Quoted 3 lines · Sudeep Holla

Sorry for raising this issue always with Exynos cpufreq drivers. IMO the bindings for "arm-bL-cpufreq-dt" is broken. Currently no one is using it and it's better to fix it before we have a real user of it.

Hmm, yeah if we can. I haven't found a easy way to go ahead and then got caught in other activities.

Quoted 3 lines

If you look at the binding document for it[1], it has a fixme which shouldn't have been there at first place. It assumes the ordering of CPU's specified in the DT and the logical index allocation to them.

Ok, I believe the FIXME is a bit outdated. From the code I can see only this limitation.

- For every cluster, the cpu which boots up first should carry the OPPs. Otherwise there is no restriction on ordering of CPUs.

- I believe CPUs boot in the order they are present in DT except for the boot CPU. So, the first node for every cluster should have it.

Correct ? Then we can update the fixme.

Quoted 2 lines

It even breaks for hotplug especially if you hotplug-in back in different order.

Hmm, I never thought about it. But yes the CPU with the OPPs should be the first one to come back.

Quoted 3 lines

We can work around that probably, but it's better to
fix the binding. I failed to grab much attention in my previous attempts to address this[2]. Viresh also started a discussion more recently[3].

They are just stuck and went nowhere :(

Sudeep Holla

2014-11-24 13:44 UTC #16 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

Quoted 11 lines · Viresh Kumar

Oh, you are still alive? I thought you were about to get married :) Just kidding !!
Quoted 3 lines · Sudeep Holla
Sorry for raising this issue always with Exynos cpufreq drivers. IMO the bindings for "arm-bL-cpufreq-dt" is broken. Currently no one is using it and it's better to fix it before we have a real user of it.
Hmm, yeah if we can. I haven't found a easy way to go ahead and then got caught in other activities.

Agreed, it's not easy but needs to be fixed :)

Quoted 10 lines

Quoted 3 lines
If you look at the binding document for it[1], it has a fixme which shouldn't have been there at first place. It assumes the ordering of CPU's specified in the DT and the logical index allocation to them.
Ok, I believe the FIXME is a bit outdated. From the code I can see only this limitation.
- For every cluster, the cpu which boots up first should carry the OPPs. Otherwise there is no restriction on ordering of CPUs.

Not entirely true, it assuming the fact that the logical index provided by the OS is completely based on the ordering in the DT.

Quoted 5 lines

- I believe CPUs boot in the order they are present in DT except for the boot CPU. So, the first node for every cluster should have it.
Correct ? Then we can update the fixme.

No, I disagree as you trying to implicitly depend on the logic Linux uses to assign logical index. It can be changed any time, and depending on it might break things in future which can't be fixed easily later
especially if it's DT related.

Quoted 6 lines

Quoted 2 lines
It even breaks for hotplug especially if you hotplug-in back in different order.
Hmm, I never thought about it. But yes the CPU with the OPPs should be the first one to come back.

How can you assume that ? I can write a simple test which hot-plugs out all the CPUs in the (esp. multi-cluster) system in ascending order of logical index and hot-plug back in descending order. Then the above logic fails.

Quoted 6 lines

Quoted 3 lines
We can work around that probably, but it's better to
fix the binding. I failed to grab much attention in my previous attempts to address this[2]. Viresh also started a discussion more recently[3].
They are just stuck and went nowhere :(

The platforms needing it have to get involved in such discussions to make any progress.

Regards,
Sudeep

Viresh Kumar

maintainer

2014-11-25 11:02 UTC #17 lore raw

PATCH v11 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420

Quoted 11 lines · Sudeep Holla

Quoted 5 lines · Viresh Kumar
- I believe CPUs boot in the order they are present in DT except for the boot CPU. So, the first node for every cluster should have it.
Correct ? Then we can update the fixme.
No, I disagree as you trying to implicitly depend on the logic Linux uses to assign logical index. It can be changed any time, and depending on it might break things in future which can't be fixed easily later especially if it's DT related.

Yeah, correct.

Quoted 8 lines

Quoted 3 lines
Hmm, I never thought about it. But yes the CPU with the OPPs should be the first one to come back.
How can you assume that ? I can write a simple test which hot-plugs out all the CPUs in the (esp. multi-cluster) system in ascending order of logical index and hot-plug back in descending order. Then the above logic fails.

What I said is: Yes the CPU with the OPPs should be the first one to come back, if this has to work correctly. Otherwise it will break..

And you repeated the same :)

Quoted 2 lines

The platforms needing it have to get involved in such discussions to make any progress.

Yes there were people involved. I hope I cc'd you as well...

Tomasz Figa

2014-10-20 11:35 UTC #18 lore raw

v11 cover cpufreq: use generic cpufreq drivers for exynos platforms

In reply to Thomas Abraham

Quoted 8 lines · Thomas Abraham

Changes since v10:
- Rebased on top of v3.18-rc1
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver.

Quoted 5 lines

This patch series is based and tested on v3.18-rc1 and depends on the patch
- "clk: exynos4: remove duplicate div_core2 divider clock instantiation"
(http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg34859.html) This patch has been merged in "arm-soc/samsung/dt3" branch of arm-soc tree.

That patch actually went through clock tree, but it doesn't matter, because AFAIK all the dependencies for this series are already in 3.18-rc1. I'll try to apply it in next days

Best regards,
Tomasz

Thomas Abraham

2014-10-20 11:48 UTC #19 lore raw

v11 cover cpufreq: use generic cpufreq drivers for exynos platforms

Hi Tomasz,

Quoted 15 lines · Tomasz Figa

Quoted 8 lines · Thomas Abraham
Changes since v10:
- Rebased on top of v3.18-rc1
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver.
Quoted 5 lines
This patch series is based and tested on v3.18-rc1 and depends on the patch
- "clk: exynos4: remove duplicate div_core2 divider clock instantiation"
(http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg34859.html) This patch has been merged in "arm-soc/samsung/dt3" branch of arm-soc tree.

Quoted 3 lines

That patch actually went through clock tree, but it doesn't matter, because AFAIK all the dependencies for this series are already in 3.18-rc1. I'll try to apply it in next days

Thanks. The patch "clk: exynos4: remove duplicate div_core2 divider clock instantiation" is not available in 3.18-rc1. So for testing, I picked this patch from samsung/dt3 branch from arm-soc tree.

Regards,
Thomas.

Quoted 7 lines

Best regards,
Tomasz
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Tomasz Figa

2014-10-20 14:18 UTC #20 lore raw

v11 cover cpufreq: use generic cpufreq drivers for exynos platforms

Quoted 18 lines · Thomas Abraham

Hi Tomasz,
Quoted 15 lines · Tomasz Figa
Quoted 13 lines · Thomas Abraham
Changes since v10:
- Rebased on top of v3.18-rc1
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver.
This patch series is based and tested on v3.18-rc1 and depends on the patch
- "clk: exynos4: remove duplicate div_core2 divider clock instantiation"
(http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg34859.html) This patch has been merged in "arm-soc/samsung/dt3" branch of arm-soc tree.

Quoted 7 lines

Quoted 3 lines
That patch actually went through clock tree, but it doesn't matter, because AFAIK all the dependencies for this series are already in 3.18-rc1. I'll try to apply it in next days
Thanks. The patch "clk: exynos4: remove duplicate div_core2 divider clock instantiation" is not available in 3.18-rc1. So for testing, I picked this patch from samsung/dt3 branch from arm-soc tree.

Hmm? I can see it there:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/log/drivers/clk/samsung?id=v3.18-rc1

Best regards,
Tomasz