Enable driver model for GPIOs on Tegra and Exynos

The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v9: None
Changes in v8:
- Add missing special case reg property for exynos5420 GPX0

Changes in v7: None
Changes in v6:
- Move U-Boot changes into their own file
- Use exynos54xx everywhere instead of exynos5420

Changes in v5: None
Changes in v4: None

  arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 27 ++++++++++++++++++
  arch/arm/dts/exynos4210-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 46 ++++++++++++++++++++++++++++++
  arch/arm/dts/exynos4x12-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos5250-pinctrl-uboot.dtsi | 40 ++++++++++++++++++++++++++
  arch/arm/dts/exynos5250-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi | 40 ++++++++++++++++++++++++++
  arch/arm/dts/exynos54xx-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos54xx.dtsi               |  1 +
  9 files changed, 162 insertions(+)

create mode 100644 arch/arm/dts/exynos4210-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos5250-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi

arch/arm/dts/exynos4210-pinctrl.dtsi +2 -0

index bda17f7..87f162b 100644
@@ -14,6 +14,8 @@
   * published by the Free Software Foundation.
  */
 
+#include "exynos4210-pinctrl-uboot.dtsi"
+
  / {
  	pinctrl at 11400000 {
  		gpa0: gpa0 {

arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi new file +0 -0

new file mode 100644
index 0000000..c02796d

Hello Simon,

Quoted 40 lines · Simon Glass

The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v9: None
Changes in v8:
- Add missing special case reg property for exynos5420 GPX0

Changes in v7: None
Changes in v6:
- Move U-Boot changes into their own file
- Use exynos54xx everywhere instead of exynos5420

Changes in v5: None
Changes in v4: None

  arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 27 ++++++++++++++++++
  arch/arm/dts/exynos4210-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 46
++++++++++++++++++++++++++++++
  arch/arm/dts/exynos4x12-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos5250-pinctrl-uboot.dtsi | 40
++++++++++++++++++++++++++
  arch/arm/dts/exynos5250-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi | 40
++++++++++++++++++++++++++
  arch/arm/dts/exynos54xx-pinctrl.dtsi       |  2 ++
  arch/arm/dts/exynos54xx.dtsi               |  1 +
  9 files changed, 162 insertions(+)

create mode 100644 arch/arm/dts/exynos4210-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos5250-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi

... snip ...

Quoted 21 lines

arch/arm/dts/exynos4210-pinctrl.dtsi +2 -0

index bda17f7..87f162b 100644
@@ -14,6 +14,8 @@
   * published by the Free Software Foundation.
  */
 
+#include "exynos4210-pinctrl-uboot.dtsi"
+
  / {
        pinctrl at 11400000 {
                gpa0: gpa0 {

arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi new file +0 -0

new file mode 100644
index 0000000..c02796d

arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi line 10

Quoted 10 lines

arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi new file +10 -0

@@ -0,0 +1,46 @@
+/*
+ * U-Boot additions to enable a generic Exynos GPIO driver
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/{
+       pinctrl_0: pinctrl at 11400000 {
+               #address-cells = <1>;
+               #size-cells = <0>;

The first issue with Exynos GPIO driver starts here. If you put pinctrl* node data in a separated file, then the order of nodes in dtb is changed. So for the pinctrl 0, the first subnode is gpf0, instead of gpa0. And the same is for other pinctrls.

This means that function gpio_exynos_bind(), which expects proper subnodes order assign wrong base addresses to some GPIO pins.

Move "reg" properties into arch/arm/dts/exynos4x12-pinctrl.dtsi fixes this issue. But in this case, the file *-pinctrl-uboot.dtsi is quite useless - since the cells size can be moved to pinctrl.dtsi too.

This probably will touch all *pinctrl-uboot.dtsi files.

Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v9:
- Add missing compatible strings from exynos_gpio_ids[]

Changes in v8:
- Enable driver model for smdkc100 and s5p_goni separately

Changes in v7:
- Bring in patches from the SPI series to move post-reloc DM init earlier

Changes in v6: None
Changes in v5:
- Remove RFC label now that build errors are fixed
- Tidy up and update cover letter message
- Avoid reordering functions

Changes in v4:
- Add patches for exynos GPIO support

  drivers/gpio/s5p_gpio.c         | 424 +++++++++++++++++++++++++++-------------
  include/configs/exynos-common.h |   4 +
  include/configs/s5p_goni.h      |   3 +
  include/configs/smdkc100.h      |   3 +
  4 files changed, 298 insertions(+), 136 deletions(-)

drivers/gpio/s5p_gpio.c +0 -0

index 99f2dd8..13d74eb 100644
@@ -6,8 +6,15 @@
   */
 

drivers/gpio/s5p_gpio.c +10 -0

+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */
+static int gpio_exynos_bind(struct udevice *parent)
+{
+	struct exynos_gpio_platdata *plat = parent->platdata;
+	struct s5p_gpio_bank *bank, *base;
+	const void *blob = gd->fdt_blob;
+	int node;

drivers/gpio/s5p_gpio.c +15 -0

+		reg = fdtdec_get_addr(blob, node, "reg");
+		if (reg != FDT_ADDR_T_NONE)
+			bank = (struct s5p_gpio_bank *)((ulong)base + reg);
+		plat->bank = bank;
+		plat->bank_name = fdt_get_name(blob, node, NULL);
+		debug("dev at %p: %s\n", bank, plat->bank_name);
+
+		ret = device_bind(parent, parent->driver,
+					plat->bank_name, plat, -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;

Hello Simon,

Quoted 40 lines · Simon Glass

Convert the exynos GPIO driver to driver model. This implements the generic
GPIO interface but not the extra Exynos-specific functions.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v9:
- Add missing compatible strings from exynos_gpio_ids[]

Changes in v8:
- Enable driver model for smdkc100 and s5p_goni separately

Changes in v7:
- Bring in patches from the SPI series to move post-reloc DM init earlier

Changes in v6: None
Changes in v5:
- Remove RFC label now that build errors are fixed
- Tidy up and update cover letter message
- Avoid reordering functions

Changes in v4:
- Add patches for exynos GPIO support

  drivers/gpio/s5p_gpio.c         | 424
+++++++++++++++++++++++++++-------------
  include/configs/exynos-common.h |   4 +
  include/configs/s5p_goni.h      |   3 +
  include/configs/smdkc100.h      |   3 +
  4 files changed, 298 insertions(+), 136 deletions(-)

drivers/gpio/s5p_gpio.c +0 -0

index 99f2dd8..13d74eb 100644
@@ -6,8 +6,15 @@
   */
 

..snip..

Quoted 20 lines

drivers/gpio/s5p_gpio.c +17 -0

+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */
+static int gpio_exynos_bind(struct udevice *parent)
+{
+       struct exynos_gpio_platdata *plat = parent->platdata;
+       struct s5p_gpio_bank *bank, *base;
+       const void *blob = gd->fdt_blob;
+       int node;
+
+       /* If this is a child device, there is nothing to do here */
+       if (plat)
+               return 0;
+
+       base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+                                                  parent->of_offset,

"reg");
+ for (node = fdt_first_subnode(blob, parent->of_offset), bank =
base;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 424

Quoted 2 lines

drivers/gpio/s5p_gpio.c +2 -0

+            node > 0;
+            node = fdt_next_subnode(blob, node), bank++) {

Here (bank++) you assume, that order of subnodes of each pinctrl is the same like in dts file - as I wrote in comment to patch 04 - it isn't.

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 434

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+               struct exynos_gpio_platdata *plat;
+               struct udevice *dev;
+               fdt_addr_t reg;
+               int ret;
+
+               if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+                       continue;
+               plat = calloc(1, sizeof(*plat));
+               if (!plat)
+                       return -ENOMEM;

Some parts of GPIO banks, for which "reg" can be found are prober.

Quoted 16 lines

drivers/gpio/s5p_gpio.c +3 -0

+               reg = fdtdec_get_addr(blob, node, "reg");
+               if (reg != FDT_ADDR_T_NONE)
+                       bank = (struct s5p_gpio_bank *)((ulong)base +

reg);

drivers/gpio/s5p_gpio.c +12 -0

+               plat->bank = bank;
+               plat->bank_name = fdt_get_name(blob, node, NULL);
+               debug("dev at %p: %s\n", bank, plat->bank_name);
+
+               ret = device_bind(parent, parent->driver,
+                                       plat->bank_name, plat, -1, &dev);
+               if (ret)
+                       return ret;
+               dev->of_offset = parent->of_offset;
+       }
+
+       return 0;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 459

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+       { .compatible = "samsung,s5pc100-pinctrl" },
+       { .compatible = "samsung,s5pc110-pinctrl" },
+       { .compatible = "samsung,exynos4210-pinctrl" },
+       { .compatible = "samsung,exynos4x12-pinctrl" },
+       { .compatible = "samsung,exynos5250-pinctrl" },
+       { .compatible = "samsung,exynos5420-pinctrl" },
+       { }

... snip ...

And this is not the end of issues:)

Unfortunately Exynos4xxx has a gaps in GPIO bank address space, and the big gpio enum lists includes that here:
arch/arm/include/asm/arch-exynos/gpio.h

This works for Exynos5, because it's enum list is linear.

And the driver gpio-uclass.c - assumes that the gpio numbers are linear. When I removed the gaps in enum for 4x12 -then gpio is mapped good.

And after remove the enum gaps, it also requires fitting the gpios in dts files, e.g. cd-gpio, pwr-gpios for sdhci host.

Sorry for such late reply in v9 but, before it seems working fine - I didn't try to check the sd card before.

I hope that after that fixes, everything will work fine:)

Hi,

Quoted 136 lines · Przemyslaw Marczak

Hello Simon,

Quoted 40 lines · Simon Glass

Convert the exynos GPIO driver to driver model. This implements the generic
GPIO interface but not the extra Exynos-specific functions.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v9:
- Add missing compatible strings from exynos_gpio_ids[]

Changes in v8:
- Enable driver model for smdkc100 and s5p_goni separately

Changes in v7:
- Bring in patches from the SPI series to move post-reloc DM init earlier

Changes in v6: None
Changes in v5:
- Remove RFC label now that build errors are fixed
- Tidy up and update cover letter message
- Avoid reordering functions

Changes in v4:
- Add patches for exynos GPIO support

   drivers/gpio/s5p_gpio.c         | 424
+++++++++++++++++++++++++++-------------
   include/configs/exynos-common.h |   4 +
   include/configs/s5p_goni.h      |   3 +
   include/configs/smdkc100.h      |   3 +
   4 files changed, 298 insertions(+), 136 deletions(-)

drivers/gpio/s5p_gpio.c +0 -0

index 99f2dd8..13d74eb 100644
@@ -6,8 +6,15 @@
    */
 

..snip..

Quoted 20 lines

drivers/gpio/s5p_gpio.c +17 -0

+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */
+static int gpio_exynos_bind(struct udevice *parent)
+{
+       struct exynos_gpio_platdata *plat = parent->platdata;
+       struct s5p_gpio_bank *bank, *base;
+       const void *blob = gd->fdt_blob;
+       int node;
+
+       /* If this is a child device, there is nothing to do here */
+       if (plat)
+               return 0;
+
+       base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+                                                  parent->of_offset,

"reg");
+ for (node = fdt_first_subnode(blob, parent->of_offset), bank =
base;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 424

Quoted 2 lines

drivers/gpio/s5p_gpio.c +2 -0

+            node > 0;
+            node = fdt_next_subnode(blob, node), bank++) {

Here (bank++) you assume, that order of subnodes of each pinctrl is the same like in dts file - as I wrote in comment to patch 04 - it isn't.

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 434

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+               struct exynos_gpio_platdata *plat;
+               struct udevice *dev;
+               fdt_addr_t reg;
+               int ret;
+
+               if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+                       continue;
+               plat = calloc(1, sizeof(*plat));
+               if (!plat)
+                       return -ENOMEM;

Some parts of GPIO banks, for which "reg" can be found are prober.

Quoted 16 lines

drivers/gpio/s5p_gpio.c +3 -0

+               reg = fdtdec_get_addr(blob, node, "reg");
+               if (reg != FDT_ADDR_T_NONE)
+                       bank = (struct s5p_gpio_bank *)((ulong)base +

reg);

drivers/gpio/s5p_gpio.c +12 -0

+               plat->bank = bank;
+               plat->bank_name = fdt_get_name(blob, node, NULL);
+               debug("dev at %p: %s\n", bank, plat->bank_name);
+
+               ret = device_bind(parent, parent->driver,
+                                       plat->bank_name, plat, -1, &dev);
+               if (ret)
+                       return ret;
+               dev->of_offset = parent->of_offset;
+       }
+
+       return 0;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 459

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+       { .compatible = "samsung,s5pc100-pinctrl" },
+       { .compatible = "samsung,s5pc110-pinctrl" },
+       { .compatible = "samsung,exynos4210-pinctrl" },
+       { .compatible = "samsung,exynos4x12-pinctrl" },
+       { .compatible = "samsung,exynos5250-pinctrl" },
+       { .compatible = "samsung,exynos5420-pinctrl" },
+       { }

... snip ...

And this is not the end of issues:)

Unfortunately Exynos4xxx has a gaps in GPIO bank address space, and the big gpio enum lists includes that here:
arch/arm/include/asm/arch-exynos/gpio.h

This works for Exynos5, because it's enum list is linear.

And the driver gpio-uclass.c - assumes that the gpio numbers are linear. When I removed the gaps in enum for 4x12 -then gpio is mapped good.

And after remove the enum gaps, it also requires fitting the gpios in dts files, e.g. cd-gpio, pwr-gpios for sdhci host.

Sorry for such late reply in v9 but, before it seems working fine - I didn't try to check the sd card before.

Quoted 1 line

I hope that after that fixes, everything will work fine:)

Thanks very much for testing this. As mentioned on the other patch, please try u-boot-dm/next and see how things look.

Regards,
Simon

Hello,

Quoted 152 lines · Simon Glass

Hi,

Quoted 139 lines · Przemyslaw Marczak

Hello Simon,

Quoted 41 lines · Simon Glass

Convert the exynos GPIO driver to driver model. This implements the generic
GPIO interface but not the extra Exynos-specific functions.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v9:
- Add missing compatible strings from exynos_gpio_ids[]

Changes in v8:
- Enable driver model for smdkc100 and s5p_goni separately

Changes in v7:
- Bring in patches from the SPI series to move post-reloc DM init earlier

Changes in v6: None
Changes in v5:
- Remove RFC label now that build errors are fixed
- Tidy up and update cover letter message
- Avoid reordering functions

Changes in v4:
- Add patches for exynos GPIO support

   drivers/gpio/s5p_gpio.c         | 424
+++++++++++++++++++++++++++-------------
   include/configs/exynos-common.h |   4 +
   include/configs/s5p_goni.h      |   3 +
   include/configs/smdkc100.h      |   3 +
   4 files changed, 298 insertions(+), 136 deletions(-)

drivers/gpio/s5p_gpio.c +0 -0

index 99f2dd8..13d74eb 100644
@@ -6,8 +6,15 @@
    */
 

..snip..

Quoted 21 lines

+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */

drivers/gpio/s5p_gpio.c +13 -0

+static int gpio_exynos_bind(struct udevice *parent)
+{
+       struct exynos_gpio_platdata *plat = parent->platdata;
+       struct s5p_gpio_bank *bank, *base;
+       const void *blob = gd->fdt_blob;
+       int node;
+
+       /* If this is a child device, there is nothing to do here */
+       if (plat)
+               return 0;
+
+       base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+                                                  parent->of_offset,

"reg");
+ for (node = fdt_first_subnode(blob, parent->of_offset), bank =
base;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 424

Quoted 2 lines

drivers/gpio/s5p_gpio.c +2 -0

+            node > 0;
+            node = fdt_next_subnode(blob, node), bank++) {

Here (bank++) you assume, that order of subnodes of each pinctrl is the same
like in dts file - as I wrote in comment to patch 04 - it isn't.

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 434

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+               struct exynos_gpio_platdata *plat;
+               struct udevice *dev;
+               fdt_addr_t reg;
+               int ret;
+
+               if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+                       continue;
+               plat = calloc(1, sizeof(*plat));
+               if (!plat)
+                       return -ENOMEM;

Some parts of GPIO banks, for which "reg" can be found are prober.

Quoted 17 lines

drivers/gpio/s5p_gpio.c +3 -0

+               reg = fdtdec_get_addr(blob, node, "reg");
+               if (reg != FDT_ADDR_T_NONE)
+                       bank = (struct s5p_gpio_bank *)((ulong)base +

reg);

drivers/gpio/s5p_gpio.c +6 -0

+               plat->bank = bank;
+               plat->bank_name = fdt_get_name(blob, node, NULL);
+               debug("dev at %p: %s\n", bank, plat->bank_name);
+
+               ret = device_bind(parent, parent->driver,
+                                       plat->bank_name, plat, -1,

&dev);

drivers/gpio/s5p_gpio.c +6 -0

+               if (ret)
+                       return ret;
+               dev->of_offset = parent->of_offset;
+       }
+
+       return 0;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 459

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+       { .compatible = "samsung,s5pc100-pinctrl" },
+       { .compatible = "samsung,s5pc110-pinctrl" },
+       { .compatible = "samsung,exynos4210-pinctrl" },
+       { .compatible = "samsung,exynos4x12-pinctrl" },
+       { .compatible = "samsung,exynos5250-pinctrl" },
+       { .compatible = "samsung,exynos5420-pinctrl" },
+       { }

... snip ...

And this is not the end of issues:)

Unfortunately Exynos4xxx has a gaps in GPIO bank address space, and the big
gpio enum lists includes that here:
arch/arm/include/asm/arch-exynos/gpio.h

This works for Exynos5, because it's enum list is linear.

And the driver gpio-uclass.c - assumes that the gpio numbers are linear. When I removed the gaps in enum for 4x12 -then gpio is mapped good.

And after remove the enum gaps, it also requires fitting the gpios in dts
files, e.g. cd-gpio, pwr-gpios for sdhci host.

Quoted 5 lines

Sorry for such late reply in v9 but, before it seems working fine - I didn't
try to check the sd card before.

I hope that after that fixes, everything will work fine:)

Thanks very much for testing this. As mentioned on the other patch, please try u-boot-dm/next and see how things look.

Quoted 3 lines

Regards,
Simon

No problem, it's also important for me. I will check the "next" in a few minutes.

Regards,

Hello again,

Quoted 163 lines · Przemyslaw Marczak

Hello,

Quoted 159 lines · Simon Glass

Hi,

Quoted 144 lines · Przemyslaw Marczak

Hello Simon,

Quoted 42 lines · Simon Glass

Convert the exynos GPIO driver to driver model. This implements the generic
GPIO interface but not the extra Exynos-specific functions.

Signed-off-by Simon Glass <[email protected]>

---

Changes in v9:
- Add missing compatible strings from exynos_gpio_ids[]

Changes in v8:
- Enable driver model for smdkc100 and s5p_goni separately

Changes in v7:
- Bring in patches from the SPI series to move post-reloc DM init earlier

Changes in v6: None
Changes in v5:
- Remove RFC label now that build errors are fixed
- Tidy up and update cover letter message
- Avoid reordering functions

Changes in v4:
- Add patches for exynos GPIO support

   drivers/gpio/s5p_gpio.c         | 424
+++++++++++++++++++++++++++-------------
   include/configs/exynos-common.h |   4 +
   include/configs/s5p_goni.h      |   3 +
   include/configs/smdkc100.h      |   3 +
   4 files changed, 298 insertions(+), 136 deletions(-)

drivers/gpio/s5p_gpio.c +0 -0

index 99f2dd8..13d74eb 100644
@@ -6,8 +6,15 @@
    */
 

..snip..

Quoted 21 lines

+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */

drivers/gpio/s5p_gpio.c +13 -0

+static int gpio_exynos_bind(struct udevice *parent)
+{
+       struct exynos_gpio_platdata *plat = parent->platdata;
+       struct s5p_gpio_bank *bank, *base;
+       const void *blob = gd->fdt_blob;
+       int node;
+
+       /* If this is a child device, there is nothing to do here */
+       if (plat)
+               return 0;
+
+       base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+                                                  parent->of_offset,

"reg");
+ for (node = fdt_first_subnode(blob, parent->of_offset), bank =
base;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 424

Quoted 2 lines

drivers/gpio/s5p_gpio.c +2 -0

+            node > 0;
+            node = fdt_next_subnode(blob, node), bank++) {

Here (bank++) you assume, that order of subnodes of each pinctrl is the same
like in dts file - as I wrote in comment to patch 04 - it isn't.

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 434

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+               struct exynos_gpio_platdata *plat;
+               struct udevice *dev;
+               fdt_addr_t reg;
+               int ret;
+
+               if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+                       continue;
+               plat = calloc(1, sizeof(*plat));
+               if (!plat)
+                       return -ENOMEM;

Some parts of GPIO banks, for which "reg" can be found are prober.

Quoted 17 lines

drivers/gpio/s5p_gpio.c +3 -0

+               reg = fdtdec_get_addr(blob, node, "reg");
+               if (reg != FDT_ADDR_T_NONE)
+                       bank = (struct s5p_gpio_bank *)((ulong)base +

reg);

drivers/gpio/s5p_gpio.c +6 -0

+               plat->bank = bank;
+               plat->bank_name = fdt_get_name(blob, node, NULL);
+               debug("dev at %p: %s\n", bank, plat->bank_name);
+
+               ret = device_bind(parent, parent->driver,
+                                       plat->bank_name, plat, -1,

&dev);

drivers/gpio/s5p_gpio.c +6 -0

+               if (ret)
+                       return ret;
+               dev->of_offset = parent->of_offset;
+       }
+
+       return 0;

drivers/gpio/s5p_gpio.c void gpio_set_rate(int gpio, int mode) · line 459

Quoted 10 lines

drivers/gpio/s5p_gpio.c +10 -0

+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+       { .compatible = "samsung,s5pc100-pinctrl" },
+       { .compatible = "samsung,s5pc110-pinctrl" },
+       { .compatible = "samsung,exynos4210-pinctrl" },
+       { .compatible = "samsung,exynos4x12-pinctrl" },
+       { .compatible = "samsung,exynos5250-pinctrl" },
+       { .compatible = "samsung,exynos5420-pinctrl" },
+       { }

... snip ...

And this is not the end of issues:)

Unfortunately Exynos4xxx has a gaps in GPIO bank address space, and the big
gpio enum lists includes that here:
arch/arm/include/asm/arch-exynos/gpio.h

This works for Exynos5, because it's enum list is linear.

And the driver gpio-uclass.c - assumes that the gpio numbers are linear. When I removed the gaps in enum for 4x12 -then gpio is mapped good.

And after remove the enum gaps, it also requires fitting the gpios in dts
files, e.g. cd-gpio, pwr-gpios for sdhci host.

Quoted 5 lines

Sorry for such late reply in v9 but, before it seems working fine - I didn't
try to check the sd card before.

I hope that after that fixes, everything will work fine:)

Thanks very much for testing this. As mentioned on the other patch, please try u-boot-dm/next and see how things look.

Quoted 8 lines

Quoted 3 lines

Regards,
Simon

No problem, it's also important for me. I will check the "next" in a few minutes.

Regards,

After a quick look into the code I suppose that the issues are not fixed, but it is tested for sure:)

So the main required changes:
1. Remove/fix all "**pinctrl-uboot.dtsi" files and move the cells size into "pinctrl.dtsi"

2. Remove the gaps in Exynos4xxx gpio enum:
arch/arm/include/asm/arch-exynos/gpio.

and now I checked that the same is for s5pc110, here:
arch/arm/include/asm/arch-s5pc1xx/gpio.h (only S5PC110_GPIO_H00)

3. Fix exynos4xxx boards *.dts after remove the gaps in gpio enum.

(Note: Tegra patches have been applied, I am resending with exynos only)

Now that driver model is part of U-Boot, the task of converting drivers over to it begins. GPIO is one of the easiest to convert, since it already has a sandbox driver and a uclass driver.

The Tegra GPIO driver is relatively simple since it has a linear numbering and already uses the generic GPIO framework. Each GPIO bank has a separate device. Some arguments have been made that a single device should support all the GPIO banks, but currently the driver model uclass does not work that way and it would require a second-level data structure to handle the bank feature.

This driver has been tested on:

- Seaboard (Tegra 20)
- Beaver (Tegra 30)
- Jetson-TK1 (Tegra 124).

I don't have a Tegra 114 board (Dalmore seems to be the only one with U-Boot support) but I am quite confident that it works.

For exynos, the pinctrl device tree files are brought in from the kernel and cut down to remove the groupings which we don't yet use. Very small additions are made to avoid replicating the awful tables that Linux has for every exynos SoC. This series sits on top of the exynos refactors.

The 'gpio' command is updated to support display of only the allocated GPIOs. This is much more friendly than displaying a large table.

A few related clean-ups are provided as well.

This series is available at u-boot-dm.git, branch working.

Changes in v9:
- Change compatible string to s5pc110-pinctrl for s5p_goni
- Add missing compatible strings from exynos_gpio_ids[]

Changes in v8:
- Adjust odroid device tree file to use #include instead of /include/
- Add missing special case reg property for exynos5420 GPX0
- Add patch containing pinctrl settings for s5p_goni
- Add patch containing pinctrl settings for s5p_goni
- Add new patch to move smdkc100 to generic board
- Add new patch to move s5p_goni to generic board
- Enable driver model for smdkc100 and s5p_goni separately

Changes in v7:
- Bring in patches from the SPI series to move post-reloc DM init earlier

Changes in v6:
- Fix typo in compatible string
- Remove exynos5420.dtsi which is not used in U-Boot
- Move U-Boot changes into their own file
- Use exynos54xx everywhere instead of exynos5420

Changes in v5:
- Put this patch before the others to avoid breaking bisectability
- Add additional gpio_request() calls for other samsung boards
- Use a mask instead of division in gpio_request() naming call
- Remove RFC label now that build errors are fixed
- Tidy up and update cover letter message
- Avoid reordering functions

Changes in v4:
- Add patches for exynos GPIO support

Simon Glass (12):
dm: exynos: dts: Convert /include/ to #include
dm: exynos: Bring in pinctrl dts files from Linux kernel
dm: exynos: dts: Remove unused pinctrl information to save space
dm: exynos: dts: Adjust device tree files for U-Boot
dm: exynos: Add pinctrl settings for smdkc100
dm: exynos: Add pinctrl settings for s5p_goni
dm: exynos: Move smdkc100 to generic board
dm: exynos: Move s5p_goni to generic board
dm: exynos: Tidy up GPIO headers
dm: exynos: Tidy up GPIO defines
dm: exynos: Make sure that GPIOs are requested
dm: exynos: gpio: Convert to driver model

  arch/arm/cpu/armv7/exynos/pinmux.c         |   5 +-
  arch/arm/dts/exynos4.dtsi                  |   9 +-
  arch/arm/dts/exynos4210-origen.dts         |   4 +-
  arch/arm/dts/exynos4210-pinctrl-uboot.dtsi |  27 ++
  arch/arm/dts/exynos4210-pinctrl.dtsi       | 306 ++++++++++++++++++++
  arch/arm/dts/exynos4210-smdkv310.dts       |   2 +-
  arch/arm/dts/exynos4210-trats.dts          |   2 +-
  arch/arm/dts/exynos4210-universal_c210.dts |   2 +-
  arch/arm/dts/exynos4210.dtsi               | 155 ++++++++++
  arch/arm/dts/exynos4412-odroid.dts         |   2 +-
  arch/arm/dts/exynos4412-trats2.dts         |   2 +-
  arch/arm/dts/exynos4412.dtsi               |  38 +++
  arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi |  46 +++
  arch/arm/dts/exynos4x12-pinctrl.dtsi       | 346 ++++++++++++++++++++++
  arch/arm/dts/exynos4x12.dtsi               | 114 ++++++++
  arch/arm/dts/exynos5.dtsi                  |  56 +++-
  arch/arm/dts/exynos5250-pinctrl-uboot.dtsi |  40 +++
  arch/arm/dts/exynos5250-pinctrl.dtsi       | 333 +++++++++++++++++++++
  arch/arm/dts/exynos5250-smdk5250.dts       |   2 +-
  arch/arm/dts/exynos5250-snow.dts           |   2 +-
  arch/arm/dts/exynos5250.dtsi               |  40 ++-
  arch/arm/dts/exynos5420-peach-pit.dts      |   2 +-
  arch/arm/dts/exynos5420-smdk5420.dts       |   2 +-
  arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi |  40 +++
  arch/arm/dts/exynos54xx-pinctrl.dtsi       | 305 ++++++++++++++++++++
  arch/arm/dts/exynos54xx.dtsi               |  44 ++-
  arch/arm/dts/s5pc100-pinctrl.dtsi          | 180 ++++++++++++
  arch/arm/dts/s5pc110-pinctrl.dtsi          | 273 ++++++++++++++++++
  arch/arm/dts/s5pc1xx-goni.dts              |   7 +
  arch/arm/dts/s5pc1xx-smdkc100.dts          |   7 +
  arch/arm/include/asm/arch-exynos/gpio.h    |   5 -
  arch/arm/include/asm/arch-s5pc1xx/gpio.h   |   4 -
  board/samsung/arndale/arndale.c            |   4 +-
  board/samsung/common/board.c               |   2 +-
  board/samsung/common/misc.c                |   3 +-
  board/samsung/goni/goni.c                  |   4 +-
  board/samsung/origen/origen.c              |   2 +-
  board/samsung/smdk5250/exynos5-dt.c        |   7 +
  board/samsung/smdk5420/smdk5420.c          |   6 +-
  board/samsung/smdkc100/smdkc100.c          |   2 +-
  board/samsung/smdkv310/smdkv310.c          |   2 +-
  board/samsung/trats/trats.c                |  17 +-
  board/samsung/trats2/trats2.c              |  27 +-
  board/samsung/universal_c210/universal.c   |   4 +-
  drivers/gpio/s5p_gpio.c                    | 446 +++++++++++++++++++----------
  drivers/mmc/s5p_sdhci.c                    |   7 +-
  include/configs/exynos-common.h            |   4 +
  include/configs/s5p_goni.h                 |   5 +
  include/configs/smdkc100.h                 |   5 +
  49 files changed, 2758 insertions(+), 191 deletions(-)

create mode 100644 arch/arm/dts/exynos4210-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos4210-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos4210.dtsi create mode 100644 arch/arm/dts/exynos4412.dtsi create mode 100644 arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos4x12-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos4x12.dtsi create mode 100644 arch/arm/dts/exynos5250-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos5250-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos54xx-pinctrl.dtsi create mode 100644 arch/arm/dts/s5pc100-pinctrl.dtsi create mode 100644 arch/arm/dts/s5pc110-pinctrl.dtsi