ls102x: configs - Add hash command in freescale LS1 platforms
PATCH v4 1/1 ls102x: configs - Add hash command in freescale LS1 platforms
Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block.
---
Changes from v3:
Added CONFIG_FSL_CAAM to enable CAAM/SEC
Changes from v2:
Incorporated Denx comments
Rearranged config options in order
sec_init call modified
Changes from v1:
Rebased to HEAD of uboot
Compilation warning fixed in ls1021atwr build
arch/arm/include/asm/arch-ls102xa/config.h | 4 ++++ board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ include/configs/ls1021aqds.h | 7 +++++++ include/configs/ls1021atwr.h | 8 ++++++++ 5 files changed, 39 insertions(+)
arch/arm/include/asm/arch-ls102xa/config.h +4 -0
@@ -19,6 +19,8 @@#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
@@ -66,6 +68,7 @@#define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE #define DCU_LAYER_MAX_NUM 16
@@ -76,6 +79,7 @@#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8#define CONFIG_NUM_DDR_CONTROLLERS 1#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5#else #error SoC not defined#endif
board/freescale/ls1021aqds/ls1021aqds.c +10 -0
@@ -13,6 +13,7 @@#include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <fsl_sec.h> #include "../common/qixis.h" #include "ls1021aqds_qixis.h"
@@ -213,6 +214,15 @@ int config_serdes_mux(void)return 0 ; } +#if defined(CONFIG_MISC_INIT_R ) +int misc_init_r (void ) +{ +#ifdef CONFIG_FSL_CAAM +return sec_init (); +#endif +} +#endif +int board_init (void ) {struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR ;
board/freescale/ls1021atwr/ls1021atwr.c +10 -0
@@ -16,6 +16,7 @@#include <netdev.h> #include <fsl_mdio.h> #include <tsec.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -280,6 +281,15 @@ int board_init(void)return 0 ; } +#if defined(CONFIG_MISC_INIT_R ) +int misc_init_r (void ) +{ +#ifdef CONFIG_FSL_CAAM +return sec_init (); +#endif +} +#endif +void ft_board_setup (void *blob,bd_t *bd) {ft_cpu_setup (blob, bd);
include/configs/ls1021aqds.h +7 -0
@@ -69,6 +69,7 @@ unsigned long get_board_ddr_clk(void);#define CONFIG_SYS_HAS_SERDES +#define CONFIG_FSL_CAAM /* Enable CAAM */ /* * IFC Definitions */
@@ -388,4 +389,10 @@ unsigned long get_board_ddr_clk(void);#define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif
include/configs/ls1021atwr.h +8 -0
@@ -48,6 +48,8 @@#define CONFIG_SYS_HAS_SERDES +#define CONFIG_FSL_CAAM /* Enable CAAM */ +/* * IFC Definitions */
@@ -288,4 +290,10 @@#define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif
Signature · 1 line
1.8.1.4
PATCH v4 1/1 ls102x: configs - Add hash command in freescale LS1 platforms
Quoted 8 lines · Ruchika Gupta
Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by Ruchika Gupta <[email protected]>CC York Sun <[email protected]>---
This and other patches in this series have been applied to fsl-qoriq/master, awaiting upstream.
York