ARM: dts: dra72-evm: NAND and USB support

PATCH New Roger Quadros 3 participants 11 messages Oct 21, 2014 – Nov 10, 2014 Device tree bindings

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Roger Quadros

author

2014-10-21 10:41 UTC #0 lore raw

cover ARM: dts: dra72-evm: NAND and USB support

Hi Tony,

These patches add NAND and USB support for DRA72-evm. Patches are for v3.19 and based on v3.18-rc1.

I've tested that NAND and USB host works fine on DRA72-evm.

I couldn't get USB gadget mode to work. It doesn't work on DRA7-evm either. There seems to be some issue at the driver level. The dts entries are correct though.

cheers,
-roger

George Cherian (1):
ARM: dts: dra72-evm: Enable USB support for dra72-evm.

Roger Quadros (3):
ARM: dts: dra72-evm: Add NAND support
ARM: dts: DRA7: Move USB_OTG 4 to dra74x.dtsi
ARM: dts: dra72-evm: Add regulator information to USB2 PHYs

 arch/arm/boot/dts/dra7.dtsi     |  20 ------
 arch/arm/boot/dts/dra72-evm.dts | 147 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra74x.dtsi   |  22 ++++++
 3 files changed, 169 insertions(+), 20 deletions(-)

Signature · 1 line

1.8.3.2

Roger Quadros

author

2014-10-21 10:41 UTC #1 lore raw

PATCH 1/4 ARM: dts: dra72-evm: Add NAND support

DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node.

The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so:

SW5.1 (NAND_SELn) = ON (LOW)
SW5.9 (GPMC_WPN) = OFF (HIGH)

Signed-off-by Roger Quadros <[email protected]>

Signed-off-by Sekhar Nori <[email protected]>

---
 arch/arm/boot/dts/dra72-evm.dts | 115 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

arch/arm/boot/dts/dra72-evm.dts +115 -0

index 4107428..6f5417a 100644
@@ -26,6 +26,33 @@
 			0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
 		>;
 	};
+
+	nand_default: nand_default {
+		pinctrl-single,pins = <
+			0x0	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
+			0x4	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
+			0x8	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
+			0xc	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
+			0x10	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
+			0x14	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
+			0x18	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
+			0x1c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
+			0x20	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
+			0x24	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
+			0x28	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
+			0x2c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
+			0x30	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
+			0x34	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
+			0x38	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
+			0x3c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
+			0xb4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
+			0xc4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+			0xcc	(PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+			0xc8	(PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+			0xd0	(PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
+			0xd8	(PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -142,3 +169,91 @@
 &uart1 {
 	status = "okay";
 };
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_default>;
+	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
+	nand at 0,0 {
+		/* To use NAND, DIP switch SW5 must be set like so:
+		 * SW5.1 (NAND_SELn) = ON (LOW)
+		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
+		 */
+		reg = <0 0 4>;		/* device IO registers */
+		ti,nand-ecc-opt = "bch8";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <80>;
+		gpmc,cs-wr-off-ns = <80>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <60>;
+		gpmc,adv-wr-off-ns = <60>;
+		gpmc,we-on-ns = <10>;
+		gpmc,we-off-ns = <50>;
+		gpmc,oe-on-ns = <4>;
+		gpmc,oe-off-ns = <40>;
+		gpmc,access-ns = <40>;
+		gpmc,wr-access-ns = <80>;
+		gpmc,rd-cycle-ns = <80>;
+		gpmc,wr-cycle-ns = <80>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition at 0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x000020000>;
+		};
+		partition at 1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00020000 0x00020000>;
+		};
+		partition at 2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00040000 0x00020000>;
+		};
+		partition at 3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x00060000 0x00020000>;
+		};
+		partition at 4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition at 5 {
+			label = "NAND.u-boot";
+			reg = <0x000c0000 0x00100000>;
+		};
+		partition at 6 {
+			label = "NAND.u-boot-env";
+			reg = <0x001c0000 0x00020000>;
+		};
+		partition at 7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x001e0000 0x00020000>;
+		};
+		partition at 8 {
+			label = "NAND.kernel";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition at 9 {
+			label = "NAND.file-system";
+			reg = <0x00a00000 0x0f600000>;
+		};
+	};
+};

Signature · 1 line

1.8.3.2

Nishanth Menon

2014-10-21 16:43 UTC #2 lore raw

PATCH 1/4 ARM: dts: dra72-evm: Add NAND support

Roger,

Quoted 9 lines · Roger Quadros

DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node.
The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so:
SW5.1 (NAND_SELn) = ON (LOW)
SW5.9 (GPMC_WPN) = OFF (HIGH)

Could we move this description to the dts as a comment? it would be little more easier to refer to than figuring it out from git log. I recollect trying to figure this out while attempting to test out NAND previously, never actually thought to check in git log. just a suggestion..

Quoted 138 lines

Signed-off-by Roger Quadros <[email protected]>

Signed-off-by Sekhar Nori <[email protected]>

---
 arch/arm/boot/dts/dra72-evm.dts | 115 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

arch/arm/boot/dts/dra72-evm.dts +115 -0

index 4107428..6f5417a 100644
@@ -26,6 +26,33 @@
 			0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
 		>;
 	};
+
+	nand_default: nand_default {
+		pinctrl-single,pins = <
+			0x0	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
+			0x4	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
+			0x8	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
+			0xc	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
+			0x10	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
+			0x14	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
+			0x18	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
+			0x1c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
+			0x20	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
+			0x24	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
+			0x28	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
+			0x2c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
+			0x30	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
+			0x34	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
+			0x38	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
+			0x3c	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
+			0xb4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
+			0xc4	(PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+			0xcc	(PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+			0xc8	(PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+			0xd0	(PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
+			0xd8	(PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -142,3 +169,91 @@
 &uart1 {
 	status = "okay";
 };
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_default>;
+	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
+	nand at 0,0 {
+		/* To use NAND, DIP switch SW5 must be set like so:
+		 * SW5.1 (NAND_SELn) = ON (LOW)
+		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
+		 */
+		reg = <0 0 4>;		/* device IO registers */
+		ti,nand-ecc-opt = "bch8";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <80>;
+		gpmc,cs-wr-off-ns = <80>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <60>;
+		gpmc,adv-wr-off-ns = <60>;
+		gpmc,we-on-ns = <10>;
+		gpmc,we-off-ns = <50>;
+		gpmc,oe-on-ns = <4>;
+		gpmc,oe-off-ns = <40>;
+		gpmc,access-ns = <40>;
+		gpmc,wr-access-ns = <80>;
+		gpmc,rd-cycle-ns = <80>;
+		gpmc,wr-cycle-ns = <80>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition at 0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x000020000>;
+		};
+		partition at 1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00020000 0x00020000>;
+		};
+		partition at 2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00040000 0x00020000>;
+		};
+		partition at 3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x00060000 0x00020000>;
+		};
+		partition at 4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition at 5 {
+			label = "NAND.u-boot";
+			reg = <0x000c0000 0x00100000>;
+		};
+		partition at 6 {
+			label = "NAND.u-boot-env";
+			reg = <0x001c0000 0x00020000>;
+		};
+		partition at 7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x001e0000 0x00020000>;
+		};
+		partition at 8 {
+			label = "NAND.kernel";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition at 9 {
+			label = "NAND.file-system";
+			reg = <0x00a00000 0x0f600000>;
+		};
+	};
+};

Signature · 2 lines

Regards,
Nishanth Menon

Nishanth Menon

2014-10-21 17:16 UTC #3 lore raw

PATCH 1/4 ARM: dts: dra72-evm: Add NAND support

Quoted 18 lines · Nishanth Menon

Roger,
Quoted 9 lines · Roger Quadros
DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node.
The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so:
SW5.1 (NAND_SELn) = ON (LOW)
SW5.9 (GPMC_WPN) = OFF (HIGH)
Could we move this description to the dts as a comment? it would be little more easier to refer to than figuring it out from git log. I recollect trying to figure this out while attempting to test out NAND previously, never actually thought to check in git log. just a suggestion..

[...]

Quoted 10 lines

arch/arm/boot/dts/dra72-evm.dts line 186

Quoted 10 lines

+&gpmc {

arch/arm/boot/dts/dra72-evm.dts +9 -0

+     status = "okay";
+     pinctrl-names = "default";
+     pinctrl-0 = <&nand_default>;
+     ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+     nand at 0,0 {
+             /* To use NAND, DIP switch SW5 must be set like so:
+              * SW5.1 (NAND_SELn) = ON (LOW)
+              * SW5.9 (GPMC_WPN) = OFF (HIGH)
+              */

[...]

Uggh.. ignore my comment - I see you already did that.. my bad.. i missed it :(

Quickly trying to test this, I got the following:
"

[    1.840728] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    1.847290] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xca
[    1.854003] nand: Micron MT29F2G16ABAEAWP
[    1.858245] nand: 256MiB, SLC, page size: 2048, OOB size: 64
[    1.864227] omap2-nand omap2-nand.0: CONFIG_MTD_NAND_OMAP_BCH not enabled
[    1.871459] omap2-nand: probe of omap2-nand.0 failed with error -22

Full log: http://hastebin.com/ozugepemin.md

Does this depend on
http://marc.info/?l=linux-omap&m=141389532511600&w=2 to function? I assume yes.

as well?

---
Regards,
Nishanth Menon

Nishanth Menon

2014-10-21 17:32 UTC #4 lore raw

PATCH 1/4 ARM: dts: dra72-evm: Add NAND support

Quoted 22 lines · Nishanth Menon

Quoted 18 lines · Nishanth Menon
Roger,
Quoted 9 lines · Roger Quadros
DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node.
The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so:
SW5.1 (NAND_SELn) = ON (LOW)
SW5.9 (GPMC_WPN) = OFF (HIGH)
Could we move this description to the dts as a comment? it would be little more easier to refer to than figuring it out from git log. I recollect trying to figure this out while attempting to test out NAND previously, never actually thought to check in git log. just a suggestion..
[...]

Quoted 7 lines

arch/arm/boot/dts/dra72-evm.dts line 183

Quoted 7 lines

+&gpmc {

arch/arm/boot/dts/dra72-evm.dts +6 -0

+     status = "okay";
+     pinctrl-names = "default";
+     pinctrl-0 = <&nand_default>;
+     ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+     nand at 0,0 {
+             /* To use NAND, DIP switch SW5 must be set like so:

		      ^^ minor:
		      /*
		       * To use NAND,....

Quoted 17 lines

Quoted 3 lines
arch/arm/boot/dts/dra72-evm.dts line 186
Quoted 3 lines
arch/arm/boot/dts/dra72-evm.dts +3 -0
+              * SW5.1 (NAND_SELn) = ON (LOW)
+              * SW5.9 (GPMC_WPN) = OFF (HIGH)
+              */
[...]
Uggh.. ignore my comment - I see you already did that.. my bad.. i missed it :(
Quickly trying to test this, I got the following:
"
[    1.840728] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    1.847290] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xca
[    1.854003] nand: Micron MT29F2G16ABAEAWP
[    1.858245] nand: 256MiB, SLC, page size: 2048, OOB size: 64
[    1.864227] omap2-nand omap2-nand.0: CONFIG_MTD_NAND_OMAP_BCH not enabled
[    1.871459] omap2-nand: probe of omap2-nand.0 failed with error -22

Quoted 7 lines

"
Full log: http://hastebin.com/ozugepemin.md
Does this depend on
http://marc.info/?l=linux-omap&m=141389532511600&w=2 to function? I assume yes.

looks like we'd want Tony to enable CONFIG_MTD_NAND_OMAP_BCH in omap2plus_defconfig?

With that, it works like a charm..
http://slexy.org/raw/s29rfTTWB4

Feel free to add my:

Tested-by Nishanth Menon <[email protected]>

Acked-by Nishanth Menon <[email protected]>

Signature · 2 lines

Regards,
Nishanth Menon

Roger Quadros

author

2014-10-28 15:04 UTC #5 lore raw

PATCH 1/4 ARM: dts: dra72-evm: Add NAND support

Nishant,

Quoted 61 lines · Nishanth Menon

Quoted 22 lines · Nishanth Menon
Quoted 18 lines · Nishanth Menon
Roger,
Quoted 9 lines · Roger Quadros
DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node.
The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so:
SW5.1 (NAND_SELn) = ON (LOW)
SW5.9 (GPMC_WPN) = OFF (HIGH)
Could we move this description to the dts as a comment? it would be little more easier to refer to than figuring it out from git log. I recollect trying to figure this out while attempting to test out NAND previously, never actually thought to check in git log. just a suggestion..
[...]
Quoted 7 lines
Quoted 7 lines
arch/arm/boot/dts/dra72-evm.dts line 183
Quoted 7 lines
+&gpmc {
arch/arm/boot/dts/dra72-evm.dts +6 -0
+     status = "okay";
+     pinctrl-names = "default";
+     pinctrl-0 = <&nand_default>;
+     ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+     nand at 0,0 {
+             /* To use NAND, DIP switch SW5 must be set like so:
		      ^^ minor:
		      /*
		       * To use NAND,.... 
Quoted 17 lines
Quoted 3 lines
arch/arm/boot/dts/dra72-evm.dts line 186
Quoted 3 lines
arch/arm/boot/dts/dra72-evm.dts +3 -0
+              * SW5.1 (NAND_SELn) = ON (LOW)
+              * SW5.9 (GPMC_WPN) = OFF (HIGH)
+              */
[...]
Uggh.. ignore my comment - I see you already did that.. my bad.. i missed it :(
Quickly trying to test this, I got the following:
"
[    1.840728] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    1.847290] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xca
[    1.854003] nand: Micron MT29F2G16ABAEAWP
[    1.858245] nand: 256MiB, SLC, page size: 2048, OOB size: 64
[    1.864227] omap2-nand omap2-nand.0: CONFIG_MTD_NAND_OMAP_BCH not enabled
[    1.871459] omap2-nand: probe of omap2-nand.0 failed with error -22
Quoted 7 lines
"
Full log: http://hastebin.com/ozugepemin.md
Does this depend on
http://marc.info/?l=linux-omap&m=141389532511600&w=2 to function? I assume yes.
looks like we'd want Tony to enable CONFIG_MTD_NAND_OMAP_BCH in omap2plus_defconfig?

Quoted 8 lines

With that, it works like a charm..
http://slexy.org/raw/s29rfTTWB4
Feel free to add my:
Tested-by Nishanth Menon <[email protected]>
Acked-by Nishanth Menon <[email protected]>

Thanks for testing. Sorry for being silent for a while. This whole thread got moved accidentally to old-inbox ;). Took a while to figure out if I really sent these patches or just in my dreamworld. :)

cheers,
-roger

Roger Quadros

author

2014-10-21 10:41 UTC #6 lore raw

PATCH 2/4 ARM: dts: DRA7: Move USB_OTG 4 to dra74x.dtsi

In reply to Roger Quadros

The 4th USB controller instance present only on the DRA74x family of devices so move it there.

Signed-off-by Roger Quadros <[email protected]>

Acked-by Nishanth Menon <[email protected]>

Signed-off-by Sekhar Nori <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi   | 20 --------------------
 arch/arm/boot/dts/dra74x.dtsi | 22 ++++++++++++++++++++++
 2 files changed, 22 insertions(+), 20 deletions(-)

arch/arm/boot/dts/dra7.dtsi +0 ~~-20~~

index 9cc9843..ea243e0 100644
@@ -1204,26 +1204,6 @@
 			};
 		};
 
-		omap_dwc3_4 at 48940000 {
-			compatible = "ti,dwc3";
-			ti,hwmods = "usb_otg_ss4";
-			reg = <0x48940000 0x10000>;
-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			utmi-mode = <2>;
-			ranges;
-			status = "disabled";
-			usb4: usb at 48950000 {
-				compatible = "snps,dwc3";
-				reg = <0x48950000 0x17000>;
-				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-				tx-fifo-resize;
-				maximum-speed = "high-speed";
-				dr_mode = "otg";
-			};
-		};
-
 		elm: elm at 48078000 {
 			compatible = "ti,am3352-elm";
 			reg = <0x48078000 0xfc0>;      /* device IO registers */

arch/arm/boot/dts/dra74x.dtsi +22 -0

index 3be544c..5667b92 100644
@@ -44,4 +44,26 @@
 		interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	ocp {
+		omap_dwc3_4 at 48940000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss4";
+			reg = <0x48940000 0x10000>;
+			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			status = "disabled";
+			usb4: usb at 48950000 {
+				compatible = "snps,dwc3";
+				reg = <0x48950000 0x17000>;
+				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
+	};
 };

Signature · 1 line

1.8.3.2

Roger Quadros

author

2014-10-21 10:41 UTC #7 lore raw

PATCH 3/4 ARM: dts: dra72-evm: Enable USB support for dra72-evm.

In reply to Roger Quadros

From: George Cherian <[email protected]>

Add USB data and pinctrl for USB.

Signed-off-by George Cherian <[email protected]>

Signed-off-by Sekhar Nori <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra72-evm.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm/boot/dts/dra72-evm.dts +24 -0

index 6f5417a..ad6ec4a 100644
@@ -53,6 +53,18 @@
 			0xd8	(PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
 		>;
 	};
+
+	usb1_pins: pinmux_usb1_pins {
+		pinctrl-single,pins = <
+			0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+		>;
+	};
+
+	usb2_pins: pinmux_usb2_pins {
+		pinctrl-single,pins = <
+			0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+		>;
+	};
 };
 
 &i2c1 {

@@ -257,3 +269,15 @@
 		};
 	};
 };
+
+&usb1 {
+	dr_mode = "peripheral";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb2_pins>;
+};

Signature · 1 line

1.8.3.2

Roger Quadros

author

2014-10-21 10:41 UTC #8 lore raw

PATCH 4/4 ARM: dts: dra72-evm: Add regulator information to USB2 PHYs

In reply to Roger Quadros

The ldo4_reg regulator provides power to the USB1 and USB2 High Speed PHYs.

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra72-evm.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/arm/boot/dts/dra72-evm.dts +8 -0

index ad6ec4a..b135aab 100644
@@ -270,6 +270,14 @@
 	};
 };
 
+&usb2_phy1 {
+	phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+	phy-supply = <&ldo4_reg>;
+};
+
 &usb1 {
 	dr_mode = "peripheral";
 	pinctrl-names = "default";

Signature · 1 line

1.8.3.2

Roger Quadros

author

2014-10-30 14:36 UTC #9 lore raw

cover ARM: dts: dra72-evm: NAND and USB support

In reply to Roger Quadros

Hi Tony,

Quoted 9 lines · Roger Quadros

Hi Tony,
These patches add NAND and USB support for DRA72-evm. Patches are for v3.19 and based on v3.18-rc1.
I've tested that NAND and USB host works fine on DRA72-evm.
I couldn't get USB gadget mode to work. It doesn't work on DRA7-evm either. There seems to be some issue at the driver level. The dts entries are correct though.

Any further comments on this? Can we please queue this for -next? Thanks.

cheers,
-roger

Quoted 17 lines

cheers,
-roger
George Cherian (1):
ARM: dts: dra72-evm: Enable USB support for dra72-evm.
Roger Quadros (3):
ARM: dts: dra72-evm: Add NAND support
ARM: dts: DRA7: Move USB_OTG 4 to dra74x.dtsi
ARM: dts: dra72-evm: Add regulator information to USB2 PHYs
 arch/arm/boot/dts/dra7.dtsi     |  20 ------
 arch/arm/boot/dts/dra72-evm.dts | 147 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra74x.dtsi   |  22 ++++++
 3 files changed, 169 insertions(+), 20 deletions(-)

Tony Lindgren

2014-11-10 20:26 UTC #10 lore raw

cover ARM: dts: dra72-evm: NAND and USB support

Quoted 8 lines · Roger Quadros

Hi Tony,
Quoted 5 lines · Roger Quadros
Hi Tony,
These patches add NAND and USB support for DRA72-evm. Patches are for v3.19 and based on v3.18-rc1.

Quoted 6 lines

Quoted 4 lines
I've tested that NAND and USB host works fine on DRA72-evm.
I couldn't get USB gadget mode to work. It doesn't work on DRA7-evm either. There seems to be some issue at the driver level. The dts entries are correct though.
Any further comments on this? Can we please queue this for -next? Thanks.

Applying into omap-for-v3.19/dt thanks.

Tony

Quoted 17 lines

Quoted 16 lines
cheers,
-roger
George Cherian (1):
ARM: dts: dra72-evm: Enable USB support for dra72-evm.
Roger Quadros (3):
ARM: dts: dra72-evm: Add NAND support
ARM: dts: DRA7: Move USB_OTG 4 to dra74x.dtsi
ARM: dts: dra72-evm: Add regulator information to USB2 PHYs
 arch/arm/boot/dts/dra7.dtsi     |  20 ------
 arch/arm/boot/dts/dra72-evm.dts | 147 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra74x.dtsi   |  22 ++++++
 3 files changed, 169 insertions(+), 20 deletions(-)