Set of fixes for Exynos4xxx boards

The SD Card slot detection pin should be configured as input.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 3 lines · Przemyslaw Marczak

The SD Card slot detection pin should be configured as input.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

Hi Tom,

Quoted 3 lines · Simon Glass

Quoted 2 lines · Przemyslaw Marczak

The SD Card slot detection pin should be configured as input.

Quoted 3 lines

Quoted 1 line

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

As this directly relates to fixes for the driver model series, I will pick this up in the DM tree. Some of the patches need a respin but I will pull in those that are ready.

The SD Card slot detection pin should be configured as input.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 drivers/mmc/s5p_sdhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/mmc/s5p_sdhci.c +0 -0

index 0dea45d..a5d3487 100644

drivers/mmc/s5p_sdhci.c +0 -0

 		if (gpio_get_value(host->cd_gpio.gpio))
 			return -ENODEV;
 

Hi, Przemyslaw.

Quoted 7 lines · Przemyslaw Marczak

The SD Card slot detection pin should be configured as input.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  drivers/mmc/s5p_sdhci.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

drivers/mmc/s5p_sdhci.c static int do_sdhci_init(struct sdhci_host *host) · line 126

Quoted 10 lines

drivers/mmc/s5p_sdhci.c +1 -1

index 0dea45d..a5d3487 100644
@@ -123,7 +123,7 @@ static int do_sdhci_init(struct sdhci_host *host)
  	if (fdt_gpio_isvalid(&host->cd_gpio)) {
  		sprintf(str, "sdhci%d_cd", host->index & 0xf);
  		gpio_request(host->cd_gpio.gpio, str);
-		gpio_direction_output(host->cd_gpio.gpio, 1);
+		gpio_direction_input(host->cd_gpio.gpio);

Input is right?

Best Regards,
Jaehoon Chung

Quoted 4 lines

drivers/mmc/s5p_sdhci.c +0 -0

  		if (gpio_get_value(host->cd_gpio.gpio))
  			return -ENODEV;
 

This config is required by Odroid, and could be also useful for the other boards.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 4 lines · Przemyslaw Marczak

This config is required by Odroid, and could be also useful for the other boards.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

After remove the offsets in Exynos4/4x12 gpio enums, an addidional gpio base

addresses are required.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++
 1 file changed, 9 insertions(+)

arch/arm/include/asm/arch-exynos/cpu.h +2 -0

index ba71714..78aceef 100644
@@ -29,6 +29,8 @@
 #define EXYNOS4_MIU_BASE               0x10600000
 #define EXYNOS4_ACE_SFR_BASE           0x10830000
 #define EXYNOS4_GPIO_PART2_BASE                0x11000000
+#define EXYNOS4_GPIO_PART2_0           0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1           0x11000c00 /* GPX0 */
 #define EXYNOS4_GPIO_PART1_BASE                0x11400000
 #define EXYNOS4_FIMD_BASE              0x11C00000
 #define EXYNOS4_MIPI_DSIM_BASE         0x11C80000

@@ -70,7 +72,14 @@
 #define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000

Hi Przemyslaw,

Quoted 1 line · Przemyslaw Marczak

After remove the offsets in Exynos4/4x12 gpio enums, an addidional gpio base

additional

Quoted 22 lines

addresses are required.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++
  1 file changed, 9 insertions(+)

arch/arm/include/asm/arch-exynos/cpu.h +2 -0

index ba71714..78aceef 100644
@@ -29,6 +29,8 @@
  #define EXYNOS4_MIU_BASE               0x10600000
  #define EXYNOS4_ACE_SFR_BASE           0x10830000
  #define EXYNOS4_GPIO_PART2_BASE                0x11000000
+#define EXYNOS4_GPIO_PART2_0           0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1           0x11000c00 /* GPX0 */
  #define EXYNOS4_GPIO_PART1_BASE                0x11400000
  #define EXYNOS4_FIMD_BASE              0x11C00000
  #define EXYNOS4_MIPI_DSIM_BASE         0x11C80000

@@ -70,7 +72,14 @@
  #define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000

arch/arm/include/asm/arch-exynos/cpu.h line 82

Quoted 10 lines

arch/arm/include/asm/arch-exynos/cpu.h +7 -0

  #define EXYNOS4X12_ACE_SFR_BASE                0x10830000
  #define EXYNOS4X12_GPIO_PART2_BASE     0x11000000
+#define EXYNOS4X12_GPIO_PART2_0                0x11000000
+#define EXYNOS4X12_GPIO_PART2_1                0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2                0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3                0x11000c00 /* GPX0 */
  #define EXYNOS4X12_GPIO_PART1_BASE     0x11400000
+#define EXYNOS4X12_GPIO_PART1_0                0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1                0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2                0x11400240 /* GPJ0 */

Why not just number them 0 to 7? It would be simpler.

Also what are these actually used for now? Are they used in SPL perhaps?

Regards,
Simon

This patch adds extra gpio part addresses to exynos4/4x12_gpio_data arrays, which are required since the gpio enum lists are linear

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++-----------
 1 file changed, 39 insertions(+), 20 deletions(-)

arch/arm/include/asm/arch-exynos/gpio.h +32 -18

index ad2ece6..02287de 100644
@@ -284,7 +284,10 @@ enum exynos4_gpio_pin {
        EXYNOS4_GPIO_Y65,
        EXYNOS4_GPIO_Y66,
        EXYNOS4_GPIO_Y67,
-       EXYNOS4_GPIO_X00,               /* 256 0x100 */
+
+       /* GPIO_PART2_1 STARTS */
+       EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+       EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
        EXYNOS4_GPIO_X01,
        EXYNOS4_GPIO_X02,
        EXYNOS4_GPIO_X03,

@@ -318,8 +321,8 @@ enum exynos4_gpio_pin {
        EXYNOS4_GPIO_X37,
 
        /* GPIO_PART3_STARTS */
-       EXYNOS4_GPIO_MAX_PORT_PART_2,   /* 288 0x120 */
-       EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+       EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+       EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
        EXYNOS4_GPIO_Z1,
        EXYNOS4_GPIO_Z2,
        EXYNOS4_GPIO_Z3,

@@ -332,7 +335,7 @@ enum exynos4_gpio_pin {
 };
 
 enum exynos4X12_gpio_pin {
-       /* GPIO_PART1_STARTS */
+       /* EXYNOS4X12_GPIO_PART1_0 starts here */
        EXYNOS4X12_GPIO_A00,            /* 0 */
        EXYNOS4X12_GPIO_A01,
        EXYNOS4X12_GPIO_A02,

@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin {
        EXYNOS4X12_GPIO_D15,
        EXYNOS4X12_GPIO_D16,
        EXYNOS4X12_GPIO_D17,
-       EXYNOS4X12_GPIO_F00,            /* 56 0x38 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+       /* EXYNOS4X12_GPIO_PART1_1 starts here */
+       EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
        EXYNOS4X12_GPIO_F01,
        EXYNOS4X12_GPIO_F02,
        EXYNOS4X12_GPIO_F03,

@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin {
        EXYNOS4X12_GPIO_F35,
        EXYNOS4X12_GPIO_F36,
        EXYNOS4X12_GPIO_F37,
-       EXYNOS4X12_GPIO_J00,            /* 88 0x58 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+       /* EXYNOS4X12_GPIO_PART1_2 starts here */
+       EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
        EXYNOS4X12_GPIO_J01,
        EXYNOS4X12_GPIO_J02,
        EXYNOS4X12_GPIO_J03,

@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin {
        EXYNOS4X12_GPIO_J16,
        EXYNOS4X12_GPIO_J17,
 
-       /* GPIO_PART2_STARTS */
-       EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
-       EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
+       /**
+        * EXYNOS4X12_GPIO_PART2_0 is not used
+        * EXYNOS4X12_GPIO_PART2_1 starts here
+        */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+       EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
        EXYNOS4X12_GPIO_K01,
        EXYNOS4X12_GPIO_K02,
        EXYNOS4X12_GPIO_K03,

@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin {
        EXYNOS4X12_GPIO_Y65,
        EXYNOS4X12_GPIO_Y66,
        EXYNOS4X12_GPIO_Y67,
-       EXYNOS4X12_GPIO_M00,            /* 216 0xd8 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+       /* EXYNOS4X12_GPIO_PART2_2 starts here */
+       EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
        EXYNOS4X12_GPIO_M01,
        EXYNOS4X12_GPIO_M02,
        EXYNOS4X12_GPIO_M03,

@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin {
        EXYNOS4X12_GPIO_M45,
        EXYNOS4X12_GPIO_M46,
        EXYNOS4X12_GPIO_M47,
-       EXYNOS4X12_GPIO_X00,            /* 256 0x100 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+       /* EXYNOS4X12_GPIO_PART2_3 starts here */
+       EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
        EXYNOS4X12_GPIO_X01,
        EXYNOS4X12_GPIO_X02,
        EXYNOS4X12_GPIO_X03,

@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin {
        EXYNOS4X12_GPIO_X36,
        EXYNOS4X12_GPIO_X37,
 
-       /* GPIO_PART3_STARTS */
-       EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
-       EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+       /* EXYNOS4X12_GPIO_PART3 starts here */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+       EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
        EXYNOS4X12_GPIO_Z1,
        EXYNOS4X12_GPIO_Z2,
        EXYNOS4X12_GPIO_Z3,

@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin {
        EXYNOS4X12_GPIO_Z6,
        EXYNOS4X12_GPIO_Z7,
 
-       /* GPIO_PART4_STARTS */
+       /* EXYNOS4X12_GPIO_PART4 starts here */
        EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
        EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
        EXYNOS4X12_GPIO_V01,

@@ -1339,17 +1353,22 @@ struct gpio_info {
        unsigned int max_gpio;  /* Maximum GPIO in this part */
 };
 
-#define EXYNOS4_GPIO_NUM_PARTS 3
+#define EXYNOS4_GPIO_NUM_PARTS 4
 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
        { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
-       { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+       { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+       { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
        { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
 };
 
-#define EXYNOS4X12_GPIO_NUM_PARTS      4

arch/arm/include/asm/arch-exynos/gpio.h +0 -1

        { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
        { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
 };
--

1.9.1

Hi,

Quoted 140 lines · Przemyslaw Marczak

This patch adds extra gpio part addresses to exynos4/4x12_gpio_data arrays, which are required since the gpio enum lists are linear

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++-----------
  1 file changed, 39 insertions(+), 20 deletions(-)

arch/arm/include/asm/arch-exynos/gpio.h +32 -17

index ad2ece6..02287de 100644
@@ -284,7 +284,10 @@ enum exynos4_gpio_pin {
         EXYNOS4_GPIO_Y65,
         EXYNOS4_GPIO_Y66,
         EXYNOS4_GPIO_Y67,
-       EXYNOS4_GPIO_X00,               /* 256 0x100 */
+
+       /* GPIO_PART2_1 STARTS */
+       EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+       EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
         EXYNOS4_GPIO_X01,
         EXYNOS4_GPIO_X02,
         EXYNOS4_GPIO_X03,

@@ -318,8 +321,8 @@ enum exynos4_gpio_pin {
         EXYNOS4_GPIO_X37,
 
         /* GPIO_PART3_STARTS */
-       EXYNOS4_GPIO_MAX_PORT_PART_2,   /* 288 0x120 */
-       EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+       EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+       EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
         EXYNOS4_GPIO_Z1,
         EXYNOS4_GPIO_Z2,
         EXYNOS4_GPIO_Z3,

@@ -332,7 +335,7 @@ enum exynos4_gpio_pin {
  };
 
  enum exynos4X12_gpio_pin {
-       /* GPIO_PART1_STARTS */
+       /* EXYNOS4X12_GPIO_PART1_0 starts here */
         EXYNOS4X12_GPIO_A00,            /* 0 */
         EXYNOS4X12_GPIO_A01,
         EXYNOS4X12_GPIO_A02,

@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin {
         EXYNOS4X12_GPIO_D15,
         EXYNOS4X12_GPIO_D16,
         EXYNOS4X12_GPIO_D17,
-       EXYNOS4X12_GPIO_F00,            /* 56 0x38 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+       /* EXYNOS4X12_GPIO_PART1_1 starts here */
+       EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
         EXYNOS4X12_GPIO_F01,
         EXYNOS4X12_GPIO_F02,
         EXYNOS4X12_GPIO_F03,

@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin {
         EXYNOS4X12_GPIO_F35,
         EXYNOS4X12_GPIO_F36,
         EXYNOS4X12_GPIO_F37,
-       EXYNOS4X12_GPIO_J00,            /* 88 0x58 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+       /* EXYNOS4X12_GPIO_PART1_2 starts here */
+       EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
         EXYNOS4X12_GPIO_J01,
         EXYNOS4X12_GPIO_J02,
         EXYNOS4X12_GPIO_J03,

@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin {
         EXYNOS4X12_GPIO_J16,
         EXYNOS4X12_GPIO_J17,
 
-       /* GPIO_PART2_STARTS */
-       EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
-       EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
+       /**
+        * EXYNOS4X12_GPIO_PART2_0 is not used
+        * EXYNOS4X12_GPIO_PART2_1 starts here
+        */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+       EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
         EXYNOS4X12_GPIO_K01,
         EXYNOS4X12_GPIO_K02,
         EXYNOS4X12_GPIO_K03,

@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin {
         EXYNOS4X12_GPIO_Y65,
         EXYNOS4X12_GPIO_Y66,
         EXYNOS4X12_GPIO_Y67,
-       EXYNOS4X12_GPIO_M00,            /* 216 0xd8 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+       /* EXYNOS4X12_GPIO_PART2_2 starts here */
+       EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
         EXYNOS4X12_GPIO_M01,
         EXYNOS4X12_GPIO_M02,
         EXYNOS4X12_GPIO_M03,

@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin {
         EXYNOS4X12_GPIO_M45,
         EXYNOS4X12_GPIO_M46,
         EXYNOS4X12_GPIO_M47,
-       EXYNOS4X12_GPIO_X00,            /* 256 0x100 */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+       /* EXYNOS4X12_GPIO_PART2_3 starts here */
+       EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
         EXYNOS4X12_GPIO_X01,
         EXYNOS4X12_GPIO_X02,
         EXYNOS4X12_GPIO_X03,

@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin {
         EXYNOS4X12_GPIO_X36,
         EXYNOS4X12_GPIO_X37,
 
-       /* GPIO_PART3_STARTS */
-       EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
-       EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+       /* EXYNOS4X12_GPIO_PART3 starts here */
+       EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+       EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
         EXYNOS4X12_GPIO_Z1,
         EXYNOS4X12_GPIO_Z2,
         EXYNOS4X12_GPIO_Z3,

@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin {
         EXYNOS4X12_GPIO_Z6,
         EXYNOS4X12_GPIO_Z7,
 
-       /* GPIO_PART4_STARTS */
+       /* EXYNOS4X12_GPIO_PART4 starts here */
         EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
         EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
         EXYNOS4X12_GPIO_V01,

@@ -1339,17 +1353,22 @@ struct gpio_info {
         unsigned int max_gpio;  /* Maximum GPIO in this part */
  };
 
-#define EXYNOS4_GPIO_NUM_PARTS 3
+#define EXYNOS4_GPIO_NUM_PARTS 4
  static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
         { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
-       { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+       { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+       { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
         { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
  };
 

arch/arm/include/asm/arch-exynos/gpio.h struct gpio_info { · line 1371

Quoted 11 lines

arch/arm/include/asm/arch-exynos/gpio.h +7 -3

-#define EXYNOS4X12_GPIO_NUM_PARTS      4
+#define EXYNOS4X12_GPIO_NUM_PARTS      8
  static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
-       { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
-       { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+       { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+       { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+       { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+       { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+       { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+       { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },

Again I wonder if we can just number these 0 to 7?

Quoted 6 lines

arch/arm/include/asm/arch-exynos/gpio.h +0 -1

         { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
         { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
  };
--

1.9.1

Regards,
Simon

The pinctrl dts was imported from the kernel, but the order of GPM and GPY is wrong. The gpio enum in: asm/arch/gpio.h is proper.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 5 lines · Przemyslaw Marczak

The pinctrl dts was imported from the kernel, but the order of GPM and GPY is wrong. The gpio enum in: asm/arch/gpio.h is proper.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

The gpf0 offset was bad and it's now fixed.
After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 4 lines · Przemyslaw Marczak

The gpf0 offset was bad and it's now fixed.
After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

The gpy0 don't need any additional register offset, but the gpx0 does, so now it is fixed.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 4 lines · Przemyslaw Marczak

The gpy0 don't need any additional register offset, but the gpx0 does, so now it is fixed.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 1 line

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  board/samsung/universal_c210/universal.c | 24 ++++++++++++++++++++++++
  1 file changed, 24 insertions(+)

board/samsung/universal_c210/universal.c +17 -0

index c04f48c..b53def8 100644
@@ -204,6 +204,21 @@ int exynos_early_init_f(void)
  #ifdef CONFIG_SOFT_SPI
  static void soft_spi_init(void)
  {
+	char buf[16];
+
+	/* Reserve gpios for soft SPI */
+	sprintf(buf, "soft_spi_sclk");
+	gpio_request(CONFIG_SOFT_SPI_GPIO_SCLK, buf);
+
+	sprintf(buf, "soft_spi_mosi");
+	gpio_request(CONFIG_SOFT_SPI_GPIO_MOSI, buf);
+
+	sprintf(buf, "soft_spi_miso");
+	gpio_request(CONFIG_SOFT_SPI_GPIO_MISO, buf);
+
+	sprintf(buf, "soft_spi_cs");
+	gpio_request(CONFIG_SOFT_SPI_GPIO_CS, buf);
+
  	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
  		CONFIG_SOFT_SPI_MODE & SPI_CPOL);
  	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);

@@ -377,6 +392,8 @@ void exynos_enable_ldo(unsigned int onoff)
 
  int exynos_init(void)
  {
+	char buf[16];
+
  	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
 
  	switch (get_hwrev()) {

@@ -401,6 +418,13 @@ int exynos_init(void)
  		break;
  	}
 

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 4 lines · Przemyslaw Marczak

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 4 lines · Przemyslaw Marczak

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 4 lines · Przemyslaw Marczak

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 4 lines · Przemyslaw Marczak

There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

Odroid is based on Exynos4412.

Signed-off-by Przemyslaw Marczak <[email protected]>

Quoted 3 lines · Przemyslaw Marczak

Odroid is based on Exynos4412.

Signed-off-by Przemyslaw Marczak <[email protected]>

Acked-by Simon Glass <[email protected]>

Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.

Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 board/samsung/odroid/odroid.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

board/samsung/odroid/odroid.c +0 -0

index 5edb250..5ce8e9f 100644

board/samsung/odroid/odroid.c +12 -2

+
        gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
        gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
        gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
 
        /* Enable FAN (Odroid U3) */
+       sprintf(buf, "FAN Control");
+       gpio_request(EXYNOS4X12_GPIO_D00, buf);
+
        gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
        gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
        gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
 
        /* OTG Vbus output (Odroid U3+) */
+       sprintf(buf, "OTG Vbus");
+       gpio_request(EXYNOS4X12_GPIO_L20, buf);
+
        gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
        gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
        gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
 
        /* OTG INT (Odroid U3+) */
+       sprintf(buf, "OTG INT");
+       gpio_request(EXYNOS4X12_GPIO_X31, buf);
+
        gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
        gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
        gpio_direction_input(EXYNOS4X12_GPIO_X31);

@@ -403,7 +417,6 @@ static void board_init_i2c(void)
 int exynos_early_init_f(void)
 {
        board_clock_init();
-       board_gpio_init();
 
        return 0;
 }

@@ -414,6 +427,8 @@ int exynos_init(void)
        gd->ram_size -= SZ_1M;
        gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
 
+       board_gpio_init();
+
        return 0;
 }
 
--

1.9.1

Hi,

Quoted 16 lines · Przemyslaw Marczak

Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.

Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  board/samsung/odroid/odroid.c | 17 ++++++++++++++++-
  1 file changed, 16 insertions(+), 1 deletion(-)

board/samsung/odroid/odroid.c +0 -0

index 5edb250..5ce8e9f 100644

board/samsung/odroid/odroid.c static void board_clock_init(void) · line 362

Quoted 8 lines

board/samsung/odroid/odroid.c +4 -0

@@ -355,22 +355,36 @@ static void board_clock_init(void)
 
  static void board_gpio_init(void)
  {
+       char buf[16];
+
         /* eMMC Reset Pin */
+       sprintf(buf, "eMMC Reset");
+       gpio_request(EXYNOS4X12_GPIO_K12, buf);

You can use:

gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");

Same below.

Quoted 45 lines

board/samsung/odroid/odroid.c +12 -1

+
         gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
         gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
         gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
 
         /* Enable FAN (Odroid U3) */
+       sprintf(buf, "FAN Control");
+       gpio_request(EXYNOS4X12_GPIO_D00, buf);
+
         gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
         gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
         gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
 
         /* OTG Vbus output (Odroid U3+) */
+       sprintf(buf, "OTG Vbus");
+       gpio_request(EXYNOS4X12_GPIO_L20, buf);
+
         gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
         gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
         gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
 
         /* OTG INT (Odroid U3+) */
+       sprintf(buf, "OTG INT");
+       gpio_request(EXYNOS4X12_GPIO_X31, buf);
+
         gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
         gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
         gpio_direction_input(EXYNOS4X12_GPIO_X31);

@@ -403,7 +417,6 @@ static void board_init_i2c(void)
  int exynos_early_init_f(void)
  {
         board_clock_init();
-       board_gpio_init();
 
         return 0;
  }

@@ -414,6 +427,8 @@ int exynos_init(void)
         gd->ram_size -= SZ_1M;
         gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
 
+       board_gpio_init();
+
         return 0;
  }
 

Quoted 3 lines

--
1.9.1

Regards,
Simon

Hello Simon, Tom,

The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.

So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.

The patchset was rebased on the top of u-boot-dm/master, which is now:
c2ded96 serial: remove uniphier_serial_initialize() call

Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)

Best Regards,
Przemyslaw Marczak

Przemyslaw Marczak (14):
mmc: s5p: set SD detection pin as input
exynos: common: enable generic fs operations exynos4/4x12: cpu: add extra gpio base addresses exynos4/4x12: gpio: use gpio extra base addresses
exynos4412: dts: fix bad gpio order in pinctrl
exynos4412: dts: adjust pinctrl-uboot to changed gpio order
exynos4210: dts: fix gpio offset in pinctrl-uboot
universal: request soft i2c gpio
universal: dts: adjust gpio numbers to new api
trats: dts: adjust gpio numbers to new api
trats2: dts: adjust gpio numbers after gpio rework
odroid: dts: adjust sd cd-gpios for SD Card
odroid: dts: fix name of included dtsi
odroid: adjust gpio calls to dm gpio api

  arch/arm/dts/exynos4210-pinctrl-uboot.dtsi |  2 +-
  arch/arm/dts/exynos4210-trats.dts          |  4 +-
  arch/arm/dts/exynos4210-universal_c210.dts |  4 +-
  arch/arm/dts/exynos4412-odroid.dts         |  4 +-
  arch/arm/dts/exynos4412-trats2.dts         |  6 +--
  arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi |  5 +--
  arch/arm/dts/exynos4x12-pinctrl.dtsi       | 54 +++++++++++++--------------
  arch/arm/include/asm/arch-exynos/cpu.h     |  9 +++++
  arch/arm/include/asm/arch-exynos/gpio.h    | 59 ++++++++++++++++++++----------
  board/samsung/odroid/odroid.c              | 17 ++++++++-
  board/samsung/universal_c210/universal.c   |  9 +++++
  drivers/mmc/s5p_sdhci.c                    |  2 +-
  include/configs/exynos-common.h            |  1 +
  13 files changed, 113 insertions(+), 63 deletions(-)

Hello Simon, Tom,

The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.

So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.

The patchset was rebased on the top of u-boot-dm/master, which is now:
c2ded96 serial: remove uniphier_serial_initialize() call

Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)

Hi Przemyslaw,

Quoted 12 lines · Przemyslaw Marczak

Hello Simon, Tom,

The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.

So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.

The patchset was rebased on the top of u-boot-dm/master, which is now:
c2ded96 serial: remove uniphier_serial_initialize() call

Quoted 6 lines

Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)

Actually I never did update the device tree numbering so I suspect this series has been incorrect since version 1! Since exynos5 was always sequential I somehow missing thinking about it. This is great, thanks for straightening it all out and testing. Particularly I am pleased about Universal since the soft SPI was a bit of a poke in the dark.

I'll go through this soon. I was also planning to send a patch to clean up some of the gpio_name_num_table stuff since it shouldn't be needed any more.

Hi Przemyslaw,

Quoted 12 lines · Przemyslaw Marczak

Hello Simon, Tom,

The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.

So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.

The patchset was rebased on the top of u-boot-dm/master, which is now:
c2ded96 serial: remove uniphier_serial_initialize() call

Quoted 6 lines

Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)

Actually I never did update the device tree numbering so I suspect this series has been incorrect since version 1! Since exynos5 was always sequential I somehow missing thinking about it. This is great, thanks for straightening it all out and testing. Particularly I am pleased about Universal since the soft SPI was a bit of a poke in the dark.

I'll go through this soon. I was also planning to send a patch to clean up some of the gpio_name_num_table stuff since it shouldn't be needed any more.

Regards,
Simon

After remove the offsets in Exynos4/4x12 gpio enums, an additional gpio base addresses are required.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++
  1 file changed, 9 insertions(+)

arch/arm/include/asm/arch-exynos/cpu.h +3 -0

index ba71714..78aceef 100644
@@ -29,6 +29,8 @@
  #define EXYNOS4_MIU_BASE		0x10600000
  #define EXYNOS4_ACE_SFR_BASE		0x10830000
  #define EXYNOS4_GPIO_PART2_BASE		0x11000000
+#define EXYNOS4_GPIO_PART2_0		0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1		0x11000c00 /* GPX0 */
  #define EXYNOS4_GPIO_PART1_BASE		0x11400000
  #define EXYNOS4_FIMD_BASE		0x11C00000
  #define EXYNOS4_MIPI_DSIM_BASE		0x11C80000

@@ -70,7 +72,14 @@
  #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
  #define EXYNOS4X12_ACE_SFR_BASE		0x10830000
  #define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
+#define EXYNOS4X12_GPIO_PART2_0		0x11000000

This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear

Signed-off-by Przemyslaw Marczak <[email protected]>

This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++-----------
 1 file changed, 39 insertions(+), 20 deletions(-)

Quoted 9 lines · Przemyslaw Marczak

This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++-----------
  1 file changed, 39 insertions(+), 20 deletions(-)

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

Hello Minkyu,

Quoted 11 lines · Minkyu Kang

Quoted 9 lines · Przemyslaw Marczak

This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear

Signed-off-by Przemyslaw Marczak <[email protected]>

---
  arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++-----------
  1 file changed, 39 insertions(+), 20 deletions(-)

Quoted 5 lines

applied to u-boot-samsung.

Thanks,
Minkyu Kang.

I thought that those patches will go through u-boot-dm, since it was a second version of some not merged V1 patches.

Now, the u-boot-dm/master and u-boot/master are broken for exynos4 because of missing those few patches.

Could you please make a pull request with those patches asap?

Best regards,

Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.

Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 board/samsung/odroid/odroid.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

board/samsung/odroid/odroid.c +0 -0

index 5edb250..33003ee 100644

board/samsung/odroid/odroid.c +9 -2

+
        gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
        gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
        gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
 
        /* Enable FAN (Odroid U3) */
+       gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
+
        gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
        gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
        gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
 
        /* OTG Vbus output (Odroid U3+) */
+       gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
+
        gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
        gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
        gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
 
        /* OTG INT (Odroid U3+) */
+       gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
+
        gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
        gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
        gpio_direction_input(EXYNOS4X12_GPIO_X31);

@@ -403,7 +411,6 @@ static void board_init_i2c(void)
 int exynos_early_init_f(void)
 {
        board_clock_init();
-       board_gpio_init();
 
        return 0;
 }

@@ -414,6 +421,8 @@ int exynos_init(void)
        gd->ram_size -= SZ_1M;
        gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
 
+       board_gpio_init();
+
        return 0;
 }
 
--

1.9.1

Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.

Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 board/samsung/odroid/odroid.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

After remove the offsets in Exynos4/4x12 gpio enums, an additional gpio base addresses are required.

Signed-off-by Przemyslaw Marczak <[email protected]>

After remove the offsets in Exynos4/4x12 gpio enums, an additional gpio base addresses are required.

Signed-off-by Przemyslaw Marczak <[email protected]>

---
 arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++
 1 file changed, 9 insertions(+)