omap gpmc and board clean-up for v3.19 merge window

Apparently some versions of nolo don't mux the necessary GPMC pins for the smc91x probe to work properly. Let's fix this issue by adding mux support for GPMC to the kernel.

Note that it's unclear why the GPMC clk pin has input enabled, but let's not touch that as in general the mux settings in nolo are correct.

Cc Kevin Hilman <[email protected]>

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

---
 arch/arm/boot/dts/omap3-n900.dts | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

arch/arm/boot/dts/omap3-n900.dts +14 -0

index 739fcf2..e7210d1 100644
@@ -142,6 +142,33 @@
 		>;
 	};
 
+	gpmc_pins: pinmux_gpmc_pins {
+		pinctrl-single,pins = <
+
+			/* address lines */
+                        OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a1.gpmc_a1 */
+                        OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a2.gpmc_a2 */
+                        OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a3.gpmc_a3 */
+
+			/* data lines, gpmc_d0..d7 not muxable according to TRM */
+                        OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0)        /* gpmc_d8.gpmc_d8 */
+                        OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0)        /* gpmc_d9.gpmc_d9 */
+                        OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0)        /* gpmc_d10.gpmc_d10 */
+                        OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0)        /* gpmc_d11.gpmc_d11 */
+                        OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0)        /* gpmc_d12.gpmc_d12 */

arch/arm/boot/dts/omap3-n900.dts +5 -0

+		>;
+	};
+
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
 			0x18a (PIN_INPUT | MUX_MODE0)		/* i2c1_scl */

@@ -588,6 +615,8 @@
 	ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
 	ranges = <0 0 0x01000000 0x01000000>,	/* 16 MB for OneNAND */
 		 <1 0 0x02000000 0x01000000>;	/* 16 MB for smc91c96 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpmc_pins>;
 
 	/* gpio-irq for dma: 65 */
 

Review

Quoted 7 lines · Tony Lindgren

(quoted diff) +7 -0

+
+			/*
+			 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
+			 * according to TRM. REVISIT: why does nolo set input for gpmc_clk?
+			 */
+                        OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs1.gpmc_ncs1 */
+                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */

Right about the comment. GPMC_CLK should feed the CLK input of the OneNAND. This needs to be an OUTPUT pin.

Does OneNAND work when this pin is configured as output?

Quoted 12 lines · Roger Quadros

arch/arm/boot/dts/omap3-n900.dts line 168

Quoted 7 lines · Tony Lindgren

arch/arm/boot/dts/omap3-n900.dts +7 -0

+
+			/*
+			 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
+			 * according to TRM. REVISIT: why does nolo set input for gpmc_clk?
+			 */
+                        OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs1.gpmc_ncs1 */
+                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */

Right about the comment. GPMC_CLK should feed the CLK input of the OneNAND. This needs to be an OUTPUT pin.

Quoted 1 line

Does OneNAND work when this pin is configured as output?

Does not seem to work, it produces onenand_wait: ECC error = 0xffff.

It seems the clock needs to be copied to GPMC too in some cases. For MMC, there's the MMCSDIO2ADPCLKISEL option to copy the clock to account for level shifter latencies [1]. But in the OneNAND case I don't think there are any level shifters, and I don't think we have "copy clock" option for GPMC either in SCM so it somehow is automatic in GPMC.

Anyways, updated patch below with wrong guessing removed.

Regards,

Tony

[1] http://processors.wiki.ti.com/index.php/SD-MMC_Usage_Notes_on_OMAP35x_and_AM37x

8< --------------------
From: Tony Lindgren <[email protected]>
Date: Wed, 29 Oct 2014 17:16:47 -0700
Subject: [PATCH] ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins

Apparently some versions of nolo don't mux the all the necessary GPMC pins for the smc91x probe to work properly. Let's fix this issue by adding mux support for GPMC to the kernel.

Note that GPMC clk needs input enabled for OnenNAND to work.

Cc Kevin Hilman <[email protected]>

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

The GPMC binding is obviously very confusing as the values are all over the place. People seem to confuse the GPMC partition size for the chip select, and the device IO size within the GPMC partition easily.

The ranges entry contains the GPMC partition size. And the reg entry contains the size of the IO registers of the device connected to the GPMC.

Let's fix the issue according to the following table:

Device          GPMC partition size     Device IO size
connected       in the ranges entry     in the reg entry

NAND            0x01000000 (16MB)       4
16550           0x01000000 (16MB)       8
smc91x          0x01000000 (16MB)       0xf
smc911x         0x01000000 (16MB)       0xff
OneNAND         0x01000000 (16MB)       0x20000 (128KB)
16MB NOR        0x01000000 (16MB)       0x01000000 (16MB)
32MB NOR        0x02000000 (32MB)       0x02000000 (32MB)
64MB NOR        0x04000000 (64MB)       0x04000000 (64MB)
128MB NOR       0x08000000 (128MB)      0x08000000 (128MB)
256MB NOR       0x10000000 (256MB)      0x10000000 (256MB)

Let's also add comments to the fixed entries while at it.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

The four port serial port on the zoom debug board uses a TL16CP754C with a single interrupt and GPMC chip select. The serial ports each use a 8 bytes for IO registers, and are 256 bytes apart on the GPMC line.

Let's add timings for all four ports so we can remove the GPMC workarounds for using bootloader timings.

Not caused by this patch, but looks like u-boot only properly initializes the fifo on the first serial port. Currently the other ports produce garbage at least with my version of u-boot. I suspect that TL16CP754C needs non-standard initialization added to 8250 driver to properly fix this issue.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

---
 arch/arm/boot/dts/omap-zoom-common.dtsi | 58 +++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

arch/arm/boot/dts/omap-zoom-common.dtsi +58 -0

index 2889b50..46ef3e4 100644
@@ -23,6 +23,64 @@
 		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
 		clock-frequency = <1843200>;
 		current-speed = <115200>;
+		gpmc,mux-add-data = <0>;
+		gpmc,device-width = <1>;
+		gpmc,wait-pin = <1>;
+		gpmc,cycle2cycle-samecsen = <1>;
+		gpmc,cycle2cycle-diffcsen = <1>;
+		gpmc,cs-on-ns = <5>;
+		gpmc,cs-rd-off-ns = <155>;
+		gpmc,cs-wr-off-ns = <155>;
+		gpmc,adv-on-ns = <15>;
+		gpmc,adv-rd-off-ns = <40>;
+		gpmc,adv-wr-off-ns = <40>;
+		gpmc,oe-on-ns = <45>;
+		gpmc,oe-off-ns = <145>;
+		gpmc,we-on-ns = <45>;
+		gpmc,we-off-ns = <145>;
+		gpmc,rd-cycle-ns = <155>;
+		gpmc,wr-cycle-ns = <155>;
+		gpmc,access-ns = <145>;
+		gpmc,page-burst-access-ns = <20>;
+		gpmc,bus-turnaround-ns = <20>;
+		gpmc,cycle2cycle-delay-ns = <20>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <45>;
+		gpmc,wr-access-ns = <145>;
+	};
+	uart at 3,1 {
+		compatible = "ns16550a";
+		reg = <3 0x100 8>;	/* CS3, offset 0x100, IO size 8 */
+		bank-width = <2>;
+		reg-shift = <1>;
+		reg-io-width = <1>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
+		clock-frequency = <1843200>;
+		current-speed = <115200>;
+	};
+	uart at 3,2 {
+		compatible = "ns16550a";
+		reg = <3 0x200 8>;	/* CS3, offset 0x200, IO size 8 */
+		bank-width = <2>;
+		reg-shift = <1>;
+		reg-io-width = <1>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
+		clock-frequency = <1843200>;
+		current-speed = <115200>;
+	};
+	uart at 3,3 {
+		compatible = "ns16550a";
+		reg = <3 0x300 8>;	/* CS3, offset 0x300, IO size 8 */
+		bank-width = <2>;
+		reg-shift = <1>;
+		reg-io-width = <1>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
+		clock-frequency = <1843200>;
+		current-speed = <115200>;
 	};
 
 	ethernet at gpmc {

There are cases where we have multiple device instances connected to a single GPMC chip select. For example, there are four UARTs on the Zoom debug boards that all share a single chip select and a GPIO interrupt.

We do have support for this already in theory, but it's broken because we're bailing out if the chip select is already taken.

To be able to provide checks on the chip select usage, let's add new struct gpmc_cs_data so we can start using already registered device names for checks.

Later on we probably want to start using struct gpmc_cs_data as a wrapper for all the GPMC chipselect related data.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

As we still have some devices with GPMC timings missing from the .dts files, let's make it a bit easier to use the bootloader values and print them out.

Note that we now need to move the parsing of the device tree provided configuration a bit earlier so we can use that for checking if anything was configured.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

---
 arch/arm/mach-omap2/gpmc.c | 141 +++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 137 insertions(+), 4 deletions(-)

arch/arm/mach-omap2/gpmc.c +61 -0

index 2c5f348..0999923 100644
@@ -291,6 +291,123 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 			   p->cycle2cyclediffcsen);
 }
 
+static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
+			       bool raw, bool noval, int shift,
+			       const char *name)
+{
+	u32 l;
+	int nr_bits, max_value, mask;
+
+	l = gpmc_cs_read_reg(cs, reg);
+	nr_bits = end_bit - st_bit + 1;
+	max_value = (1 << nr_bits) - 1;
+	mask = max_value << st_bit;
+	l = (l & mask) >> st_bit;
+	if (shift)
+		l <<= shift;
+	if (noval && (l == 0))
+		return 0;
+	if (!raw) {
+		unsigned int time_ns_min, time_ns, time_ns_max;
+
+		time_ns_min = gpmc_ticks_to_ns(l ? l - 1 : 0);
+		time_ns = gpmc_ticks_to_ns(l);
+		time_ns_max = gpmc_ticks_to_ns(l + 1 > max_value ?
+					       max_value : l + 1);
+		pr_info("gpmc,%s = <%u> (%u - %u ns, %i ticks)\n",
+			name, time_ns, time_ns_min, time_ns_max, l);
+	} else {
+		pr_info("gpmc,%s = <%u>\n", name, l);
+	}
+
+	return l;
+}
+
+#define GPMC_PRINT_CONFIG(cs, config) \
+	pr_info("cs%i %s: 0x%08x\n", cs, #config, \
+		gpmc_cs_read_reg(cs, config))
+#define GPMC_GET_RAW(reg, st, end, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
+#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
+#define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
+#define GPMC_GET_TICKS(reg, st, end, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
+
+static void gpmc_show_regs(int cs, const char *desc)
+{
+	pr_info("gpmc cs%i %s:\n", cs, desc);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
+}
+
+/*
+ * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
+ * see commit c9fb809.
+ */
+static void gpmc_cs_show_timings(int cs, const char *desc)
+{

arch/arm/mach-omap2/gpmc.c +36 -0

+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
+
+	pr_info("gpmc cs%i timings configuration:\n", cs);
+	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
+

arch/arm/mach-omap2/gpmc.c +20 -3

 #ifdef DEBUG
 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 			       int time, const char *name)

@@ -361,6 +478,9 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 	int div;
 	u32 l;
 
+#ifdef DEBUG
+	gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
+#endif
 	div = gpmc_calc_divider(t->sync_clk);
 	if (div < 0)
 		return div;

@@ -410,7 +530,9 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 	}
 
 	gpmc_cs_bool_timings(cs, &t->bool_timings);
-
+#ifdef DEBUG
+	gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
+#endif
 	return 0;
 }
 

@@ -1571,6 +1693,20 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
 	}
 	gpmc_cs_set_name(cs, child->name);
 
+	gpmc_read_settings_dt(child, &gpmc_s);
+	gpmc_read_timings_dt(child, &gpmc_t);
+
+	/*
+	 * For some GPMC devices we still need to rely on the bootloader
+	 * timings because the devices can be connected via FPGA.
+	 * REVISIT: Add timing support from slls644g.pdf.
+	 */
+	if (!gpmc_t.cs_rd_off) {
+		gpmc_cs_show_timings(cs,
+				     "please add GPMC bootloader timings to .dts");
+		goto no_timings;
+	}
+
 	/*
 	 * For some GPMC devices we still need to rely on the bootloader
 	 * timings because the devices can be connected via FPGA. So far

@@ -1602,8 +1738,6 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
 		goto err;
 	}
 
-	gpmc_read_settings_dt(child, &gpmc_s);
-
 	ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
 	if (ret < 0)
 		goto err;

Quoted 10 lines · Tony Lindgren

arch/arm/mach-omap2/gpmc.c +10 -0

+static void gpmc_cs_show_timings(int cs, const char *desc)
+{
+	gpmc_show_regs(cs, desc);
+
+	pr_info("gpmc cs%i access configuration:\n", cs);
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");

arch/arm/mach-omap2/gpmc.c static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) · line 364

Quoted 2 lines

arch/arm/mach-omap2/gpmc.c +2 -0

+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
+	GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 3, "burst-length");

how does this work with shift = 3?
Possible values of burst length are
0 -> 4
1 -> 8
2 -> 16

Shouldn't all the above functions except gpmc_show_regs() be defined within #ifdef DEBUG?

Quoted 11 lines · Roger Quadros

Quoted 10 lines · Tony Lindgren

arch/arm/mach-omap2/gpmc.c +10 -0

+static void gpmc_cs_show_timings(int cs, const char *desc)
+{
+	gpmc_show_regs(cs, desc);
+
+	pr_info("gpmc cs%i access configuration:\n", cs);
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");

Quoted 8 lines

arch/arm/mach-omap2/gpmc.c static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) · line 364

Quoted 2 lines

arch/arm/mach-omap2/gpmc.c +2 -0

+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
+	GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 3, "burst-length");

how does this work with shift = 3?
Possible values of burst length are
0 -> 4
1 -> 8
2 -> 16

Hmm sounds like a bug..

In general, if you a chance to test this patch with a few devices that would be great. Assuming you have working timings in the bootloader, just remove the gpmc,* entries temporarily from the .dts file for a device, and see if the values printed by this patch make sense. I've used this to generate the values for the 2430sdp smc91x and zoom 8250 but I don't think I've tried anything with a burst mode so far.

Quoted 2 lines

Shouldn't all the above functions except gpmc_show_regs() be defined within #ifdef DEBUG?

Yes let's do that to avoid bloat. Let's do a warning if no timings are specified so people know to enable DEBUG.

BTW, I'm hoping we can start using gpmc_probe_generic_child() for all the devices and get rid of gpmc_probe_nand_child() and gpmc_probe_onenand_child(). We can now use gpmc_cs_get_name() to call helpers from gpmc_probe_generic_child() for NAND and OneNAND if really needed.

Quoted 21 lines · Tony Lindgren

Quoted 19 lines · Roger Quadros

Review

Quoted 12 lines · Tony Lindgren

(quoted diff) +12 -0

+static void gpmc_cs_show_timings(int cs, const char *desc)
+{
+	gpmc_show_regs(cs, desc);
+
+	pr_info("gpmc cs%i access configuration:\n", cs);
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
+	GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 3, "burst-length");

how does this work with shift = 3?
Possible values of burst length are
0 -> 4
1 -> 8
2 -> 16

Quoted 1 line

Hmm sounds like a bug..

Quoted 7 lines

In general, if you a chance to test this patch with a few devices that would be great. Assuming you have working timings in the bootloader, just remove the gpmc,* entries temporarily from the .dts file for a device, and see if the values printed by this patch make sense. I've used this to generate the values for the 2430sdp smc91x and zoom 8250 but I don't think I've tried anything with a burst mode so far.

OK. I'll give it a spin with u-boot configured devices.

Quoted 22 lines · Roger Quadros

Quoted 21 lines · Tony Lindgren

Quoted 19 lines · Roger Quadros

arch/arm/mach-omap2/gpmc.c static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)

Quoted 12 lines · Tony Lindgren

arch/arm/mach-omap2/gpmc.c +12 -0

+static void gpmc_cs_show_timings(int cs, const char *desc)
+{
+	gpmc_show_regs(cs, desc);
+
+	pr_info("gpmc cs%i access configuration:\n", cs);
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
+	GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 3, "burst-length");

how does this work with shift = 3?
Possible values of burst length are
0 -> 4
1 -> 8
2 -> 16

Quoted 1 line

Quoted 1 line

Hmm sounds like a bug..

The shift does not work here for 0 << 3 naturally :) I've changed it to l = (shift << l) where shift is 4 in this case.

Quoted 9 lines

Quoted 7 lines

In general, if you a chance to test this patch with a few devices that would be great. Assuming you have working timings in the bootloader, just remove the gpmc,* entries temporarily from the .dts file for a device, and see if the values printed by this patch make sense. I've used this to generate the values for the 2430sdp smc91x and zoom 8250 but I don't think I've tried anything with a burst mode so far.

OK. I'll give it a spin with u-boot configured devices.

Great thanks. Updated patch below.

Regards,

Tony

8< ----------------
From: Tony Lindgren <[email protected]>
Date: Wed, 29 Oct 2014 17:16:48 -0700
Subject: [PATCH] ARM: OMAP2+: Show bootloader GPMC timings to allow configuring the .dts file

As we still have some devices with GPMC timings missing from the .dts files, let's make it a bit easier to use the bootloader values and print them out.

Note that we now need to move the parsing of the device tree provided configuration a bit earlier so we can use that for checking if anything was configured.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

Quoted 22 lines · Roger Quadros

Quoted 21 lines · Tony Lindgren

Quoted 19 lines · Roger Quadros

arch/arm/mach-omap2/gpmc.c static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)

Quoted 12 lines · Tony Lindgren

arch/arm/mach-omap2/gpmc.c +12 -0

+static void gpmc_cs_show_timings(int cs, const char *desc)
+{
+	gpmc_show_regs(cs, desc);
+
+	pr_info("gpmc cs%i access configuration:\n", cs);
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
+	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
+	GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 3, "burst-length");

how does this work with shift = 3?
Possible values of burst length are
0 -> 4
1 -> 8
2 -> 16

Quoted 1 line

Quoted 1 line

Hmm sounds like a bug..

The shift does not work here for 0 << 3 naturally :) I've changed it to l = (shift << l) where shift is 4 in this case.

Quoted 9 lines

Quoted 7 lines

In general, if you a chance to test this patch with a few devices that would be great. Assuming you have working timings in the bootloader, just remove the gpmc,* entries temporarily from the .dts file for a device, and see if the values printed by this patch make sense. I've used this to generate the values for the 2430sdp smc91x and zoom 8250 but I don't think I've tried anything with a burst mode so far.

OK. I'll give it a spin with u-boot configured devices.

Great thanks. Updated patch below.

Regards,

Tony

8< ----------------
From: Tony Lindgren <[email protected]>
Date: Wed, 29 Oct 2014 17:16:48 -0700
Subject: [PATCH] ARM: OMAP2+: Show bootloader GPMC timings to allow configuring the .dts file

As we still have some devices with GPMC timings missing from the .dts files, let's make it a bit easier to use the bootloader values and print them out.

Note that we now need to move the parsing of the device tree provided configuration a bit earlier so we can use that for checking if anything was configured.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

I don't have any board with smsc or working NOR so I called gpmc_cs_show_timings() after NAND was setup.

The printed values match closely to the configured values in the DTS.

As we still have some devices with GPMC timings missing from the .dts files, let's make it a bit easier to use the bootloader values and print them out.

Note that we now need to move the parsing of the device tree provided configuration a bit earlier so we can use that for checking if anything was configured.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

---
 arch/arm/mach-omap2/gpmc.c | 141 +++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 137 insertions(+), 4 deletions(-)

arch/arm/mach-omap2/gpmc.c +61 -0

index 2c5f348..0999923 100644
@@ -291,6 +291,123 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 			   p->cycle2cyclediffcsen);
 }
 
+static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
+			       bool raw, bool noval, int shift,
+			       const char *name)
+{
+	u32 l;
+	int nr_bits, max_value, mask;
+
+	l = gpmc_cs_read_reg(cs, reg);
+	nr_bits = end_bit - st_bit + 1;
+	max_value = (1 << nr_bits) - 1;
+	mask = max_value << st_bit;
+	l = (l & mask) >> st_bit;
+	if (shift)
+		l <<= shift;
+	if (noval && (l == 0))
+		return 0;
+	if (!raw) {
+		unsigned int time_ns_min, time_ns, time_ns_max;
+
+		time_ns_min = gpmc_ticks_to_ns(l ? l - 1 : 0);
+		time_ns = gpmc_ticks_to_ns(l);
+		time_ns_max = gpmc_ticks_to_ns(l + 1 > max_value ?
+					       max_value : l + 1);
+		pr_info("gpmc,%s = <%u> (%u - %u ns, %i ticks)\n",
+			name, time_ns, time_ns_min, time_ns_max, l);
+	} else {
+		pr_info("gpmc,%s = <%u>\n", name, l);
+	}
+
+	return l;
+}
+
+#define GPMC_PRINT_CONFIG(cs, config) \
+	pr_info("cs%i %s: 0x%08x\n", cs, #config, \
+		gpmc_cs_read_reg(cs, config))
+#define GPMC_GET_RAW(reg, st, end, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
+#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
+#define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
+#define GPMC_GET_TICKS(reg, st, end, field) \
+	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
+
+static void gpmc_show_regs(int cs, const char *desc)
+{
+	pr_info("gpmc cs%i %s:\n", cs, desc);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
+	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
+}
+
+/*
+ * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
+ * see commit c9fb809.
+ */
+static void gpmc_cs_show_timings(int cs, const char *desc)
+{

arch/arm/mach-omap2/gpmc.c +36 -0

+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
+
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
+	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
+
+	pr_info("gpmc cs%i timings configuration:\n", cs);
+	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
+
+	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
+

arch/arm/mach-omap2/gpmc.c +20 -3

 #ifdef DEBUG
 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 			       int time, const char *name)

@@ -361,6 +478,9 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 	int div;
 	u32 l;
 
+#ifdef DEBUG
+	gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
+#endif
 	div = gpmc_calc_divider(t->sync_clk);
 	if (div < 0)
 		return div;

@@ -410,7 +530,9 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 	}
 
 	gpmc_cs_bool_timings(cs, &t->bool_timings);
-
+#ifdef DEBUG
+	gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
+#endif
 	return 0;
 }
 

@@ -1571,6 +1693,20 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
 	}
 	gpmc_cs_set_name(cs, child->name);
 
+	gpmc_read_settings_dt(child, &gpmc_s);
+	gpmc_read_timings_dt(child, &gpmc_t);
+
+	/*
+	 * For some GPMC devices we still need to rely on the bootloader
+	 * timings because the devices can be connected via FPGA.
+	 * REVISIT: Add timing support from slls644g.pdf.
+	 */
+	if (!gpmc_t.cs_rd_off) {
+		gpmc_cs_show_timings(cs,
+				     "please add GPMC bootloader timings to .dts");
+		goto no_timings;
+	}
+
 	/*
 	 * For some GPMC devices we still need to rely on the bootloader
 	 * timings because the devices can be connected via FPGA. So far

@@ -1602,8 +1738,6 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
 		goto err;
 	}
 
-	gpmc_read_settings_dt(child, &gpmc_s);
-
 	ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
 	if (ret < 0)
 		goto err;

Now that we have timings in the .dts files for smc91x and 8250, we can remove the device specific checks and just print out the bootloader timings for devices that may not have timings in the .dts files.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>

This code was only used by 2430sdp, 3430sdp, and n900 development boards.

The 2430sdp is already device tree only, and all the users of the 3430sdp and n900 development boards are already booting in device tree mode, so we can drop the legacy smc91x support.

Cc Roger Quadros <[email protected]>

Signed-off-by Tony Lindgren <[email protected]>