drm/msm: a4xx support for msm-drm
Subsystems (4)
PATCH 1/1 drm/msm: a4xx support for msm-drm
Added a4xx GPU support.
--- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 619 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a4xx_gpu.h | 34 ++ drivers/gpu/drm/msm/adreno/adreno_device.c | 13 + drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 +- 6 files changed, 680 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_gpu.c create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_gpu.h
drivers/gpu/drm/msm/Makefile +1 -0
@@ -7,6 +7,7 @@ msm-y := \ adreno/adreno_device.o \ adreno/adreno_gpu.o \ adreno/a3xx_gpu.o \ + adreno/a4xx_gpu.o \ hdmi/hdmi.o \ hdmi/hdmi_audio.o \ hdmi/hdmi_bridge.o \
(quoted diff) +0 -0
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
new file mode 100644
index 0000000..f0edac0
drivers/gpu/drm/msm/adreno/a4xx_gpu.c new file +619 -0
619 lines not on this page · raw message
(quoted diff) +0 -0
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.h
new file mode 100644
index 0000000..0124720
drivers/gpu/drm/msm/adreno/a4xx_gpu.h new file +34 -0
@@ -0,0 +1,34 @@ +/* Copyright (c) 2014 The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#ifndef __A4XX_GPU_H__ +#define __A4XX_GPU_H__ + +#include "adreno_gpu.h" + +/* arrg, somehow fb.h is getting pulled in: */ +#undef ROP_COPY +#undef ROP_XOR + +#include "a4xx.xml.h" + +struct a4xx_gpu { +struct adreno_gpu base; +struct platform_device *pdev; + +/* if OCMEM is used for GMEM: */ +uint32_t ocmem_base; +void *ocmem_hdl; +}; +#define to_a4xx_gpu (x) container_of(x, struct a4xx_gpu, base) + +#endif /* __A4XX_GPU_H__ */
(quoted diff) +0 -0
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 7ab85af..be83dee 100644
drivers/gpu/drm/msm/adreno/adreno_device.c +2 -0
@@ -2,6 +2,8 @@* Copyright (C) 2013-2014 Red Hat * Author: Rob Clark <[email protected]> * +* Copyright (c) 2014 The Linux Foundation. All rights reserved. +* * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as
published by
* the Free Software Foundation.
@@ -28,6 +30,7 @@ MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!
module_param_named(hang_debug, hang_debug, bool, 0600);
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
+struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
static const struct adreno_info gpulist[] = {
{
@@ -54,6 +57,14 @@ static const struct adreno_info gpulist[] = {
.pfpfw = "a330_pfp.fw",
.gmem = SZ_1M,
.init = a3xx_gpu_init,
+ }, {
+ .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .revn = 420, + .name = "A420",
+ .pm4fw = "a420_pm4.fw",
+ .pfpfw = "a420_pfp.fw",
+ .gmem = (SZ_1M + SZ_512K),
+ .init = a4xx_gpu_init,
},
};
@@ -61,6 +72,8 @@ MODULE_FIRMWARE("a300_pm4.fw");
MODULE_FIRMWARE("a300_pfp.fw");
MODULE_FIRMWARE("a330_pm4.fw");
MODULE_FIRMWARE("a330_pfp.fw");
+MODULE_FIRMWARE("a420_pm4.fw");
+MODULE_FIRMWARE("a420_pfp.fw");
static inline bool _rev_match(uint8_t entry, uint8_t id) {
(quoted diff) +0 -0
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 82619b1..1fe7c8d 100644
drivers/gpu/drm/msm/adreno/adreno_gpu.c +0 -0
@@ -147,7 +147,7 @@ int adreno_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); OUT_RING(ring, submit->fence);
- if (adreno_is_a3xx(adreno_gpu)) {
+ if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
/* Flush HLSQ lazy updates to make sure there is nothing
* pending for indirect loads after the timestamp has
* passed:
(quoted diff) +0 -0
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index ec84d79..3fa06b3 100644
drivers/gpu/drm/msm/adreno/adreno_gpu.h +0 -0
@@ -225,6 +225,16 @@ static inline bool adreno_is_a330v2(struct
adreno_gpu *gpu)
return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
}
+static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
+{
+ return (gpu->revn >= 400) && (gpu->revn < 500);
+}
+
+static inline int adreno_is_a420(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 420;
+}
+
int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); int adreno_hw_init(struct msm_gpu *gpu);
uint32_t adreno_last_fence(struct msm_gpu *gpu);
@@ -289,8 +299,8 @@ static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
{
u32 reg = gpu->reg_offsets->offsets[offset_name];
u32 val = 0;
- if(adreno_reg_check(gpu,offset_name))
- val = gpu_read(&gpu->base,reg);
+ if(adreno_reg_check(gpu, offset_name))
+ val = gpu_read(&gpu->base, reg);
return val;
}
Signature · 6 lines
1.8.5.2 -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Hey Aravind,
Just a couple quick comments (inline below).. overall patchset looks to be in reasonably good shape. It would be nice if you could resend and CC [email protected].. and format-patch as a patchset (so subject lines have the "[PATCH x/y]" since things don't always show up in the inbox in FIFO order). I'll have a closer look and may have a minor nit-pick or two, but the overall structure of things in the patchset looks good.
Quoted 20 lines · Aravind
Added a4xx GPU support.
Signed-off-by Aravind Ganesan <[email protected]>--- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 619 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a4xx_gpu.h | 34 ++ drivers/gpu/drm/msm/adreno/adreno_device.c | 13 + drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 +- 6 files changed, 680 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_gpu.c create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_gpu.hdrivers/gpu/drm/msm/adreno/a4xx_gpu.c new file +0
-0
[snip]
drivers/gpu/drm/msm/adreno/a4xx_gpu.c line 323
Quoted 13 lines
drivers/gpu/drm/msm/adreno/a4xx_gpu.c new file +13
-0+static irqreturn_t a4xx_irq (struct msm_gpu *gpu) +{ +uint32_t status; + + status =gpu_read (gpu,REG_A4XX_RBBM_INT_0_STATUS ); +DBG ("%s: Int status %08x" , gpu->name, status); + +gpu_write (gpu,REG_A4XX_RBBM_INT_CLEAR_CMD , status); + +msm_gpu_retire (gpu); + +return IRQ_HANDLED ; +}
newline pls
Quoted 71 lines
drivers/gpu/drm/msm/adreno/a4xx_gpu.c new file +71
-0+const unsigned int a4xx_registers[] = { +/* RBBM */ +0x0000 ,0x0002 ,0x0004 ,0x0021 ,0x0023 ,0x0024 ,0x0026 ,0x0026 , +0x0028 ,0x002B ,0x002E ,0x0034 ,0x0037 ,0x0044 ,0x0047 ,0x0066 , +0x0068 ,0x0095 ,0x009C ,0x0170 ,0x0174 ,0x01AF , +/* CP */ +0x0200 ,0x0233 ,0x0240 ,0x0250 ,0x04C0 ,0x04DD ,0x0500 ,0x050B , +0x0578 ,0x058F , +/* VSC */ +0x0C00 ,0x0C03 ,0x0C08 ,0x0C41 ,0x0C50 ,0x0C51 , +/* GRAS */ +0x0C80 ,0x0C81 ,0x0C88 ,0x0C8F , +/* RB */ +0x0CC0 ,0x0CC0 ,0x0CC4 ,0x0CD2 , +/* PC */ +0x0D00 ,0x0D0C ,0x0D10 ,0x0D17 ,0x0D20 ,0x0D23 , +/* VFD */ +0x0E40 ,0x0E4A , +/* VPC */ +0x0E60 ,0x0E61 ,0x0E63 ,0x0E68 , +/* UCHE */ +0x0E80 ,0x0E84 ,0x0E88 ,0x0E95 , +/* VMIDMT */ +0x1000 ,0x1000 ,0x1002 ,0x1002 ,0x1004 ,0x1004 ,0x1008 ,0x100A , +0x100C ,0x100D ,0x100F ,0x1010 ,0x1012 ,0x1016 ,0x1024 ,0x1024 , +0x1027 ,0x1027 ,0x1100 ,0x1100 ,0x1102 ,0x1102 ,0x1104 ,0x1104 , +0x1110 ,0x1110 ,0x1112 ,0x1116 ,0x1124 ,0x1124 ,0x1300 ,0x1300 , +0x1380 ,0x1380 , +/* GRAS CTX 0 */ +0x2000 ,0x2004 ,0x2008 ,0x2067 ,0x2070 ,0x2078 ,0x207B ,0x216E , +/* PC CTX 0 */ +0x21C0 ,0x21C6 ,0x21D0 ,0x21D0 ,0x21D9 ,0x21D9 ,0x21E5 ,0x21E7 , +/* VFD CTX 0 */ +0x2200 ,0x2204 ,0x2208 ,0x22A9 , +/* GRAS CTX 1 */ +0x2400 ,0x2404 ,0x2408 ,0x2467 ,0x2470 ,0x2478 ,0x247B ,0x256E , +/* PC CTX 1 */ +0x25C0 ,0x25C6 ,0x25D0 ,0x25D0 ,0x25D9 ,0x25D9 ,0x25E5 ,0x25E7 , +/* VFD CTX 1 */ +0x2600 ,0x2604 ,0x2608 ,0x26A9 , +/* XPU */ +0x2C00 ,0x2C01 ,0x2C10 ,0x2C10 ,0x2C12 ,0x2C16 ,0x2C1D ,0x2C20 , +0x2C28 ,0x2C28 ,0x2C30 ,0x2C30 ,0x2C32 ,0x2C36 ,0x2C40 ,0x2C40 , +0x2C50 ,0x2C50 ,0x2C52 ,0x2C56 ,0x2C80 ,0x2C80 ,0x2C94 ,0x2C95 , +/* VBIF */ +0x3000 ,0x3007 ,0x300C ,0x3014 ,0x3018 ,0x301D ,0x3020 ,0x3022 , +0x3024 ,0x3026 ,0x3028 ,0x302A ,0x302C ,0x302D ,0x3030 ,0x3031 , +0x3034 ,0x3036 ,0x3038 ,0x3038 ,0x303C ,0x303D ,0x3040 ,0x3040 , +0x3049 ,0x3049 ,0x3058 ,0x3058 ,0x305B ,0x3061 ,0x3064 ,0x3068 , +0x306C ,0x306D ,0x3080 ,0x3088 ,0x308B ,0x308C ,0x3090 ,0x3094 , +0x3098 ,0x3098 ,0x309C ,0x309C ,0x30C0 ,0x30C0 ,0x30C8 ,0x30C8 , +0x30D0 ,0x30D0 ,0x30D8 ,0x30D8 ,0x30E0 ,0x30E0 ,0x3100 ,0x3100 , +0x3108 ,0x3108 ,0x3110 ,0x3110 ,0x3118 ,0x3118 ,0x3120 ,0x3120 , +0x3124 ,0x3125 ,0x3129 ,0x3129 ,0x3131 ,0x3131 ,0x330C ,0x330C , +0x3310 ,0x3310 ,0x3400 ,0x3401 ,0x3410 ,0x3410 ,0x3412 ,0x3416 , +0x341D ,0x3420 ,0x3428 ,0x3428 ,0x3430 ,0x3430 ,0x3432 ,0x3436 , +0x3440 ,0x3440 ,0x3450 ,0x3450 ,0x3452 ,0x3456 ,0x3480 ,0x3480 , +0x3494 ,0x3495 ,0x4000 ,0x4000 ,0x4002 ,0x4002 ,0x4004 ,0x4004 , +0x4008 ,0x400A ,0x400C ,0x400D ,0x400F ,0x4012 ,0x4014 ,0x4016 , +0x401D ,0x401D ,0x4020 ,0x4027 ,0x4060 ,0x4062 ,0x4200 ,0x4200 , +0x4300 ,0x4300 ,0x4400 ,0x4400 ,0x4500 ,0x4500 ,0x4800 ,0x4802 , +0x480F ,0x480F ,0x4811 ,0x4811 ,0x4813 ,0x4813 ,0x4815 ,0x4816 , +0x482B ,0x482B ,0x4857 ,0x4857 ,0x4883 ,0x4883 ,0x48AF ,0x48AF , +0x48C5 ,0x48C5 ,0x48E5 ,0x48E5 ,0x4905 ,0x4905 ,0x4925 ,0x4925 , +0x4945 ,0x4945 ,0x4950 ,0x4950 ,0x495B ,0x495B ,0x4980 ,0x498E , +0x4B00 ,0x4B00 ,0x4C00 ,0x4C00 ,0x4D00 ,0x4D00 ,0x4E00 ,0x4E00 , +0x4E80 ,0x4E80 ,0x4F00 ,0x4F00 ,0x4F08 ,0x4F08 ,0x4F10 ,0x4F10 , +0x4F18 ,0x4F18 ,0x4F20 ,0x4F20 ,0x4F30 ,0x4F30 ,0x4F60 ,0x4F60 , +0x4F80 ,0x4F81 ,0x4F88 ,0x4F89 ,0x4FEE ,0x4FEE ,0x4FF3 ,0x4FF3 , +0x6000 ,0x6001 ,0x6008 ,0x600F ,0x6014 ,0x6016 ,0x6018 ,0x601B , +0x61FD ,0x61FD ,0x623C ,0x623C ,0x6380 ,0x6380 ,0x63A0 ,0x63A0 ,
drivers/gpu/drm/msm/adreno/a4xx_gpu.c line 404
Quoted 10 lines
drivers/gpu/drm/msm/adreno/a4xx_gpu.c new file +10
-0+0x63C0 ,0x63C1 ,0x63C8 ,0x63C9 ,0x63D0 ,0x63D4 ,0x63D6 ,0x63D6 , +0x63EE ,0x63EE ,0x6400 ,0x6401 ,0x6408 ,0x640F ,0x6414 ,0x6416 , +0x6418 ,0x641B ,0x65FD ,0x65FD ,0x663C ,0x663C ,0x6780 ,0x6780 , +0x67A0 ,0x67A0 ,0x67C0 ,0x67C1 ,0x67C8 ,0x67C9 ,0x67D0 ,0x67D4 , +0x67D6 ,0x67D6 ,0x67EE ,0x67EE ,0x6800 ,0x6801 ,0x6808 ,0x680F , +0x6814 ,0x6816 ,0x6818 ,0x681B ,0x69FD ,0x69FD ,0x6A3C ,0x6A3C , +0x6B80 ,0x6B80 ,0x6BA0 ,0x6BA0 ,0x6BC0 ,0x6BC1 ,0x6BC8 ,0x6BC9 , + 0x6BD0, 0x6BD4, 0x6BD6, 0x6BD6, 0x6BEE, 0x6BEE, +}; +
you'll need a ~0 sentinel at the end of that.. which was something I added recently.
BR,
-R
_______________________________________________
dri-devel mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel