clk: fractional-divider: fix up the fractional clk's jitter

Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation.

For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions, approx = rockchip_fractional_special_approx;
but approx = NULL in the default case.

RK document description:
3.1.9 Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART.

Signed-off-by Elaine Zhang <[email protected]>

---
 drivers/clk/clk-fractional-divider.c |  4 ++++
 drivers/clk/rockchip/clk.c           | 20 ++++++++++++++++++++
 include/linux/clk-provider.h         |  3 +++
 3 files changed, 27 insertions(+)

From: Elaine Zhang <[email protected]>

Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation.

For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions.

Signed-off-by Elaine Zhang <[email protected]>

---
  drivers/clk/clk-fractional-divider.c | 28 ++++++++++++++++++++--------
  include/linux/clk-provider.h         |  3 +++
  2 files changed, 23 insertions(+), 8 deletions(-)

drivers/clk/clk-fractional-divider.c +20 -8

index aab904618eb6..fdf625fb10fa 100644
@@ -49,16 +49,12 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
  	return ret;
  }
 
-static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
-			      unsigned long *parent_rate)
+static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
+					 unsigned long *parent_rate,
+					 unsigned long *m, unsigned long *n)
  {
  	struct clk_fractional_divider *fd = to_clk_fd(hw);
  	unsigned long scale;
-	unsigned long m, n;
-	u64 ret;
-
-	if (!rate || rate >= *parent_rate)
-		return *parent_rate;
 
  	/*
  	 * Get rate closer to *parent_rate to guarantee there is no overflow

@@ -71,7 +67,23 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
 
  	rational_best_approximation(rate, *parent_rate,
  			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
-			&m, &n);
+			m, n);
+}
+
+static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long *parent_rate)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long m, n;
+	u64 ret;
+
+	if (!rate || rate >= *parent_rate)
+		return *parent_rate;
+
+	if (fd->approximation)
+		fd->approximation(hw, rate, parent_rate, &m, &n);
+	else
+		clk_fd_general_approximation(hw, rate, parent_rate, &m, &n);
 
  	ret = (u64)*parent_rate * m;
  	do_div(ret, n);

include/linux/clk-provider.h +0 -0

index c59c62571e4f..1fc113fbf955 100644

From: Elaine Zhang <[email protected]>

Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation.

For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions.

Signed-off-by Elaine Zhang <[email protected]>

---

From: Elaine Zhang <[email protected]>

Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation.

For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies.

Therefore add the ability to provide custom approximation functions.

Signed-off-by Elaine Zhang <[email protected]>

From Rockchips fractional divider description:

From: Elaine Zhang <[email protected]>

Quoted 1 line

From Rockchips fractional divider description:

3.1.9 Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART.

Therefore add a special approximation function that handles this special requirement.

Signed-off-by Elaine Zhang <[email protected]>

---
  drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++++++
  1 file changed, 36 insertions(+)

drivers/clk/rockchip/clk.c +35 -0

index fe1d393cf678..b6db79a00602 100644
@@ -29,6 +29,7 @@
  #include <linux/mfd/syscon.h>
  #include <linux/regmap.h>
  #include <linux/reboot.h>
+#include <linux/rational.h>
  #include "clk.h"
 
  /**

@@ -164,6 +165,40 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
  	return notifier_from_errno(ret);
  }
 
+/**
+ * fractional divider must set that denominator is 20 times larger than
+ * numerator to generate precise clock frequency.
+ */
+void rockchip_fractional_approximation(struct clk_hw *hw,
+		unsigned long rate, unsigned long *parent_rate,
+		unsigned long *m, unsigned long *n)
+{
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+	unsigned long p_rate, p_parent_rate;
+	struct clk_hw *p_parent;
+	unsigned long scale;
+
+	p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
+	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
+		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
+		p_parent_rate = clk_hw_get_rate(p_parent);
+		*parent_rate = p_parent_rate;
+	}
+
+	/*
+	 * Get rate closer to *parent_rate to guarantee there is no overflow
+	 * for m and n. In the result it will be the nearest rate left shifted
+	 * by (scale - fd->nwidth) bits.
+	 */
+	scale = fls_long(*parent_rate / rate - 1);
+	if (scale > fd->nwidth)
+		rate <<= scale - fd->nwidth;
+
+	rational_best_approximation(rate, *parent_rate,
+			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
+			m, n);
+}
+
  static struct clk *rockchip_clk_register_frac_branch(
  		struct rockchip_clk_provider *ctx, const char *name,
  		const char *const *parent_names, u8 num_parents,

From: Elaine Zhang <[email protected]>

From Rockchips fractional divider description:
3.1.9 Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART.

Therefore add a special approximation function that handles this special requirement.

Signed-off-by Elaine Zhang <[email protected]>