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imx: mx6slevk: Add I2C1 support

PATCH Superseded Ye.Li 4 participants 17 messages Sep 10, 2014 – Dec 22, 2014 Arm (32-bit)

v1 of 3 Superseded Latest is v3 →

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Ye.Li

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#0 lore raw

PATCH 1/4 imx: mx6slevk: Add I2C1 support

Add I2C1 pin and pad settings, and enable the MXC I2C driver.

Signed-off-by Ye.Li <[email protected]>
---
 arch/arm/include/asm/arch-mx6/mx6sl_pins.h |    5 +++++
 board/freescale/mx6slevk/mx6slevk.c        |   26 ++++++++++++++++++++++++++
 include/configs/mx6slevk.h                 |    6 ++++++
 3 files changed, 37 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx6/mx6sl_pins.h +5 -0
index 045ccc4..ac84270 100644
@@ -34,5 +34,10 @@ enum {
 	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
 	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
 	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
+
+	MX6_PAD_I2C1_SDA__I2C1_SDA					= IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+	MX6_PAD_I2C1_SDA__GPIO_3_13					= IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SCL__I2C1_SCL					= IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+	MX6_PAD_I2C1_SCL__GPIO_3_12					= IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
 };
 #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
board/freescale/mx6slevk/mx6slevk.c +26 -0
index a990b4c..fedd5c3 100644
@@ -13,12 +13,14 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
 #include <netdev.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
 
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info0 = {
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+};
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

@@ -162,6 +185,9 @@ int board_init(void)
 #ifdef	CONFIG_FEC_MXC
 	setup_fec();
 #endif
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+
 	return 0;
 }
include/configs/mx6slevk.h +6 -0
index 3d05a64..bf5066f 100644
@@ -60,6 +60,12 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
Signature · 1 line
1.7.4.1
author
#1 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>
---
 board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
 include/configs/mx6slevk.h          |    7 ++++
 2 files changed, 64 insertions(+), 0 deletions(-)
board/freescale/mx6slevk/mx6slevk.c +57 -0
index fedd5c3..8b6a79c 100644
@@ -21,6 +21,8 @@
 #include <mmc.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC	0
+
 /* I2C1 for PMIC */
 struct i2c_pads_info i2c_pad_info0 = {
 	.sda = {

@@ -191,6 +195,59 @@ int board_init(void)
 	return 0;
 }
 
+static int pfuze_init(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	pfuze_init();
+
+	return 0;
+}
+
 u32 get_board_rev(void)
 {
 	return get_cpu_rev();
include/configs/mx6slevk.h +7 -0
index bf5066f..09d0896 100644
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART

@@ -66,6 +67,12 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		  100000
 
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
Signature · 1 line
1.7.4.1
#2 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hi Ye,

Quoted 5 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>

---

Slowly (sorry for that..) I am checking again all PMIC related patches you sent last month. However, these patches do not fit very well in the current development.

In the last U-Boot mini summit we get the decision to post new PMIC drivers according to the Device Model rules. Przemyslaw is the new custodian for PMICs, and he will take care of all related issues regarding power management.

Please rethink your patches and post them again, not forgetting to add Przemyslaw in CC.

Best regards,
Stefano Babic

Quoted 112 lines
 board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
 include/configs/mx6slevk.h          |    7 ++++
 2 files changed, 64 insertions(+), 0 deletions(-)
board/freescale/mx6slevk/mx6slevk.c +57 -0
index fedd5c3..8b6a79c 100644
@@ -21,6 +21,8 @@
 #include <mmc.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC	0
+
 /* I2C1 for PMIC */
 struct i2c_pads_info i2c_pad_info0 = {
 	.sda = {

@@ -191,6 +195,59 @@ int board_init(void)
 	return 0;
 }
 
+static int pfuze_init(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	pfuze_init();
+
+	return 0;
+}
+
 u32 get_board_rev(void)
 {
 	return get_cpu_rev();
include/configs/mx6slevk.h +7 -0
index bf5066f..09d0896 100644
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART

@@ -66,6 +67,12 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		  100000
 
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
author
#3 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hi Przemyslaw,

Quoted 8 lines · Stefano Babic

Hi Ye,

Quoted 5 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>

---

Quoted 8 lines

Slowly (sorry for that..) I am checking again all PMIC related patches you sent last month. However, these patches do not fit very well in the current development.

In the last U-Boot mini summit we get the decision to post new PMIC drivers according to the Device Model rules. Przemyslaw is the new custodian for PMICs, and he will take care of all related issues regarding power management.

Can you share me more information about the new PMIC drivers development that Stefano mentioned above.
1. Have you completed the APIs define for new PMIC drivers? If yes, where I can get them.
2. When will the new PMIC drivers deliver?
3. Will the PMIC devices already supported in current release stay supported by new PMIC drivers?

Best regards,
Ye Li

Quoted 119 lines

Please rethink your patches and post them again, not forgetting to add Przemyslaw in CC.

Best regards,
Stefano Babic

Quoted 112 lines
 board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
 include/configs/mx6slevk.h          |    7 ++++
 2 files changed, 64 insertions(+), 0 deletions(-)
board/freescale/mx6slevk/mx6slevk.c +57 -0
index fedd5c3..8b6a79c 100644
@@ -21,6 +21,8 @@
 #include <mmc.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC	0
+
 /* I2C1 for PMIC */
 struct i2c_pads_info i2c_pad_info0 = {
 	.sda = {

@@ -191,6 +195,59 @@ int board_init(void)
 	return 0;
 }
 
+static int pfuze_init(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	pfuze_init();
+
+	return 0;
+}
+
 u32 get_board_rev(void)
 {
 	return get_cpu_rev();
include/configs/mx6slevk.h +7 -0
index bf5066f..09d0896 100644
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART

@@ -66,6 +67,12 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		  100000
 
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
author
#4 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hi Przemyslaw,

Quoted 135 lines · On 11/4/2014 5:24 PM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 8 lines · Stefano Babic

Hi Ye,

Quoted 5 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>

---

Quoted 8 lines

Slowly (sorry for that..) I am checking again all PMIC related patches you sent last month. However, these patches do not fit very well in the current development.

In the last U-Boot mini summit we get the decision to post new PMIC drivers according to the Device Model rules. Przemyslaw is the new custodian for PMICs, and he will take care of all related issues regarding power management.

Can you share me more information about the new PMIC drivers development that Stefano mentioned above.
1. Have you completed the APIs define for new PMIC drivers? If yes, where I can get them.
2. When will the new PMIC drivers deliver?
3. Will the PMIC devices already supported in current release stay supported by new PMIC drivers?

Best regards,
Ye Li

Quoted 108 lines

Please rethink your patches and post them again, not forgetting to add Przemyslaw in CC.

Best regards,
Stefano Babic

Quoted 102 lines
 board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
 include/configs/mx6slevk.h          |    7 ++++
 2 files changed, 64 insertions(+), 0 deletions(-)
board/freescale/mx6slevk/mx6slevk.c +57 -0
index fedd5c3..8b6a79c 100644
@@ -21,6 +21,8 @@
 #include <mmc.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC	0
+
 /* I2C1 for PMIC */
 struct i2c_pads_info i2c_pad_info0 = {
 	.sda = {

@@ -191,6 +195,59 @@ int board_init(void)
 	return 0;
 }
 
+static int pfuze_init(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	pfuze_init();
+
+	return 0;
+}
+
 u32 get_board_rev(void)
 {
 	return get_cpu_rev();
include/configs/mx6slevk.h +1 -0
index bf5066f..09d0896 100644
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART

@@ -66,6 +67,12 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		  100000
Quoted 10 lines
Quoted 10 lines

include/configs/mx6slevk.h line 78

Quoted 10 lines
include/configs/mx6slevk.h +6 -0
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1

Please help to answer my questions in the emails thread. A incorrect email address was given, so I resend the email now.

Best regards,
Ye Li

#5 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hello Ye Li,

Quoted 29 lines · On 11/04/2014 10:37 AM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 25 lines · On 11/4/2014 5:24 PM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 8 lines · Stefano Babic

Hi Ye,

Quoted 5 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>

---

Quoted 8 lines

Slowly (sorry for that..) I am checking again all PMIC related patches you sent last month. However, these patches do not fit very well in the current development.

In the last U-Boot mini summit we get the decision to post new PMIC drivers according to the Device Model rules. Przemyslaw is the new custodian for PMICs, and he will take care of all related issues regarding power management.

Can you share me more information about the new PMIC drivers development that Stefano mentioned above.
1. Have you completed the APIs define for new PMIC drivers? If yes, where I can get them.
2. When will the new PMIC drivers deliver?
3. Will the PMIC devices already supported in current release stay supported by new PMIC drivers?

The work on new PMIC framework was temporary on hold.
Now I'm working on it, but the basic functionality is actually done. The first version you can check here:
https://github.com/bobenstein/u-boot.git
I need to make some rework, since the i2c is going to support the driver model.

I can now focus on this work. And this will be merged through u-boot-dm
- since i2c support is added.

The plan is simple:
1) Add new drivers to the present PMIC framework - before merge the new one.
2) Add new PMIC framework as a separated piece of code.
3) Migrate old drivers and boards to the new framework.
4) Remove the old framework without any conflicts.

So it's not a problem if you want add this driver, we add this to the current framework - the migration should be simple and will not cause conflicts.

If you are interested in the new PMIC framework design, please read the doc file added by the patches from the link above.

You can implement just one class(UCLASS_PMIC), and if you need user friendly interface it is welcome to implement also UCLASS_PMIC_REGULATOR.

Please follow the list, maybe I will send the patches at the end of this week.

... [ snip ] ...

Best regards,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
author
#6 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hi Przemyslaw,

Quoted 51 lines · Przemyslaw Marczak

Hello Ye Li,

Quoted 29 lines · On 11/04/2014 10:37 AM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 25 lines · On 11/4/2014 5:24 PM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 8 lines · Stefano Babic

Hi Ye,

Quoted 5 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>

---

Quoted 8 lines

Slowly (sorry for that..) I am checking again all PMIC related patches you sent last month. However, these patches do not fit very well in the current development.

In the last U-Boot mini summit we get the decision to post new PMIC drivers according to the Device Model rules. Przemyslaw is the new custodian for PMICs, and he will take care of all related issues regarding power management.

Can you share me more information about the new PMIC drivers development that Stefano mentioned above.
1. Have you completed the APIs define for new PMIC drivers? If yes, where I can get them.
2. When will the new PMIC drivers deliver?
3. Will the PMIC devices already supported in current release stay supported by new PMIC drivers?

The work on new PMIC framework was temporary on hold.
Now I'm working on it, but the basic functionality is actually done. The first version you can check here:
https://github.com/bobenstein/u-boot.git
I need to make some rework, since the i2c is going to support the driver model.

I can now focus on this work. And this will be merged through u-boot-dm - since i2c support is added.

The plan is simple:
1) Add new drivers to the present PMIC framework - before merge the new one.
2) Add new PMIC framework as a separated piece of code.
3) Migrate old drivers and boards to the new framework.
4) Remove the old framework without any conflicts.

So it's not a problem if you want add this driver, we add this to the current framework - the migration should be simple and will not cause conflicts.

If you are interested in the new PMIC framework design, please read the doc file added by the patches from the link above.

Quoted 8 lines

You can implement just one class(UCLASS_PMIC), and if you need user friendly interface it is welcome to implement also UCLASS_PMIC_REGULATOR.

Please follow the list, maybe I will send the patches at the end of this week.

... [ snip ] ...

Best regards,

My patches don't add any new PMIC driver. The PFUZE100 driver already exists in present u-boot. We just call the driver to apply new settings for PFUZE100.
According to your plan, can you help to figure out which phase the PMIC development is at now? I feel my patches won't conflict with your job before phase 3.
If there is no conflict, I will continue the upstream.

Best regards,
Ye Li

.

#7 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hello Ye Li,

Quoted 63 lines · On 11/05/2014 09:28 AM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 51 lines · Przemyslaw Marczak

Hello Ye Li,

Quoted 29 lines · On 11/04/2014 10:37 AM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 25 lines · On 11/4/2014 5:24 PM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 8 lines · Stefano Babic

Hi Ye,

Quoted 5 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>

---

Quoted 8 lines

Slowly (sorry for that..) I am checking again all PMIC related patches you sent last month. However, these patches do not fit very well in the current development.

In the last U-Boot mini summit we get the decision to post new PMIC drivers according to the Device Model rules. Przemyslaw is the new custodian for PMICs, and he will take care of all related issues regarding power management.

Can you share me more information about the new PMIC drivers development that Stefano mentioned above.
1. Have you completed the APIs define for new PMIC drivers? If yes, where I can get them.
2. When will the new PMIC drivers deliver?
3. Will the PMIC devices already supported in current release stay supported by new PMIC drivers?

The work on new PMIC framework was temporary on hold.
Now I'm working on it, but the basic functionality is actually done. The first version you can check here:
https://github.com/bobenstein/u-boot.git
I need to make some rework, since the i2c is going to support the driver model.

I can now focus on this work. And this will be merged through u-boot-dm - since i2c support is added.

The plan is simple:
1) Add new drivers to the present PMIC framework - before merge the new one.
2) Add new PMIC framework as a separated piece of code.
3) Migrate old drivers and boards to the new framework.
4) Remove the old framework without any conflicts.

So it's not a problem if you want add this driver, we add this to the current framework - the migration should be simple and will not cause conflicts.

If you are interested in the new PMIC framework design, please read the doc file added by the patches from the link above.

Quoted 8 lines

You can implement just one class(UCLASS_PMIC), and if you need user friendly interface it is welcome to implement also UCLASS_PMIC_REGULATOR.

Please follow the list, maybe I will send the patches at the end of this week.

... [ snip ] ...

Best regards,

Quoted 9 lines

My patches don't add any new PMIC driver. The PFUZE100 driver already exists in present u-boot. We just call the driver to apply new settings for PFUZE100.
According to your plan, can you help to figure out which phase the PMIC development is at now? I feel my patches won't conflict with your job before phase 3.
If there is no conflict, I will continue the upstream.

Best regards,
Ye Li

.

Ok, so the code from github link(also can be found on the list), adds API for two PMIC uclasses: PMIC and REGULATOR - both are implemented by MAX77686 driver and enabled for Trats2 and Odroid boards.
It was RFC patchset, but is fully functional. It's hard to say when exactly I can send next version - it's not the only task. There are no conflicts, so please continue your work.

Best Regards,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
#8 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

In reply to Ye.Li

Hello Ye Li,

Quoted 77 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>
---
  board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
  include/configs/mx6slevk.h          |    7 ++++
  2 files changed, 64 insertions(+), 0 deletions(-)
board/freescale/mx6slevk/mx6slevk.c +46 -0
index fedd5c3..8b6a79c 100644
@@ -21,6 +21,8 @@
  #include <mmc.h>
  #include <netdev.h>
  #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
  DECLARE_GLOBAL_DATA_PTR;
 

@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
  #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC	0
+
  /* I2C1 for PMIC */
  struct i2c_pads_info i2c_pad_info0 = {
  	.sda = {

@@ -191,6 +195,59 @@ int board_init(void)
  	return 0;
  }
 
+static int pfuze_init(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);

board/freescale/mx6slevk/mx6slevk.c int board_init(void) · line 249

Quoted 10 lines
board/freescale/mx6slevk/mx6slevk.c +10 -0
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	pfuze_init();
+
+	return 0;
+}

Why not use power_init_board()?
It's dedicated and called at common/board_r.c.

Quoted 17 lines
board/freescale/mx6slevk/mx6slevk.c +1 -0
+
  u32 get_board_rev(void)
  {
  	return get_cpu_rev();
include/configs/mx6slevk.h +1 -0
index bf5066f..09d0896 100644
@@ -30,6 +30,7 @@
  #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
  #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
  #define CONFIG_MXC_GPIO
 
  #define CONFIG_MXC_UART

include/configs/mx6slevk.h line 74

Quoted 8 lines
include/configs/mx6slevk.h +5 -0
@@ -66,6 +67,12 @@
  #define CONFIG_SYS_I2C_MXC
  #define CONFIG_SYS_I2C_SPEED		  100000
 
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08

I assume that the I2C addr is const, if yes then it should be moved to the PFUZE100 header.

include/configs/mx6slevk.h line 78

Quoted 5 lines
include/configs/mx6slevk.h +1 -0
+
  /* allow to overwrite serial and ethaddr */
  #define CONFIG_ENV_OVERWRITE
  #define CONFIG_CONS_INDEX		1

Thank you,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
author
#9 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hi Przemyslaw,

Quoted 85 lines · Przemyslaw Marczak

Hello Ye Li,

Quoted 82 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>
---
  board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
  include/configs/mx6slevk.h          |    7 ++++
  2 files changed, 64 insertions(+), 0 deletions(-)
board/freescale/mx6slevk/mx6slevk.c +51 -0
index fedd5c3..8b6a79c 100644
@@ -21,6 +21,8 @@
  #include <mmc.h>
  #include <netdev.h>
  #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
  DECLARE_GLOBAL_DATA_PTR;
 

@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
  #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC    0
+
  /* I2C1 for PMIC */
  struct i2c_pads_info i2c_pad_info0 = {
      .sda = {

@@ -191,6 +195,59 @@ int board_init(void)
      return 0;
  }
 
+static int pfuze_init(void)
+{
+    struct pmic *p;
+    int ret;
+    unsigned int reg;
+
+    ret = power_pfuze100_init(I2C_PMIC);
+    if (ret)
+        return ret;
+
+    p = pmic_get("PFUZE100");
+    ret = pmic_probe(p);
+    if (ret)
+        return ret;
+
+    pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+    printf("PMIC:  PFUZE%s ID=0x%02x\n",
+        ((reg & 0xf) == 0) ? "100" : "200", reg);
+
+    /* Set SW1AB stanby volage to 0.975V */
+    pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+    reg &= ~0x3f;
+    reg |= 0x1b;
+    pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+    /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+    pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+    reg &= ~0xc0;
+    reg |= 0x40;
+    pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+    /* Set SW1C standby voltage to 0.975V */
+    pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+    reg &= ~0x3f;
+    reg |= 0x1b;
+    pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+    /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+    pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+    reg &= ~0xc0;
+    reg |= 0x40;
+    pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+    return 0;
+}
+
+int board_late_init(void)
Quoted 9 lines

board/freescale/mx6slevk/mx6slevk.c int board_init(void) · line 249

Quoted 5 lines
board/freescale/mx6slevk/mx6slevk.c +5 -0
+{
+    pfuze_init();
+
+    return 0;
+}

Why not use power_init_board()?
It's dedicated and called at common/board_r.c.

Good suggestion, will change to use the power_init_board in v2.

Quoted 20 lines
Quoted 20 lines
board/freescale/mx6slevk/mx6slevk.c +1 -0
+
  u32 get_board_rev(void)
  {
      return get_cpu_rev();
include/configs/mx6slevk.h +1 -0
index bf5066f..09d0896 100644
@@ -30,6 +30,7 @@
  #define CONFIG_SYS_MALLOC_LEN        (3 * SZ_1M)
 
  #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
  #define CONFIG_MXC_GPIO
 
  #define CONFIG_MXC_UART

@@ -66,6 +67,12 @@
  #define CONFIG_SYS_I2C_MXC
  #define CONFIG_SYS_I2C_SPEED          100000
Quoted 8 lines

include/configs/mx6slevk.h line 74

Quoted 5 lines
include/configs/mx6slevk.h +5 -0
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR    0x08

I assume that the I2C addr is const, if yes then it should be moved to the PFUZE100 header.

It is not const. The default I2C address is 0x08. But it can be programmed from 0x08 to 0x0F by setting OTP_I2C_ADDR register.

Quoted 7 lines

include/configs/mx6slevk.h line 78

Quoted 5 lines
include/configs/mx6slevk.h +1 -0
+
  /* allow to overwrite serial and ethaddr */
  #define CONFIG_ENV_OVERWRITE
  #define CONFIG_CONS_INDEX        1

Thank you,

Best regards,
Ye Li

#10 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

Hello,

Quoted 97 lines · On 11/05/2014 09:33 AM, Li Ye-B37916 wrote:

Hi Przemyslaw,

Quoted 85 lines · Przemyslaw Marczak

Hello Ye Li,

Quoted 82 lines · Ye.Li

Initialize the Pfuze on I2C1 at board late init. The mx6slevk board has Pfuze100 or Pfuze200, print the chip type by parsing the ID.

Signed-off-by Ye.Li <[email protected]>
---
   board/freescale/mx6slevk/mx6slevk.c |   57 +++++++++++++++++++++++++++++++++++
   include/configs/mx6slevk.h          |    7 ++++
   2 files changed, 64 insertions(+), 0 deletions(-)
board/freescale/mx6slevk/mx6slevk.c +51 -0
index fedd5c3..8b6a79c 100644
@@ -21,6 +21,8 @@
   #include <mmc.h>
   #include <netdev.h>
   #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
   DECLARE_GLOBAL_DATA_PTR;
 

@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
   #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define I2C_PMIC    0
+
   /* I2C1 for PMIC */
   struct i2c_pads_info i2c_pad_info0 = {
       .sda = {

@@ -191,6 +195,59 @@ int board_init(void)
       return 0;
   }
 
+static int pfuze_init(void)
+{
+    struct pmic *p;
+    int ret;
+    unsigned int reg;
+
+    ret = power_pfuze100_init(I2C_PMIC);
+    if (ret)
+        return ret;
+
+    p = pmic_get("PFUZE100");
+    ret = pmic_probe(p);
+    if (ret)
+        return ret;
+
+    pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+    printf("PMIC:  PFUZE%s ID=0x%02x\n",
+        ((reg & 0xf) == 0) ? "100" : "200", reg);
+
+    /* Set SW1AB stanby volage to 0.975V */
+    pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+    reg &= ~0x3f;
+    reg |= 0x1b;
+    pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+    /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+    pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+    reg &= ~0xc0;
+    reg |= 0x40;
+    pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+    /* Set SW1C standby voltage to 0.975V */
+    pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+    reg &= ~0x3f;
+    reg |= 0x1b;
+    pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+    /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+    pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+    reg &= ~0xc0;
+    reg |= 0x40;
+    pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+    return 0;
+}
+
+int board_late_init(void)
Quoted 9 lines

board/freescale/mx6slevk/mx6slevk.c int board_init(void) · line 249

Quoted 5 lines
board/freescale/mx6slevk/mx6slevk.c +5 -0
+{
+    pfuze_init();
+
+    return 0;
+}

Why not use power_init_board()?
It's dedicated and called at common/board_r.c.

Quoted 2 lines

Good suggestion, will change to use the power_init_board in v2.

The power_init_board is called much more earlier, then please make sure that everything will work for you.

Quoted 28 lines
Quoted 20 lines
Quoted 20 lines
board/freescale/mx6slevk/mx6slevk.c +1 -0
+
   u32 get_board_rev(void)
   {
       return get_cpu_rev();
include/configs/mx6slevk.h +1 -0
index bf5066f..09d0896 100644
@@ -30,6 +30,7 @@
   #define CONFIG_SYS_MALLOC_LEN        (3 * SZ_1M)
 
   #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
   #define CONFIG_MXC_GPIO
 
   #define CONFIG_MXC_UART

@@ -66,6 +67,12 @@
   #define CONFIG_SYS_I2C_MXC
   #define CONFIG_SYS_I2C_SPEED          100000
Quoted 8 lines

include/configs/mx6slevk.h line 74

Quoted 5 lines
include/configs/mx6slevk.h +5 -0
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR    0x08

I assume that the I2C addr is const, if yes then it should be moved to the PFUZE100 header.

Quoted 3 lines

It is not const. The default I2C address is 0x08. But it can be programmed from 0x08 to 0x0F by setting OTP_I2C_ADDR register.

Yes, so the PMIC header is a good place for the default definitions. But I see that each board defines the same address for it. So leave it as it is.

Quoted 11 lines
Quoted 7 lines

include/configs/mx6slevk.h line 78

Quoted 5 lines
include/configs/mx6slevk.h +1 -0
+
   /* allow to overwrite serial and ethaddr */
   #define CONFIG_ENV_OVERWRITE
   #define CONFIG_CONS_INDEX        1

Thank you,

Best regards,
Ye Li

Best regards,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
#11 lore raw

PATCH 2/4 imx: mx6slevk: Add PMIC Pfuze support

In reply to Li Ye-B37916

Hi Ye Li,

Quoted 4 lines · On Wed, Nov 5, 2014 at 6:33 AM, Li Ye-B37916 <[email protected]> wrote:
Quoted 3 lines

Why not use power_init_board()?
It's dedicated and called at common/board_r.c.

Good suggestion, will change to use the power_init_board in v2.

Have you had a chance to send a v2 for this series?

I still don't see this patch applied.

Thanks

author
#12 lore raw

PATCH 3/4 imx: mx6sabresd: Add clear print for pfuze200

In reply to Ye.Li

Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd.

Signed-off-by Ye.Li <[email protected]>
---
 board/freescale/mx6sabresd/mx6sabresd.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
board/freescale/mx6sabresd/mx6sabresd.c +2 -1
index 5f65f1b..72d6562 100644
@@ -472,7 +472,8 @@ static int pfuze_init(void)
 		return ret;
 
 	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+	printf("PMIC:  PFUZE%s ID=0x%02x\n",
+		((reg & 0xf) == 0) ? "100" : "200", reg);
 
 	/* Increase VGEN3 from 2.5 to 2.8V */
 	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
Signature · 1 line
1.7.4.1
author
#13 lore raw

PATCH 4/4 imx: mx6: Set Pfuze mode to decrease power number for DSM

In reply to Ye.Li

Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode.

Changes for boards:
-mx6 sabreauto
-mx6 sabresd
-mx6slevk
-mx6sxsabresd

Signed-off-by Ye.Li <[email protected]>
---
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |   36 +++++++++++++++++++++++++
 board/freescale/mx6sabresd/mx6sabresd.c       |   36 +++++++++++++++++++++++++
 board/freescale/mx6slevk/mx6slevk.c           |   36 +++++++++++++++++++++++++
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |   36 +++++++++++++++++++++++++
 4 files changed, 144 insertions(+), 0 deletions(-)
board/freescale/mx6qsabreauto/mx6qsabreauto.c +36 -0
index 76b024b..9e79915 100644
@@ -263,6 +263,37 @@ int board_init(void)
 	return 0;
 }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
 static int pfuze_init(void)
 {
 	struct pmic *p;

@@ -281,6 +312,11 @@ static int pfuze_init(void)
 	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
 	/* Set SW1AB stanby volage to 0.975V */
 	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 	reg &= ~0x3f;
board/freescale/mx6sabresd/mx6sabresd.c +36 -0
index 72d6562..810fe13 100644
@@ -456,6 +456,37 @@ int board_init(void)
 	return 0;
 }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
 static int pfuze_init(void)
 {
 	struct pmic *p;

@@ -475,6 +506,11 @@ static int pfuze_init(void)
 	printf("PMIC:  PFUZE%s ID=0x%02x\n",
 		((reg & 0xf) == 0) ? "100" : "200", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
 	/* Increase VGEN3 from 2.5 to 2.8V */
 	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 	reg &= ~0xf;
board/freescale/mx6slevk/mx6slevk.c +36 -0
index 8b6a79c..fe5e37d 100644
@@ -195,6 +195,37 @@ int board_init(void)
 	return 0;
 }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
 static int pfuze_init(void)
 {
 	struct pmic *p;

@@ -214,6 +245,11 @@ static int pfuze_init(void)
 	printf("PMIC:  PFUZE%s ID=0x%02x\n",
 		((reg & 0xf) == 0) ? "100" : "200", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
 	/* Set SW1AB stanby volage to 0.975V */
 	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 	reg &= ~0x3f;
board/freescale/mx6sxsabresd/mx6sxsabresd.c +36 -0
index 80d2d99..d6a33cd 100644
@@ -170,6 +170,37 @@ struct i2c_pads_info i2c_pad_info1 = {
 	},
 };
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
 static int pfuze_init(void)
 {
 	struct pmic *p;

@@ -188,6 +219,11 @@ static int pfuze_init(void)
 	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
 	/* Set SW1AB standby voltage to 0.975V */
 	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 	reg &= ~0x3f;
Signature · 1 line
1.7.4.1
#14 lore raw

PATCH 4/4 imx: mx6: Set Pfuze mode to decrease power number for DSM

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_init(void) · line 285

Quoted 5 lines · Ye.Li
board/freescale/mx6qsabreauto/mx6qsabreauto.c +5 -0
+       value = 0xc;
+       if (pmic_reg_write(p, 0x23, value)) {
+               printf("Set SW1AB mode error!\n");
+               return -1;
+       }

-1 is not a proper return code here.

You could do this instead:

ret = pmic_reg_write(p, 0x23, value)

if (ret) {
        printf("Set SW1AB mode error: %d\n", ret);
        return ret;
}

Same applies for other parts.

#15 lore raw

PATCH 4/4 imx: mx6: Set Pfuze mode to decrease power number for DSM

In reply to Ye.Li

Hello Ye Li,

Quoted 23 lines · Ye.Li

Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode.

Changes for boards:

(quoted diff) +0 -4
-mx6 sabreauto
-mx6 sabresd
-mx6slevk
-mx6sxsabresd
Signed-off-by Ye.Li <[email protected]>
---
  board/freescale/mx6qsabreauto/mx6qsabreauto.c |   36 +++++++++++++++++++++++++
  board/freescale/mx6sabresd/mx6sabresd.c       |   36 +++++++++++++++++++++++++
  board/freescale/mx6slevk/mx6slevk.c           |   36 +++++++++++++++++++++++++
  board/freescale/mx6sxsabresd/mx6sxsabresd.c   |   36 +++++++++++++++++++++++++
  4 files changed, 144 insertions(+), 0 deletions(-)
board/freescale/mx6qsabreauto/mx6qsabreauto.c +0 -0
index 76b024b..9e79915 100644

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_init(void) · line 266

Quoted 4 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +1 -0
@@ -263,6 +263,37 @@ int board_init(void)
  	return 0;
  }
 
+/* set all switches APS in normal and PFM mode in standby */

I think that the "chip" is quite misleading.
Just use chipid and check the real value instead of using it as bool. And the PF100 DEVICEID should be defined in pf100 header.

Quoted 5 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +5 -0
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_init(void) · line 281

Quoted 10 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +10 -0
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;

If you change "magic" values (e.g. 0xc) with proper defines in pmic header, then it could be reused in the future and the code will be more readable.

Quoted 4 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +4 -0
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_init(void) · line 295

Quoted 10 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +10 -0
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}

The function above is duplicated few times in each board code. Why not make it common and just one?

Quoted 169 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +6 -0
+
  static int pfuze_init(void)
  {
  	struct pmic *p;

@@ -281,6 +312,11 @@ static int pfuze_init(void)
  	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
  	/* Set SW1AB stanby volage to 0.975V */
  	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
  	reg &= ~0x3f;
board/freescale/mx6sabresd/mx6sabresd.c +36 -0
index 72d6562..810fe13 100644
@@ -456,6 +456,37 @@ int board_init(void)
  	return 0;
  }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
  static int pfuze_init(void)
  {
  	struct pmic *p;

@@ -475,6 +506,11 @@ static int pfuze_init(void)
  	printf("PMIC:  PFUZE%s ID=0x%02x\n",
  		((reg & 0xf) == 0) ? "100" : "200", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
  	/* Increase VGEN3 from 2.5 to 2.8V */
  	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
  	reg &= ~0xf;
board/freescale/mx6slevk/mx6slevk.c +36 -0
index 8b6a79c..fe5e37d 100644
@@ -195,6 +195,37 @@ int board_init(void)
  	return 0;
  }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
  static int pfuze_init(void)
  {
  	struct pmic *p;

@@ -214,6 +245,11 @@ static int pfuze_init(void)
  	printf("PMIC:  PFUZE%s ID=0x%02x\n",
  		((reg & 0xf) == 0) ? "100" : "200", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
  	/* Set SW1AB stanby volage to 0.975V */
  	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
  	reg &= ~0x3f;
board/freescale/mx6sxsabresd/mx6sxsabresd.c +31 -0
index 80d2d99..d6a33cd 100644
@@ -170,6 +170,37 @@ struct i2c_pads_info i2c_pad_info1 = {
  	},
  };
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+	unsigned char offset, i, switch_num, value;
+
+	if (!chip) {
+		/* pfuze100 */
+		switch_num = 6;
+		offset = 0x31;
+	} else {
+		/* pfuze200 */
+		switch_num = 4;
+		offset = 0x38;
+	}
+
+	value = 0xc;
+	if (pmic_reg_write(p, 0x23, value)) {
+		printf("Set SW1AB mode error!\n");
+		return -1;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		if (pmic_reg_write(p, offset + i * 7, value)) {
+			printf("Set switch%x mode error!\n", offset);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
  static int pfuze_init(void)
  {
  	struct pmic *p;

@@ -188,6 +219,11 @@ static int pfuze_init(void)
  	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);

board/freescale/mx6sxsabresd/mx6sxsabresd.c static int pfuze_init(void) · line 229

Quoted 10 lines
board/freescale/mx6sxsabresd/mx6sxsabresd.c +5 -0
  	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
+	if (pfuze_setup_mode(p, (reg & 0xf))) {
+		printf("setup pfuze mode error!\n");
+		return -1;
+	}
+
  	/* Set SW1AB standby voltage to 0.975V */
  	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
  	reg &= ~0x3f;

And as Fabio wrote, please return real error values or use errno instead of "-1".

Best regards,

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
author
#16 lore raw

PATCH 4/4 imx: mx6: Set Pfuze mode to decrease power number for DSM

Hi Przemyslaw,

Quoted 29 lines · Przemyslaw Marczak

Hello Ye Li,

Quoted 26 lines · Ye.Li

Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode.

Changes for boards:

(quoted diff) +0 -4
-mx6 sabreauto
-mx6 sabresd
-mx6slevk
-mx6sxsabresd
Signed-off-by Ye.Li <[email protected]>
---
  board/freescale/mx6qsabreauto/mx6qsabreauto.c |   36 +++++++++++++++++++++++++
  board/freescale/mx6sabresd/mx6sabresd.c       |   36 +++++++++++++++++++++++++
  board/freescale/mx6slevk/mx6slevk.c           |   36 +++++++++++++++++++++++++
  board/freescale/mx6sxsabresd/mx6sxsabresd.c   |   36 +++++++++++++++++++++++++
  4 files changed, 144 insertions(+), 0 deletions(-)
board/freescale/mx6qsabreauto/mx6qsabreauto.c +0 -0
index 76b024b..9e79915 100644
@@ -263,6 +263,37 @@ int board_init(void)
      return 0;
  }
Quoted 6 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_init(void) · line 266

Quoted 1 line
board/freescale/mx6qsabreauto/mx6qsabreauto.c +1 -0
+/* set all switches APS in normal and PFM mode in standby */

I think that the "chip" is quite misleading.
Just use chipid and check the real value instead of using it as bool. And the PF100 DEVICEID should be defined in pf100 header.

Accept. Will change it in next version.

Quoted 9 lines
Quoted 9 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +9 -0
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+    unsigned char offset, i, switch_num, value;
+
+    if (!chip) {
+        /* pfuze100 */
+        switch_num = 6;
+        offset = 0x31;
+    } else {
Quoted 9 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_init(void) · line 281

Quoted 6 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +6 -0
+        /* pfuze200 */
+        switch_num = 4;
+        offset = 0x38;
+    }
+
+    value = 0xc;

If you change "magic" values (e.g. 0xc) with proper defines in pmic header, then it could be reused in the future and the code will be more readable.

Ok.

Quoted 9 lines
Quoted 9 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +9 -0
+    if (pmic_reg_write(p, 0x23, value)) {
+        printf("Set SW1AB mode error!\n");
+        return -1;
+    }
+
+    for (i = 0; i < switch_num - 1; i++) {
+        if (pmic_reg_write(p, offset + i * 7, value)) {
+            printf("Set switch%x mode error!\n", offset);
+            return -1;
Quoted 9 lines

board/freescale/mx6qsabreauto/mx6qsabreauto.c int board_init(void) · line 295

Quoted 5 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +5 -0
+        }
+    }
+
+    return 0;
+}

The function above is duplicated few times in each board code. Why not make it common and just one?

I already have made it as a common function in v4. The patch you reviewed seems not the latest one. I will address your other comments and send out v5.

Quoted 170 lines
Quoted 170 lines
board/freescale/mx6qsabreauto/mx6qsabreauto.c +6 -0
+
  static int pfuze_init(void)
  {
      struct pmic *p;

@@ -281,6 +312,11 @@ static int pfuze_init(void)
      pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
      printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
+    if (pfuze_setup_mode(p, (reg & 0xf))) {
+        printf("setup pfuze mode error!\n");
+        return -1;
+    }
+
      /* Set SW1AB stanby volage to 0.975V */
      pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
      reg &= ~0x3f;
board/freescale/mx6sabresd/mx6sabresd.c +36 -0
index 72d6562..810fe13 100644
@@ -456,6 +456,37 @@ int board_init(void)
      return 0;
  }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+    unsigned char offset, i, switch_num, value;
+
+    if (!chip) {
+        /* pfuze100 */
+        switch_num = 6;
+        offset = 0x31;
+    } else {
+        /* pfuze200 */
+        switch_num = 4;
+        offset = 0x38;
+    }
+
+    value = 0xc;
+    if (pmic_reg_write(p, 0x23, value)) {
+        printf("Set SW1AB mode error!\n");
+        return -1;
+    }
+
+    for (i = 0; i < switch_num - 1; i++) {
+        if (pmic_reg_write(p, offset + i * 7, value)) {
+            printf("Set switch%x mode error!\n", offset);
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
  static int pfuze_init(void)
  {
      struct pmic *p;

@@ -475,6 +506,11 @@ static int pfuze_init(void)
      printf("PMIC:  PFUZE%s ID=0x%02x\n",
          ((reg & 0xf) == 0) ? "100" : "200", reg);
 
+    if (pfuze_setup_mode(p, (reg & 0xf))) {
+        printf("setup pfuze mode error!\n");
+        return -1;
+    }
+
      /* Increase VGEN3 from 2.5 to 2.8V */
      pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
      reg &= ~0xf;
board/freescale/mx6slevk/mx6slevk.c +36 -0
index 8b6a79c..fe5e37d 100644
@@ -195,6 +195,37 @@ int board_init(void)
      return 0;
  }
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+    unsigned char offset, i, switch_num, value;
+
+    if (!chip) {
+        /* pfuze100 */
+        switch_num = 6;
+        offset = 0x31;
+    } else {
+        /* pfuze200 */
+        switch_num = 4;
+        offset = 0x38;
+    }
+
+    value = 0xc;
+    if (pmic_reg_write(p, 0x23, value)) {
+        printf("Set SW1AB mode error!\n");
+        return -1;
+    }
+
+    for (i = 0; i < switch_num - 1; i++) {
+        if (pmic_reg_write(p, offset + i * 7, value)) {
+            printf("Set switch%x mode error!\n", offset);
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
  static int pfuze_init(void)
  {
      struct pmic *p;

@@ -214,6 +245,11 @@ static int pfuze_init(void)
      printf("PMIC:  PFUZE%s ID=0x%02x\n",
          ((reg & 0xf) == 0) ? "100" : "200", reg);
 
+    if (pfuze_setup_mode(p, (reg & 0xf))) {
+        printf("setup pfuze mode error!\n");
+        return -1;
+    }
+
      /* Set SW1AB stanby volage to 0.975V */
      pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
      reg &= ~0x3f;
board/freescale/mx6sxsabresd/mx6sxsabresd.c +31 -0
index 80d2d99..d6a33cd 100644
@@ -170,6 +170,37 @@ struct i2c_pads_info i2c_pad_info1 = {
      },
  };
 
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+    unsigned char offset, i, switch_num, value;
+
+    if (!chip) {
+        /* pfuze100 */
+        switch_num = 6;
+        offset = 0x31;
+    } else {
+        /* pfuze200 */
+        switch_num = 4;
+        offset = 0x38;
+    }
+
+    value = 0xc;
+    if (pmic_reg_write(p, 0x23, value)) {
+        printf("Set SW1AB mode error!\n");
+        return -1;
+    }
+
+    for (i = 0; i < switch_num - 1; i++) {
+        if (pmic_reg_write(p, offset + i * 7, value)) {
+            printf("Set switch%x mode error!\n", offset);
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
  static int pfuze_init(void)
  {
      struct pmic *p;

@@ -188,6 +219,11 @@ static int pfuze_init(void)
      pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
      printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
Quoted 12 lines

board/freescale/mx6sxsabresd/mx6sxsabresd.c static int pfuze_init(void) · line 229

Quoted 9 lines
board/freescale/mx6sxsabresd/mx6sxsabresd.c +5 -0
+    if (pfuze_setup_mode(p, (reg & 0xf))) {
+        printf("setup pfuze mode error!\n");
+        return -1;
+    }
+
      /* Set SW1AB standby voltage to 0.975V */
      pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
      reg &= ~0x3f;

And as Fabio wrote, please return real error values or use errno instead of "-1".

Have fixed it in v4 patch.

Quoted 1 line

Best regards,

Best regards,
Ye Li