i2c: designware: prevent early stop on TX FIFO empty
Subsystems (3)
PATCH 1/1 i2c: designware: prevent early stop on TX FIFO empty
If the Designware core is configured with IC_EMPTYFIFO_HOLD_MASTER_EN set to zero, allowing the TX FIFO to become empty causes a STOP condition to be generated on the I2C bus. If the transmit FIFO threshold is set too high, an erroneous STOP condition can be generated on long transfers - particularly where the interrupt latency is extended.
--- drivers/i2c/busses/i2c-designware-core.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/i2c/busses/i2c-designware-core.c +1 -1
@@ -363,7 +363,7 @@ int i2c_dw_init(struct dw_i2c_dev *dev) }/* Configure Tx/Rx FIFO threshold levels */ -dw_writel (dev, dev->tx_fifo_depth -1 ,DW_IC_TX_TL ); +dw_writel (dev, dev->tx_fifo_depth /2 ,DW_IC_TX_TL );dw_writel (dev,0 ,DW_IC_RX_TL );/* configure the i2c master */
Signature · 1 line
1.7.1
Quoted 9 lines · Andrew Jackson
If the Designware core is configured with
IC_EMPTYFIFO_HOLD_MASTER_ENset to zero, allowing the TX FIFO to become empty causes a STOP condition to be generated on the I2C bus. If the transmit FIFO threshold is set too high, an erroneous STOP condition can be generated on long transfers - particularly where the interrupt latency is extended.Signed-off-by Andrew Jackson <[email protected]>Signed-off-by Liviu Dudau <[email protected]>
So, what do other designware users think of this change (nice CC list BTW, Andrew). Adding Mika, too.
Quoted 20 lines
--- drivers/i2c/busses/i2c-designware-core.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)drivers/i2c/busses/i2c-designware-core.c +1
-1@@ -363,7 +363,7 @@ int i2c_dw_init(struct dw_i2c_dev *dev) }/* Configure Tx/Rx FIFO threshold levels */ -dw_writel (dev, dev->tx_fifo_depth -1 ,DW_IC_TX_TL ); +dw_writel (dev, dev->tx_fifo_depth /2 ,DW_IC_TX_TL );dw_writel (dev,0 ,DW_IC_RX_TL );/* configure the i2c master */ Signature · 1 line
1.7.1
Hi Wolfram,
Quoted 8 lines · Wolfram Sang
Quoted 7 lines · Andrew Jackson
If the Designware core is configured with
IC_EMPTYFIFO_HOLD_MASTER_ENset to zero, allowing the TX FIFO to become empty causes a STOP condition to be generated on the I2C bus. If the transmit FIFO threshold is set too high, an erroneous STOP condition can be generated on long transfers - particularly where the interrupt latency is extended.
Quoted 5 lines
Quoted 2 lines
Signed-off-by Andrew Jackson <[email protected]>Signed-off-by Liviu Dudau <[email protected]>So, what do other designware users think of this change (nice CC list BTW, Andrew). Adding Mika, too.
I don't have access to this hardware anymore so I can't test. As far as I remember the spec this change should be OK.
baruch
Quoted 16 lines
Quoted 16 lines
drivers/i2c/busses/i2c-designware-core.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)drivers/i2c/busses/i2c-designware-core.c +1
-1@@ -363,7 +363,7 @@ int i2c_dw_init(struct dw_i2c_dev *dev) }/* Configure Tx/Rx FIFO threshold levels */ -dw_writel (dev, dev->tx_fifo_depth -1 ,DW_IC_TX_TL ); +dw_writel (dev, dev->tx_fifo_depth /2 ,DW_IC_TX_TL );dw_writel (dev,0 ,DW_IC_RX_TL );/* configure the i2c master */
Signature · 3 lines
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -Quoted 7 lines · Wolfram Sang
Quoted 6 lines · Andrew Jackson
If the Designware core is configured with
IC_EMPTYFIFO_HOLD_MASTER_ENset to zero, allowing the TX FIFO to become empty causes a STOP condition to be generated on the I2C bus. If the transmit FIFO threshold is set too high, an erroneous STOP condition can be generated on long transfers - particularly where the interrupt latency is extended.
Makes sense to give some slack so that the interrupt handler is still able to fill the FIFO.
Quoted 6 lines
Quoted 3 lines
Signed-off-by Andrew Jackson <[email protected]>Signed-off-by Liviu Dudau <[email protected]>So, what do other designware users think of this change (nice CC list BTW, Andrew). Adding Mika, too.
I quickly tested this on Haswell machine with touch screen connected to the I2C bus and it still works fine, so
Wolfram Sang
AppliedQuoted 9 lines · Andrew Jackson
If the Designware core is configured with
IC_EMPTYFIFO_HOLD_MASTER_ENset to zero, allowing the TX FIFO to become empty causes a STOP condition to be generated on the I2C bus. If the transmit FIFO threshold is set too high, an erroneous STOP condition can be generated on long transfers - particularly where the interrupt latency is extended.Signed-off-by Andrew Jackson <[email protected]>Signed-off-by Liviu Dudau <[email protected]>
Applied to for-current, thanks!