sun6i: Add dram init and SPL support

---
 arch/arm/cpu/armv7/sunxi/Makefile      |   1 +
 arch/arm/cpu/armv7/sunxi/p2wi.c        | 117 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/gpio.h |   3 +
 arch/arm/include/asm/arch-sunxi/p2wi.h | 140 +++++++++++++++++++++++++++++++++
 4 files changed, 261 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/p2wi.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/p2wi.h

arch/arm/cpu/armv7/sunxi/Makefile +1 -0

index 82dbf76..b3a3601 100644
@@ -13,6 +13,7 @@ obj-y	+= clock.o
 obj-y	+= pinmux.o
 obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN8I)	+= prcm.o
+obj-$(CONFIG_MACH_SUN6I)	+= p2wi.o
 obj-$(CONFIG_MACH_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o

arch/arm/cpu/armv7/sunxi/p2wi.c new file +117 -0

117 lines not on this page · raw message

arch/arm/include/asm/arch-sunxi/gpio.h +3 -0

index 437dd35..c734cf0 100644
@@ -172,6 +172,9 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPI4_SDC3		2
 
+#define SUNXI_GPL0_R_P2WI_SCK	3
+#define SUNXI_GPL1_R_P2WI_SDA	3
+
 #define SUN8I_GPL2_R_UART_TX	2
 #define SUN8I_GPL3_R_UART_RX	2

arch/arm/include/asm/arch-sunxi/p2wi.h new file +140 -0

140 lines not on this page · raw message

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:14 UTC #2 lore raw

PATCH v3 1/11 sun6i: Add new p2wi controller driver

Quoted 9 lines · Hans de Goede

From: Oliver Schinagl <[email protected]>
The A31 uses a new push-pull two wire interface, which features higher transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8 bytes each time, this driver will only see very little use and thus is limited to single byte transmission only.
Signed-off-by Oliver Schinagl <[email protected]>
Signed-off-by Hans de Goede <[email protected]>

One question:

Quoted 4 lines

arch/arm/cpu/armv7/sunxi/p2wi.c new file +4 -0

+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	unsigned long tmo = timer_get_us() + 1000000;

arch/arm/cpu/armv7/sunxi/p2wi.c line 57

Quoted 10 lines

arch/arm/cpu/armv7/sunxi/p2wi.c new file +10 -0

+
+	writel(P2WI_PM_DEV_ADDR(slave_addr) |
+	       P2WI_PM_CTRL_ADDR(ctrl_reg) |
+	       P2WI_PM_INIT_DATA(init_data) |
+	       P2WI_PM_INIT_SEND,
+	       &p2wi->pm);
+
+	while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
+		if (timer_get_us() > tmo)
+			return -EFAULT;

You don't mean ETIME(DOUT) or something here, do you? EFAULT seems a bit odd.

Ian.

Hans de Goede

author

2014-11-08 10:22 UTC #3 lore raw

PATCH v3 1/11 sun6i: Add new p2wi controller driver

Hi,

Quoted 23 lines · Ian Campbell

Quoted 9 lines · Hans de Goede
From: Oliver Schinagl <[email protected]>
The A31 uses a new push-pull two wire interface, which features higher transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8 bytes each time, this driver will only see very little use and thus is limited to single byte transmission only.
Signed-off-by Oliver Schinagl <[email protected]>
Signed-off-by Hans de Goede <[email protected]>
Acked-by Ian Campbell <[email protected]>
One question:
Quoted 9 lines
arch/arm/cpu/armv7/sunxi/p2wi.c new file +9 -0
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	unsigned long tmo = timer_get_us() + 1000000;
+
+	writel(P2WI_PM_DEV_ADDR(slave_addr) |
+	       P2WI_PM_CTRL_ADDR(ctrl_reg) |
+	       P2WI_PM_INIT_DATA(init_data) |
+	       P2WI_PM_INIT_SEND,

Quoted 8 lines

arch/arm/cpu/armv7/sunxi/p2wi.c line 57
Quoted 5 lines
arch/arm/cpu/armv7/sunxi/p2wi.c new file +5 -0
+	       &p2wi->pm);
+
+	while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
+		if (timer_get_us() > tmo)
+			return -EFAULT;
You don't mean ETIME(DOUT) or something here, do you? EFAULT seems a bit odd.

Yes, ETIME would be much better will fix for v4.

Regards,

Hans

Hans de Goede

author

2014-11-07 19:47 UTC #4 lore raw

PATCH v3 2/11 sun6i: Add basic axp221 driver

From: Oliver Schinagl <[email protected]>

The A31 uses the AXP221 pmic for various voltages.

Signed-off-by Oliver Schinagl <[email protected]>

---
 board/sunxi/board.c    |  26 +++++++
 drivers/power/Kconfig  |  47 ++++++++++++
 drivers/power/Makefile |   1 +
 drivers/power/axp221.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/axp221.h       |  42 ++++++++++
 5 files changed, 321 insertions(+)
 create mode 100644 drivers/power/axp221.c
 create mode 100644 include/axp221.h

board/sunxi/board.c +26 -0

index 03890c8..e6ec5b8 100644
@@ -19,6 +19,9 @@
 #ifdef CONFIG_AXP209_POWER
 #include <axp209.h>
 #endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dram.h>

@@ -169,6 +172,29 @@ void sunxi_board_init(void)
 	power_failed |= axp209_set_ldo3(2800);
 	power_failed |= axp209_set_ldo4(2800);
 #endif
+#ifdef CONFIG_AXP221_POWER
+	power_failed = axp221_init();
+	power_failed |= axp221_set_dcdc1(3000);
+	power_failed |= axp221_set_dcdc2(1200);
+	power_failed |= axp221_set_dcdc3(1200);
+	power_failed |= axp221_set_dcdc4(1200);
+	power_failed |= axp221_set_dcdc5(1500);
+#if CONFIG_AXP221_DLDO1_VOLT != -1
+	power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
+#endif
+#if CONFIG_AXP221_DLDO4_VOLT != -1
+	power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO1_VOLT != -1
+	power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO2_VOLT != -1
+	power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO3_VOLT != -1
+	power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
+#endif
+#endif
 
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();

drivers/power/Kconfig +47 -0

47 lines not on this page · raw message

drivers/power/Makefile +1 -0

index dc64e4d..04bd996 100644
@@ -7,6 +7,7 @@
 
 obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
+obj-$(CONFIG_AXP221_POWER)	+= axp221.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
 obj-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o

drivers/power/axp221.c new file +205 -0

205 lines not on this page · raw message

include/axp221.h new file +42 -0

42 lines not on this page · raw message

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:19 UTC #5 lore raw

PATCH v3 2/11 sun6i: Add basic axp221 driver

Quoted 6 lines · Hans de Goede

From: Oliver Schinagl <[email protected]>
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by Oliver Schinagl <[email protected]>
Signed-off-by Hans de Goede <[email protected]>

drivers/power/axp221.c line 182

Quoted 8 lines

drivers/power/axp221.c new file +8 -0

+	cfg |= 1 << 7;
+	cfg |= 1 << 3;
+	cfg |= 1 << 4;
+	cfg |= 1 << 5;
+	cfg |= 1 << 6;
+	cfg |= 1 << 6;
+	cfg |= 1 << 7;
+	cfg |= 1 << 7;

Could we get some symbolic names for these please?

Looks like a helper to read/modify/write a p2wi register would reduce the repetition a fair bit.

Ian.

Hans de Goede

author

2014-11-07 19:47 UTC #6 lore raw

PATCH v3 3/11 sun6i: Add clock functions needed for SPL / DRAM init

Add clock_init_safe and clockset_pll5 functions, as these are needed for SPL support resp. DRAM init (which is needed for SPL too).

Also add some extra clock register constant defines.

---
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c        | 77 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/clock.h       |  1 +
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 27 +++++++++-
 arch/arm/include/asm/arch-sunxi/prcm.h        |  1 +
 include/configs/sun6i.h                       |  1 +
 5 files changed, 106 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/sunxi/clock_sun6i.c +77 -0

index 1eae976..16ab6f3 100644
@@ -16,6 +16,33 @@
 #include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_prcm_reg * const prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	/* Set PLL ldo voltage without this PLL6 does not work properly */
+	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+			PRCM_PLL_CTRL_LDO_KEY);
+	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+		PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+	clock_set_pll1(408000000);
+
+	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+
+	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
+	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+}
+#endif
+
 void clock_init_uart(void)
 {
 	struct sunxi_ccm_reg *const ccm =

@@ -65,6 +92,56 @@ int clock_twi_onoff(int port, int state)
 	return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int k = 1;
+	int m = 1;
+
+	if (clk > 1152000000) {
+		k = 2;
+	} else if (clk > 768000000) {
+		k = 3;
+		m = 2;
+	}
+
+	/* Switch to 24MHz clock while changing PLL1 */
+	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+	       ATB_DIV_2 << ATB_DIV_SHIFT |
+	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+
+	/* PLL1 rate = 24000000 * n * k / m */
+	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
+	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+	sdelay(200);
+
+	/* Switch CPU to PLL1 */
+	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+	       ATB_DIV_2 << ATB_DIV_SHIFT |
+	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int k = 2;
+	const int m = 1;
+
+	/* PLL5 rate = 24000000 * n * k / m */
+	writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+	       CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
+	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
+
+	udelay(5500);
+}
+
 unsigned int clock_get_pll6(void)
 {
 	struct sunxi_ccm_reg *const ccm =

arch/arm/include/asm/arch-sunxi/clock.h +1 -0

index 42382a8..b40c16b 100644
@@ -25,6 +25,7 @@
 int clock_init(void);
 int clock_twi_onoff(int port, int state);
 void clock_set_pll1(unsigned int hz);
+void clock_set_pll5(unsigned int hz);
 unsigned int clock_get_pll5p(void);
 unsigned int clock_get_pll6(void);
 void clock_init_safe(void);

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +26 -1

index 1397b35..4992dbc 100644
@@ -170,7 +170,17 @@ struct sunxi_ccm_reg {
 #define CPU_CLK_SRC_OSC24M		1
 #define CPU_CLK_SRC_PLL1		2
 
-#define PLL1_CFG_DEFAULT		0x90011b21
+#define CCM_PLL1_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
+#define CCM_PLL1_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
+#define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL1_CTRL_MAGIC		(0x1 << 16)
+#define CCM_PLL1_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
+#define CCM_PLL5_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
+#define CCM_PLL5_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_UPD		(0x1 << 20)
+#define CCM_PLL5_CTRL_EN		(0x1 << 31)
 
 #define PLL6_CFG_DEFAULT		0x90041811

@@ -179,6 +189,11 @@ struct sunxi_ccm_reg {
 #define CCM_PLL6_CTRL_K_SHIFT		4
 #define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
 
+#define AHB1_ABP1_DIV_DEFAULT		0x00002020
+
+#define AXI_GATE_OFFSET_DRAM		0
+
+#define AHB_GATE_OFFSET_MCTL		14
 #define AHB_GATE_OFFSET_MMC3		11
 #define AHB_GATE_OFFSET_MMC2		10
 #define AHB_GATE_OFFSET_MMC1		9

@@ -190,6 +205,16 @@ struct sunxi_ccm_reg {
 
 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
 
+#define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
+
+#define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
+#define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
+#define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
+#define CCM_DRAMCLK_CFG_RST		(0x1 << 31)
+
+#define MBUS_CLK_DEFAULT		0x81000001 /* PLL6 / 2 */
+
+#define AHB_RESET_OFFSET_MCTL		14
 #define AHB_RESET_OFFSET_MMC3		11
 #define AHB_RESET_OFFSET_MMC2		10
 #define AHB_RESET_OFFSET_MMC1		9

arch/arm/include/asm/arch-sunxi/prcm.h +1 -0

index 3d3bfa6..88de1ff 100644
@@ -119,6 +119,7 @@
 #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
 	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
 #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
 
 #define PRCM_CLK_1WIRE_GATE (0x1 << 31)

include/configs/sun6i.h +1 -0

index b714474..9558771 100644
@@ -14,6 +14,7 @@
 /*
  * A31 specific configuration
  */
+#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #define CONFIG_SYS_PROMPT		"sun6i# "

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:20 UTC #7 lore raw

PATCH v3 3/11 sun6i: Add clock functions needed for SPL / DRAM init

Quoted 6 lines · Hans de Goede

Add clock_init_safe and clockset_pll5 functions, as these are needed for SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by Hans de Goede <[email protected]>

Hans de Goede

author

2014-11-07 19:47 UTC #8 lore raw

PATCH v3 4/11 sun6i: Add cpucfg register definitions

Not used atm, for future use (e.g. PSCI).

---
 arch/arm/cpu/armv7/sunxi/psci.S                |  4 +-
 arch/arm/include/asm/arch-sunxi/cpu.h          |  3 +-
 arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h | 67 ++++++++++++++++++++++++++
 3 files changed, 71 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h

arch/arm/cpu/armv7/sunxi/psci.S +2 -2

index 0084c81..b9ea78b 100644
@@ -87,8 +87,8 @@ psci_cpu_on:
 	str	r2, [r0]
 	dsb
 
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
+	movw	r0, #(SUN7I_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUN7I_CPUCFG_BASE >> 16)
 
 	@ CPU mask
 	and	r1, r1, #3	@ only care about first cluster

arch/arm/include/asm/arch-sunxi/cpu.h +2 -1

index 0de79a0..d34690e 100644
@@ -70,7 +70,7 @@
 
 #define SUNXI_TP_BASE			0x01c25000
 #define SUNXI_PMU_BASE			0x01c25400
-#define SUNXI_CPUCFG_BASE              0x01c25c00
+#define SUN7I_CPUCFG_BASE              0x01c25c00
 
 #define SUNXI_UART0_BASE		0x01c28000
 #define SUNXI_UART1_BASE		0x01c28400

@@ -111,6 +111,7 @@
 #define SUNXI_AVG_BASE			0x01ea0000
 
 #define SUNXI_PRCM_BASE			0x01f01400
+#define SUN6I_CPUCFG_BASE		0x01f01c00
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
 #define SUNXI_P2WI_BASE			0x01f03400

arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h new file +67 -0

67 lines not on this page · raw message

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:20 UTC #9 lore raw

PATCH v3 4/11 sun6i: Add cpucfg register definitions

Quoted 3 lines · Hans de Goede

Not used atm, for future use (e.g. PSCI).
Signed-off-by Hans de Goede <[email protected]>

Hans de Goede

author

2014-11-07 19:47 UTC #10 lore raw

PATCH v3 5/11 sun4i: Rename dram files to dram_sun4i.x

In preparation for adding sun6i dram support.

---
 arch/arm/cpu/armv7/sunxi/Makefile            |   6 +-
 arch/arm/cpu/armv7/sunxi/dram.c              | 750 ---------------------------
 arch/arm/cpu/armv7/sunxi/dram_sun4i.c        | 750 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/dram.h       | 167 +-----
 arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 182 +++++++
 5 files changed, 937 insertions(+), 918 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/sunxi/dram.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun4i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun4i.h

arch/arm/cpu/armv7/sunxi/Makefile +3 -3

index b3a3601..48cca0b 100644
@@ -28,9 +28,9 @@ endif
 endif
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I)	+= dram.o
-obj-$(CONFIG_MACH_SUN5I)	+= dram.o
-obj-$(CONFIG_MACH_SUN7I)	+= dram.o
+obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i.o
+obj-$(CONFIG_MACH_SUN5I)	+= dram_sun4i.o
+obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o
 endif

arch/arm/cpu/armv7/sunxi/dram.c deleted +0 ~~-750~~

750 lines not on this page · raw message

arch/arm/cpu/armv7/sunxi/dram_sun4i.c new file +750 -0

750 lines not on this page · raw message

arch/arm/include/asm/arch-sunxi/dram.h +2 ~~-165~~

174 lines not on this page · raw message

arch/arm/include/asm/arch-sunxi/dram_sun4i.h new file +182 -0

182 lines not on this page · raw message

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:21 UTC #11 lore raw

PATCH v3 5/11 sun4i: Rename dram files to dram_sun4i.x

Quoted 3 lines · Hans de Goede

In preparation for adding sun6i dram support.
Signed-off-by Hans de Goede <[email protected]>

Hans de Goede

author

2014-11-07 19:47 UTC #12 lore raw

PATCH v3 6/11 sun6i: Add dram initialization code

Add full support for dram initialization, using a fixed clock and autodetection of the memory organization (numbers of channels, bus-width, etc.).

This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK, extended with extra initialization sequences and the autodetect algorithm from boot0.

---
 arch/arm/cpu/armv7/sunxi/Makefile            |   1 +
 arch/arm/cpu/armv7/sunxi/dram_sun6i.c        | 436 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/cpu.h        |   8 +-
 arch/arm/include/asm/arch-sunxi/dram.h       |   4 +
 arch/arm/include/asm/arch-sunxi/dram_sun6i.h | 359 ++++++++++++++++++++++
 5 files changed, 805 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun6i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun6i.h

arch/arm/cpu/armv7/sunxi/Makefile +1 -0

index 48cca0b..3b6ae47 100644
@@ -30,6 +30,7 @@ endif
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun4i.o
+obj-$(CONFIG_MACH_SUN6I)	+= dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o

arch/arm/cpu/armv7/sunxi/dram_sun6i.c new file +436 -0

436 lines not on this page · raw message

arch/arm/include/asm/arch-sunxi/cpu.h +5 -3

index d34690e..6550e50 100644
@@ -96,9 +96,10 @@
 #define SUNXI_GMAC_BASE			0x01c50000
 
 #define SUNXI_DRAM_COM_BASE		0x01c62000
-#define SUNXI_DRAM_CTL_BASE		0x01c63000
-#define SUNXI_DRAM_PHY_CH1_BASE		0x01c65000
-#define SUNXI_DRAM_PHY_CH2_BASE		0x01c66000
+#define SUNXI_DRAM_CTL0_BASE		0x01c63000
+#define SUNXI_DRAM_CTL1_BASE		0x01c64000
+#define SUNXI_DRAM_PHY0_BASE		0x01c65000
+#define SUNXI_DRAM_PHY1_BASE		0x01c66000
 
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000

@@ -110,6 +111,7 @@
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
 #define SUN6I_CPUCFG_BASE		0x01f01c00
 #define SUNXI_R_UART_BASE		0x01f02800

arch/arm/include/asm/arch-sunxi/dram.h +4 -0

index c58971d..9072e68 100644
@@ -15,7 +15,11 @@
 #include <linux/types.h>
 
 /* dram regs definition */
+#if defined(CONFIG_MACH_SUN6I)
+#include <asm/arch/dram_sun6i.h>
+#else
 #include <asm/arch/dram_sun4i.h>
+#endif
 
 unsigned long sunxi_dram_init(void);

arch/arm/include/asm/arch-sunxi/dram_sun6i.h new file +359 -0

359 lines not on this page · raw message

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:25 UTC #13 lore raw

PATCH v3 6/11 sun6i: Add dram initialization code

Quoted 8 lines · Hans de Goede

Add full support for dram initialization, using a fixed clock and autodetection of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK, extended with extra initialization sequences and the autodetect algorithm from boot0.
Signed-off-by Hans de Goede <[email protected]>

arch/arm/cpu/armv7/sunxi/dram_sun6i.c line 324

Quoted 2 lines

arch/arm/cpu/armv7/sunxi/dram_sun6i.c new file +2 -0
+	/* Bunch of magic writes performed by boot0 */
+	writel(0x00400302, &mctl_com->rmcr[0]);

[...]

:-/ Have you pinged Allwinner about these/docs for these?

Ian.

Hans de Goede

author

2014-11-08 10:35 UTC #14 lore raw

PATCH v3 6/11 sun6i: Add dram initialization code

Hi,

Thanks for all the reviews!

Quoted 10 lines · Ian Campbell

Quoted 8 lines · Hans de Goede
Add full support for dram initialization, using a fixed clock and autodetection of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK, extended with extra initialization sequences and the autodetect algorithm from boot0.
Signed-off-by Hans de Goede <[email protected]>

Quoted 7 lines

Acked-by Ian Campbell <[email protected]>
arch/arm/cpu/armv7/sunxi/dram_sun6i.c line 324
Quoted 2 lines
arch/arm/cpu/armv7/sunxi/dram_sun6i.c new file +2 -0
+	/* Bunch of magic writes performed by boot0 */
+	writel(0x00400302, &mctl_com->rmcr[0]);
[...]
:-/ Have you pinged Allwinner about these/docs for these?

No, and neither for the next patch. I'll drop them a mail. In this case in the mean time I think I know what this is, this is *probably* setting up access rights / priorities for all the DRAM masters.

Regards,

Hans

Hans de Goede

author

2014-11-07 19:47 UTC #15 lore raw

PATCH v3 7/11 sun6i: Poke magic sram controller register to avoid cache issues

Without this the cache will only work in write-through mode, and as soon as it is put in write-back mode things break.

---
 arch/arm/cpu/armv7/sunxi/board.c | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm/cpu/armv7/sunxi/board.c +5 -0

index 6c812fc..9b3e80c 100644
@@ -114,6 +114,11 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
+#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+	/* Magic (undocmented) value taken from boot0, without this DRAM
+	 * access gets messed up (seems cache related) */
+	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
 		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:26 UTC #16 lore raw

PATCH v3 7/11 sun6i: Poke magic sram controller register to avoid cache issues

Quoted 4 lines · Hans de Goede

Without this the cache will only work in write-through mode, and as soon as it is put in write-back mode things break.
Signed-off-by Hans de Goede <[email protected]>

Urk. Have Allwinner been prodded?

Hans de Goede

author

2014-11-07 19:47 UTC #17 lore raw

PATCH v3 8/11 sun6i: Enable SPL

Enable the SPL now that we've all the necessary bits in place.

---
 board/sunxi/Kconfig        | 1 +
 configs/Colombus_defconfig | 9 +++++----
 2 files changed, 6 insertions(+), 4 deletions(-)

board/sunxi/Kconfig +1 -0

index 5b2d091..6688386 100644
@@ -16,6 +16,7 @@ config MACH_SUN5I
 config MACH_SUN6I
 	bool "sun6i (Allwinner A31)"
 	select CPU_V7
+	select SUPPORT_SPL
 
 config MACH_SUN7I
 	bool "sun7i (Allwinner A20)"

configs/Colombus_defconfig +5 -4

index 89291f9..bef568d 100644
@@ -1,5 +1,6 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN6I=y
-CONFIG_TARGET_COLOMBUS=y
+CONFIG_SPL=y
 CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_TARGET_COLOMBUS=y

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:26 UTC #18 lore raw

PATCH v3 8/11 sun6i: Enable SPL

Quoted 3 lines · Hans de Goede

Enable the SPL now that we've all the necessary bits in place.
Signed-off-by Hans de Goede <[email protected]>

Hans de Goede

author

2014-11-07 19:47 UTC #19 lore raw

PATCH v3 9/11 sun6i: Add Mele M9 board

---
 board/sunxi/Kconfig       |  4 ++++
 board/sunxi/MAINTAINERS   |  1 +
 configs/Mele_M9_defconfig | 15 +++++++++++++++
 3 files changed, 20 insertions(+)
 create mode 100644 configs/Mele_M9_defconfig

board/sunxi/Kconfig +4 -0

index 6688386..5c3b932 100644
@@ -112,6 +112,10 @@ config TARGET_MELE_M3
 	bool "MELE_M3"
 	depends on MACH_SUN7I
 
+config TARGET_MELE_M9
+	bool "MELE_M9"
+	depends on MACH_SUN6I
+
 config TARGET_MINI_X_1GB
 	bool "MINI_X_1GB"
 	depends on MACH_SUN4I

board/sunxi/MAINTAINERS +1 -0

index b3c77a8..ca03002 100644
@@ -9,6 +9,7 @@ F:	configs/Cubieboard_defconfig
 F:	configs/Mele_A1000_defconfig
 F:	configs/Mele_A1000G_defconfig
 F:	configs/Mele_M3_defconfig
+F:	configs/Mele_M9_defconfig
 F:	configs/Mini-X_defconfig
 F:	configs/Mini-X-1Gb_defconfig
 F:	include/configs/sun5i.h

configs/Mele_M9_defconfig new file +15 -0

new file mode 100644
index 0000000..3dacb19
@@ -0,0 +1,15 @@
+CONFIG_SPL=y
+CONFIG_FDTFILE="sun6i-a31-m9.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_TARGET_MELE_M9=y
+# Ethernet phy power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
+# USB hub power
++S:CONFIG_AXP221_DLDO4_VOLT=3300
+# Wifi power
++S:CONFIG_AXP221_ALDO1_VOLT=3300
+# HDMI power ?
++S:CONFIG_AXP221_ALDO2_VOLT=1800
++S:CONFIG_AXP221_ALDO3_VOLT=3000

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:27 UTC #20 lore raw

PATCH v3 9/11 sun6i: Add Mele M9 board

Quoted 1 line · Hans de Goede

Signed-off-by Hans de Goede <[email protected]>

Hans de Goede

author

2014-11-07 19:47 UTC #21 lore raw

PATCH v3 10/11 sunxi: ehci: Add proper Kconfig options to select the usb Vbus gpio-s

Add proper Kconfig options to select the usb Vbus gpio-s, besides moving to Kconfig being the right thing to do, an added advantage of this is that it allows for boards without Vbus gpio-s.

---
 board/sunxi/Kconfig                | 14 ++++++++++++++
 configs/A10s-OLinuXino-M_defconfig |  3 ++-
 configs/A13-OLinuXinoM_defconfig   |  3 ++-
 configs/A13-OLinuXino_defconfig    |  3 ++-
 configs/Auxtek-T004_defconfig      |  3 ++-
 configs/ba10_tv_box_defconfig      |  3 ++-
 configs/r7-tv-dongle_defconfig     |  3 ++-
 drivers/usb/host/ehci-sunxi.c      | 35 +++++++++++++++++++++++++----------
 include/configs/sun4i.h            |  7 -------
 include/configs/sun7i.h            |  7 -------
 10 files changed, 51 insertions(+), 30 deletions(-)

board/sunxi/Kconfig +14 -0

index 5c3b932..b2beea0 100644
@@ -197,4 +197,18 @@ config MMC_SUNXI_SLOT_EXTRA
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
 
+config USB1_VBUS_PIN
+	string "Vbus enable pin for usb1 (ehci0)"
+	default "PH6" if MACH_SUN4I || MACH_SUN7I
+	---help---
+	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
+	a string in the format understood by sunxi_name_to_gpio, e.g.
+	PH1 for pin 1 of port H.
+
+config USB2_VBUS_PIN
+	string "Vbus enable pin for usb2 (ehci1)"
+	default "PH3" if MACH_SUN4I || MACH_SUN7I
+	---help---
+	See USB1_VBUS_PIN help text.
+
 endif

configs/A10s-OLinuXino-M_defconfig +2 -1

index 6475675..94fafa6 100644
@@ -1,7 +1,8 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_USB1_VBUS_PIN="PB10"
 +S:CONFIG_MMC0_CD_PIN="PG1"
 +S:CONFIG_MMC1_CD_PIN="PG13"
 +S:CONFIG_ARM=y

configs/A13-OLinuXinoM_defconfig +2 -1

index d8b1239..8517203 100644
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
+CONFIG_USB1_VBUS_PIN="PG11"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y

configs/A13-OLinuXino_defconfig +2 -1

index 91039df..61f5466 100644
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
+CONFIG_USB1_VBUS_PIN="PG11"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y

configs/Auxtek-T004_defconfig +2 -1

index 5b06ea0..7fe9059 100644
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
+CONFIG_USB1_VBUS_PIN="PG13"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y

configs/ba10_tv_box_defconfig +2 -1

index 0a1abea..6ca7c57 100644
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
 CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
+CONFIG_USB1_VBUS_PIN="PH12"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN4I=y

configs/r7-tv-dongle_defconfig +2 -1

index 7dbff40..b9fd59c 100644
@@ -1,6 +1,7 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
 CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
+CONFIG_USB1_VBUS_PIN="PG13"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y
 +S:CONFIG_MACH_SUN5I=y

drivers/usb/host/ehci-sunxi.c +25 ~~-10~~

index 4befd57..193ac43 100644
@@ -39,7 +39,6 @@ static struct sunxi_ehci_hcd {
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY1_RST,
 		.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
-		.gpio_vbus = CONFIG_SUNXI_USB_VBUS0_GPIO,
 		.csr = (void *)SUNXI_USB_CSR,
 		.irq = 39,
 		.id = 1,

@@ -48,7 +47,6 @@ static struct sunxi_ehci_hcd {
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY2_RST,
 		.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
-		.gpio_vbus = CONFIG_SUNXI_USB_VBUS1_GPIO,
 		.csr = (void *)SUNXI_USB_CSR,
 		.irq = 40,
 		.id = 2,

@@ -68,6 +66,15 @@ static void *get_io_base(int hcd_id)
 		return NULL;
 }
 
+static int get_vbus_gpio(int hcd_id)
+{
+	switch (hcd_id) {
+	case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
+	case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+	}
+	return -1;
+}
+
 static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
 			  int data, int len)
 {

@@ -143,14 +150,16 @@ static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci)
 
 	sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN);
 
-	gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
+	if (sunxi_ehci->gpio_vbus != -1)
+		gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
 }
 
 static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
 {
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
+	if (sunxi_ehci->gpio_vbus != -1)
+		gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
 
 	sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);

@@ -165,13 +174,17 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
 	struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
 	int err;
 
+	sunxi_ehci->gpio_vbus = get_vbus_gpio(sunxi_ehci->id);
+
 	/* enable common PHY only once */
 	if (index == 0)
 		setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
 
-	err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus");
-	if (err)
-		return err;
+	if (sunxi_ehci->gpio_vbus != -1) {
+		err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus");
+		if (err)
+			return err;
+	}
 
 	sunxi_ehci_enable(sunxi_ehci);

@@ -197,9 +210,11 @@ int ehci_hcd_stop(int index)
 
 	sunxi_ehci_disable(sunxi_ehci);
 
-	err = gpio_free(sunxi_ehci->gpio_vbus);
-	if (err)
-		return err;
+	if (sunxi_ehci->gpio_vbus != -1) {
+		err = gpio_free(sunxi_ehci->gpio_vbus);
+		if (err)
+			return err;
+	}
 
 	/* disable common PHY only once, for the last enabled hcd */
 	if (enabled_hcd_count == 1)

include/configs/sun4i.h +0 -7

index e0ec52d..7b85740 100644
@@ -18,14 +18,7 @@
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
-
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
-#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO
-#define CONFIG_SUNXI_USB_VBUS0_GPIO	SUNXI_GPH(6)
-#endif
-#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO
-#define CONFIG_SUNXI_USB_VBUS1_GPIO	SUNXI_GPH(3)
-#endif
 #endif
 
 /*

include/configs/sun7i.h +0 -7

index 0193826..ea40790 100644
@@ -19,14 +19,7 @@
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI
-
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
-#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO
-#define CONFIG_SUNXI_USB_VBUS0_GPIO	SUNXI_GPH(6)
-#endif
-#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO
-#define CONFIG_SUNXI_USB_VBUS1_GPIO	SUNXI_GPH(3)
-#endif
 #endif
 
 #define CONFIG_ARMV7_VIRT		1

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:28 UTC #22 lore raw

PATCH v3 10/11 sunxi: ehci: Add proper Kconfig options to select the usb Vbus gpio-s

Quoted 5 lines · Hans de Goede

Add proper Kconfig options to select the usb Vbus gpio-s, besides moving to Kconfig being the right thing to do, an added advantage of this is that it allows for boards without Vbus gpio-s.
Signed-off-by Hans de Goede <[email protected]>

Hans de Goede

author

2014-11-07 19:47 UTC #23 lore raw

PATCH v3 11/11 sun6i: ehci: Add sun6i ehci support

Add support for the 2 ehci controllers found on the sun6i (A31) soc.

---
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h |  3 ++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 +++++++
 arch/arm/include/asm/arch-sunxi/cpu.h         |  8 +++++
 board/sunxi/Kconfig                           |  2 ++
 configs/Mele_M9_defconfig                     |  3 ++
 drivers/usb/host/ehci-sunxi.c                 | 45 +++++++++++++++++----------
 include/configs/sun6i.h                       |  5 +++
 7 files changed, 61 insertions(+), 16 deletions(-)

arch/arm/include/asm/arch-sunxi/clock_sun4i.h +3 -0

index 90af8e2..9dca800 100644
@@ -262,5 +262,8 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
 #define CCM_USB_CTRL_PHYGATE (0x1 << 8)
+/* These 2 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY1_CLK 0
+#define CCM_USB_CTRL_PHY2_CLK 0
 
 #endif /* _SUNXI_CLOCK_SUN4I_H */

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +11 -0

index 4992dbc..e16a764 100644
@@ -193,6 +193,10 @@ struct sunxi_ccm_reg {
 
 #define AXI_GATE_OFFSET_DRAM		0
 
+#define AHB_GATE_OFFSET_USB_OHCI1	30
+#define AHB_GATE_OFFSET_USB_OHCI0	29
+#define AHB_GATE_OFFSET_USB_EHCI1	27
+#define AHB_GATE_OFFSET_USB_EHCI0	26
 #define AHB_GATE_OFFSET_MCTL		14
 #define AHB_GATE_OFFSET_MMC3		11
 #define AHB_GATE_OFFSET_MMC2		10

@@ -205,6 +209,13 @@ struct sunxi_ccm_reg {
 
 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
 
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+
 #define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
 
 #define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)

arch/arm/include/asm/arch-sunxi/cpu.h +8 -0

index 6550e50..bdee89e 100644
@@ -37,16 +37,24 @@
 #define SUNXI_MMC1_BASE			0x01c10000
 #define SUNXI_MMC2_BASE			0x01c11000
 #define SUNXI_MMC3_BASE			0x01c12000
+#ifndef CONFIG_MACH_SUN6I
 #define SUNXI_USB0_BASE			0x01c13000
 #define SUNXI_USB1_BASE			0x01c14000
+#endif
 #define SUNXI_SS_BASE			0x01c15000
 #define SUNXI_HDMI_BASE			0x01c16000
 #define SUNXI_SPI2_BASE			0x01c17000
 #define SUNXI_SATA_BASE			0x01c18000
+#ifndef CONFIG_MACH_SUN6I
 #define SUNXI_PATA_BASE			0x01c19000
 #define SUNXI_ACE_BASE			0x01c1a000
 #define SUNXI_TVE1_BASE			0x01c1b000
 #define SUNXI_USB2_BASE			0x01c1c000
+#else
+#define SUNXI_USB0_BASE			0x01c19000
+#define SUNXI_USB1_BASE			0x01c1a000
+#define SUNXI_USB2_BASE			0x01c1b000
+#endif
 #define SUNXI_CSI1_BASE			0x01c1d000
 #define SUNXI_TZASC_BASE		0x01c1e000
 #define SUNXI_SPI3_BASE			0x01c1f000

board/sunxi/Kconfig +2 -0

index b2beea0..c3f865d 100644
@@ -200,6 +200,7 @@ config MMC_SUNXI_SLOT_EXTRA
 config USB1_VBUS_PIN
 	string "Vbus enable pin for usb1 (ehci0)"
 	default "PH6" if MACH_SUN4I || MACH_SUN7I
+	default "PH27" if MACH_SUN6I
 	---help---
 	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
 	a string in the format understood by sunxi_name_to_gpio, e.g.

@@ -208,6 +209,7 @@ config USB1_VBUS_PIN
 config USB2_VBUS_PIN
 	string "Vbus enable pin for usb2 (ehci1)"
 	default "PH3" if MACH_SUN4I || MACH_SUN7I
+	default "PH24" if MACH_SUN6I
 	---help---
 	See USB1_VBUS_PIN help text.

configs/Mele_M9_defconfig +3 -0

index 3dacb19..f46439f 100644
@@ -1,4 +1,5 @@
 CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
 CONFIG_FDTFILE="sun6i-a31-m9.dtb"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y

@@ -13,3 +14,5 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb"
 # HDMI power ?
 +S:CONFIG_AXP221_ALDO2_VOLT=1800
 +S:CONFIG_AXP221_ALDO3_VOLT=3000
+# No Vbus gpio for usb1
++S:CONFIG_USB1_VBUS_PIN=""

drivers/usb/host/ehci-sunxi.c +29 ~~-16~~

106 lines not on this page · raw message

include/configs/sun6i.h +5 -0

index 9558771..1b73852 100644
@@ -18,6 +18,11 @@
 
 #define CONFIG_SYS_PROMPT		"sun6i# "
 
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_SUNXI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
 /*
  * Include common sunxi configuration where most the settings are
  */

Signature · 1 line

2.1.0

Ian Campbell

2014-11-08 10:30 UTC #24 lore raw

PATCH v3 11/11 sun6i: ehci: Add sun6i ehci support

Quoted 3 lines · Hans de Goede

Add support for the 2 ehci controllers found on the sun6i (A31) soc.
Signed-off-by Hans de Goede <[email protected]>

You should probably run this by the usb custodian (Marek?) but for my part: