ARM: tegra: Add support for norrin board

From: Allen Martin <[email protected]>

Norrin (PM370) is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This board is also refered to as "nyan" in the ChromeOS trees.

This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB).

(rebase, fix pinmux that resets norrin)

---

Changes in v2:
- Rebase and adjust for Kconfig
- Fix up pinmux that reset norrin
- Add note as to the Chromebook's retail name, since it is now released

 arch/arm/cpu/armv7/tegra124/Kconfig        |  11 ++
 arch/arm/dts/Makefile                      |   1 +
 arch/arm/dts/tegra124-norrin.dts           |  92 +++++++++
 board/nvidia/norrin/Kconfig                |  24 +++
 board/nvidia/norrin/MAINTAINERS            |   6 +
 board/nvidia/norrin/Makefile               |   9 +
 board/nvidia/norrin/norrin.c               |  29 +++
 board/nvidia/norrin/pinmux-config-norrin.h | 290 +++++++++++++++++++++++++++++
 board/nvidia/venice2/as3722_init.h         |   2 +-
 configs/norrin_defconfig                   |   5 +
 include/configs/norrin.h                   |  76 ++++++++
 11 files changed, 544 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/tegra124-norrin.dts
 create mode 100644 board/nvidia/norrin/Kconfig
 create mode 100644 board/nvidia/norrin/MAINTAINERS
 create mode 100644 board/nvidia/norrin/Makefile
 create mode 100644 board/nvidia/norrin/norrin.c
 create mode 100644 board/nvidia/norrin/pinmux-config-norrin.h
 create mode 100644 configs/norrin_defconfig
 create mode 100644 include/configs/norrin.h

index 6a1c83a..db17819 100644
@@ -6,6 +6,16 @@ choice
 config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
 
+config TARGET_NORRIN
+	bool "NVIDIA Tegra124 Norrin"
+	help
+	  Norrin (PM370) is a Tegra124 clamshell board that is very similar
+	  to venice2, but it has a different panel, the sdcard CD and WP
+	  sense are flipped, and it has a different revision of the AS3722
+	  PMIC. This board is also refered to as "nyan" in the Chrome OS
+	  trees. The retail name is the Acer Chromebook 13 CB5-311-T7NN
+	  (13.3-inch HD, NVIDIA Tegra K1, 2GB).
+
 config TARGET_VENICE2
 	bool "NVIDIA Tegra124 Venice2"
 

@@ -15,6 +25,7 @@ config SYS_SOC
 	default "tegra124"
 
 source "board/nvidia/jetson-tk1/Kconfig"
+source "board/nvidia/norrin/Kconfig"
 source "board/nvidia/venice2/Kconfig"
 
 endif

index 52f8926..aa1e81a 100644
@@ -30,6 +30,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra30-tec-ng.dtb \
 	tegra114-dalmore.dtb \
 	tegra124-jetson-tk1.dtb \
+	tegra124-norrin.dtb \
 	tegra124-venice2.dtb
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc706.dtb \

new file mode 100644
index 0000000..cea6528
@@ -0,0 +1,24 @@
+if TARGET_NORRIN
+
+config SYS_CPU
+	string
+	default "arm720t" if SPL_BUILD
+	default "armv7" if !SPL_BUILD
+
+config SYS_BOARD
+	string
+	default "norrin"
+
+config SYS_VENDOR
+	string
+	default "nvidia"
+
+config SYS_SOC
+	string
+	default "tegra124"
+
+config SYS_CONFIG_NAME
+	string
+	default "norrin"
+
+endif

new file mode 100644
index 0000000..e1463ae
@@ -0,0 +1,6 @@
+NORRIN BOARD
+M:	Allen Martin <[email protected]>
+S:	Maintained
+F:	board/nvidia/norrin/
+F:	include/configs/norrin.h
+F:	configs/norrin_defconfig

new file mode 100644
index 0000000..5e490bb
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= ../venice2/as3722_init.o
+obj-y	+= norrin.o

new file mode 100644
index 0000000..6f0050c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-norrin.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_set_tristate_input_clamping();
+
+	gpio_config_table(norrin_gpio_inits,
+			  ARRAY_SIZE(norrin_gpio_inits));
+
+	pinmux_config_pingrp_table(norrin_pingrps,
+				   ARRAY_SIZE(norrin_pingrps));
+
+	pinmux_config_drvgrp_table(norrin_drvgrps,
+				   ARRAY_SIZE(norrin_drvgrps));
+}

index 06c366e..d1e0ec3 100644
@@ -18,7 +18,7 @@
 #define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
 #define AS3722_LDCONTROL_REG	0x4E
 
-#ifdef CONFIG_TARGET_JETSON_TK1
+#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NORRIN)
 #define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
 #else
 #define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)

new file mode 100644
index 0000000..a18c09b
@@ -0,0 +1,5 @@
++S:CONFIG_ARM=y
++S:CONFIG_TEGRA=y
++S:CONFIG_TEGRA124=y
++S:CONFIG_TARGET_NORRIN=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-norrin"

2.1.0.rc2.206.gedb03e5

Did the pinmux come directly from:
https://github.com/NVIDIA/tegra-pinmux-scripts

If not, we should fix the Norrin data that's there so that it's correct, and generates exactly what you want to check into U-Boot.

Hi Stephen,

Allen posted the original patch - my change was to take out the pinmux which causes the board to reset. Maybe that is a difference between nyan and norrin?

Regards,
Simon

Isn't Norrin a development board for that? I believe there are differences between Norrin and the final CB5. If this patch really is for CB5 specifically, shouldn't it be named that way? Ideally, the U-Boot board name should exactly match the DTB filename in the DT tree (i.e. arch/arm/boot/dts in the Linux kernel at present) so that the U-Boot environment doesn't have to override the automatic $dtbfile calculation.

Hi Stephen,

My intent was to get this patch merged as it has been sitting around for ages. I don't have a Norrin dev board though. We could perhaps have two device tree files but use a generic config?

Perhaps I was mislead by the comment that it is called 'nyan' in the Chrome OS tree. If you like I can change this to nyan?

Regards,
Simon