iMX6 SabreSD SPL Support

add the spl info in the header file.
Also, added a macro statement in m6sabre_common.h to avoid compiler warning.

Signed-off-by John Tobias <[email protected]>

---
 include/configs/mx6sabre_common.h | 2 ++
 include/configs/mx6sabresd.h      | 6 ++++++
 2 files changed, 8 insertions(+)

include/configs/mx6sabre_common.h +0 -0

index c81e9e9..e4d0d14 100644

Review

Quoted 5 lines

#define CONFIG_LOADADDR 0x12000000

(quoted diff) +2 -0

+#ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x17800000
+#endif

Why is that needed ? SPL does not use it, because it use CONFIG_SPL_TEXT_BASE, and this is defined in imx6_spl.h. And you do not redefine it, meaning that overwriting the value is not necessary at all, as we expect.

Hi John,

Quoted 10 lines · Stefano Babic

Review

Quoted 5 lines

#define CONFIG_LOADADDR 0x12000000

(quoted diff) +2 -0

+#ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x17800000
+#endif

Why is that needed ? SPL does not use it, because it use CONFIG_SPL_TEXT_BASE, and this is defined in imx6_spl.h. And you do not redefine it, meaning that overwriting the value is not necessary at all, as we expect.

Stefano is right.

You can simply remove this piece:

Hi Stefano,

Quoted 7 lines · Fabio Estevam

Sorry, I meant to remove only the ifdef:

include/configs/mx6sabre_common.h +0 -0

@@ -95,9 +95,7 @@
 #define CONFIG_BOOTDELAY               1
 

include/configs/mx6sabre_common.h line 100

Quoted 4 lines

include/configs/mx6sabre_common.h +0 -2

 #define CONFIG_LOADADDR                        0x12000000
-#ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x17800000
-#endif

Should John resend the series again with this change or can you remove the ifndef manually while applying it?

We already agree about the changes. There is no need to resend the patchset, I will fix it when I apply the patchset.

Hi Fabio, John,

Quoted 11 lines · Fabio Estevam

Hi Stefano,

Quoted 7 lines · Fabio Estevam

Sorry, I meant to remove only the ifdef:

include/configs/mx6sabre_common.h +0 -0

@@ -95,9 +95,7 @@
 #define CONFIG_BOOTDELAY               1
 

Quoted 8 lines

include/configs/mx6sabre_common.h line 100

Quoted 4 lines

include/configs/mx6sabre_common.h +0 -2

 #define CONFIG_LOADADDR                        0x12000000
-#ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x17800000
-#endif

Should John resend the series again with this change or can you remove the ifndef manually while applying it?

We already agree about the changes. There is no need to resend the patchset, I will fix it when I apply the patchset.

Best regards,
Stefano Babic

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Quoted 4 lines · Fabio Estevam

Hi John,

On Thu, Nov 13, 2014 at 6:58 AM, Stefano Babic <[email protected]> wrote:

Quoted 10 lines

Quoted 10 lines

Review

Quoted 5 lines

#define CONFIG_LOADADDR 0x12000000

(quoted diff) +2 -0

+#ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x17800000
+#endif

Why is that needed ? SPL does not use it, because it use CONFIG_SPL_TEXT_BASE, and this is defined in imx6_spl.h. And you do not redefine it, meaning that overwriting the value is not necessary at all, as we expect.

Quoted 8 lines

Stefano is right.

You can simply remove this piece:

include/configs/mx6sabre_common.h line 100

Quoted 6 lines

include/configs/mx6sabre_common.h +0 -3

@@ -95,9 +95,6 @@
 #define CONFIG_BOOTDELAY               1
 
 #define CONFIG_LOADADDR                        0x12000000
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE           0x17800000
-#endif

Sorry, I meant to remove only the ifdef:

include/configs/mx6sabre_common.h +0 -2

@@ -95,9 +95,7 @@
 #define CONFIG_BOOTDELAY               1
 
 #define CONFIG_LOADADDR                        0x12000000
-#ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE           0x17800000
-#endif

The CONFIG_SYS_TEXT_BASE was defined in imx6_spl.h and I was seeing previously some warning related to the duplication of the said macro.

I thought it would be great to remove the warning messages so that is why I added the macro.

This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port (Switch 1 or 2 of SW6)

Signed-off-by John Tobias <[email protected]>

---
 board/freescale/mx6sabresd/mx6sabresd.c | 186 +++++++++++++++++++++++++++++++-
 1 file changed, 184 insertions(+), 2 deletions(-)

board/freescale/mx6sabresd/mx6sabresd.c +174 -2

index 3d81fff..eda8497 100644
@@ -27,8 +27,12 @@
 #include <i2c.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
+#include <asm/arch/mx6-ddr.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BOOT_CFG	0x020D8004
+
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

@@ -55,8 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
+	gd->ram_size = imx_ddr_size();
 	return 0;
 }
 

@@ -253,6 +256,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
+#ifndef CONFIG_SPL_BUILD
 	s32 status = 0;
 	int i;
 

@@ -293,6 +297,43 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	return status;
+#else
+	unsigned reg = readl(BOOT_CFG) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x1:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x2:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x3:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
 }
 #endif
 

@@ -607,3 +648,144 @@ int checkboard(void)
 	puts("Board: MX6-SabreSD\n");
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 =  0x00020030,
+	.dram_sdclk_1 =  0x00020030,
+	.dram_cas =  0x00020030,
+	.dram_ras =  0x00020030,
+	.dram_reset =  0x00020030,
+	.dram_sdcke0 =  0x00003000,
+	.dram_sdcke1 =  0x00003000,
+	.dram_sdba2 =  0x00000000,
+	.dram_sdodt0 =  0x00003030,
+	.dram_sdodt1 =  0x00003030,
+	.dram_sdqs0 =  0x00000030,
+	.dram_sdqs1 =  0x00000030,
+	.dram_sdqs2 =  0x00000030,
+	.dram_sdqs3 =  0x00000030,
+	.dram_sdqs4 =  0x00000030,
+	.dram_sdqs5 =  0x00000030,
+	.dram_sdqs6 =  0x00000030,
+	.dram_sdqs7 =  0x00000030,
+	.dram_dqm0 =  0x00020030,
+	.dram_dqm1 =  0x00020030,
+	.dram_dqm2 =  0x00020030,
+	.dram_dqm3 =  0x00020030,
+	.dram_dqm4 =  0x00020030,
+	.dram_dqm5 =  0x00020030,
+	.dram_dqm6 =  0x00020030,
+	.dram_dqm7 =  0x00020030,
+};
+
+const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type =  0x000C0000,
+	.grp_ddrmode_ctl =  0x00020000,
+	.grp_ddrpke =  0x00000000,
+	.grp_addds =  0x00000030,
+	.grp_ctlds =  0x00000030,
+	.grp_ddrmode =  0x00020000,
+	.grp_b0ds =  0x00000030,
+	.grp_b1ds =  0x00000030,
+	.grp_b2ds =  0x00000030,
+	.grp_b3ds =  0x00000030,
+	.grp_b4ds =  0x00000030,
+	.grp_b5ds =  0x00000030,
+	.grp_b6ds =  0x00000030,
+	.grp_b7ds =  0x00000030,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x001F001F,
+	.p0_mpwldectrl1 =  0x001F001F,
+	.p1_mpwldectrl0 =  0x00440044,
+	.p1_mpwldectrl1 =  0x00440044,
+	.p0_mpdgctrl0 =  0x434B0350,
+	.p0_mpdgctrl1 =  0x034C0359,
+	.p1_mpdgctrl0 =  0x434B0350,
+	.p1_mpdgctrl1 =  0x03650348,
+	.p0_mprddlctl =  0x4436383B,
+	.p1_mprddlctl =  0x39393341,
+	.p0_mpwrdlctl =  0x35373933,
+	.p1_mpwrdlctl =  0x48254A36,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 64,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/*
+ * This section require the differentiation
+ * between iMX6 Sabre Families.
+ * But for now, it will configure only for
+ * SabreSD.
+ */
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = mem_ddr.width/32,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+#ifdef RTT_NOM_120OHM
+		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
+#else
+		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
+#endif
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	};
+
+	mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */

This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board. It tested the non-spl version of uboot as well.

After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.

sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync
sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69

Changes (v2):
Merged the SPL support into the main board file
Remove the compilation warmings

Changes (v3):
Removed sp and gd
Use imx_ddr_size to set the ram_size

Changes (v4):
Add a separate board configuration file to enable SPL (mx6sabresd_spl_defconfig).

Mapped DCD data to mx6_mmdc_calibration, mx6dq_iomux_grp_regs, mx6dq_iomux_ddr_regs and mx6_ddr3_cfg data structures.

Read 11 and 12 bits of BOOT_CFG register to actually determine the active mmc port.

Changes (v5):
Use the default CONFIG_SPL_STACK
Add a macro #ifndef for CONFIG_SYS_TEXT_BASE to avoid compilation warning.

Changes (v6):
Use board_mmc_init for spl mmc initialization instead of adding spl_board_mmc_init function

Changes (v7):
Corrected the chip select value and now the DRAM showing a correct 1 GiB.

This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board. It tested the non-spl version of uboot as well.

After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.

sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync
sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69

Changes (v2):
Merged the SPL support into the main board file
Remove the compilation warmings

Changes (v3):
Removed sp and gd
Use imx_ddr_size to set the ram_size

Changes (v4):
Add a separate board configuration file to enable SPL (mx6sabresd_spl_defconfig).

Mapped DCD data to mx6_mmdc_calibration, mx6dq_iomux_grp_regs, mx6dq_iomux_ddr_regs and mx6_ddr3_cfg data structures.

Read 11 and 12 bits of BOOT_CFG register to actually determine the active mmc port.

Changes (v5):
Use the default CONFIG_SPL_STACK
Add a macro #ifndef for CONFIG_SYS_TEXT_BASE to avoid compilation warning.

Changes (v6):
Use board_mmc_init for spl mmc initialization instead of adding spl_board_mmc_init function

Changes (v7):
Corrected the chip select value and now the DRAM showing a correct 1 GiB.

John Tobias (5):
imx6: add spl config for mx6sabresd
imx6: add data configuration file for SPL
kconfig: imx6: add SUPPORT_SPL
imx6: add spl in the header file
imx6: SPL support for iMX6 SabreSD

 arch/arm/Kconfig                              |   1 +
 board/freescale/mx6sabresd/mx6sabresd.c       | 186 +++++++++++++++++++++++++-
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg |  58 ++++++++
 configs/mx6sabresd_spl_defconfig              |   5 +
 include/configs/mx6sabre_common.h             |   2 +
 include/configs/mx6sabresd.h                  |   6 +
 6 files changed, 256 insertions(+), 2 deletions(-)
 create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
 create mode 100644 configs/mx6sabresd_spl_defconfig