imx: mx6q/dl sabre_common: Move MMC ENV offset to 512KB position

PATCH New Ye.Li 3 participants 5 messages Nov 12, 2014 – Nov 13, 2014

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Ye.Li

author

2014-11-12 06:02 UTC #0 lore raw

PATCH v2 1/2 imx: mx6q/dl sabre_common: Move MMC ENV offset to 512KB position

Set the CONFIG_ENV_OFFSET from 384KB to 512KB offset, so we will have larger space for u-boot image.
When enabling NAND flash support feature, the u-boot image size has exceeded the 384KB, which causes overlay to the environment variables storage.

Signed-off-by Ye.Li <[email protected]>

Acked-by Fabio Estevam <[email protected]>

---
Changes since v1:
- None

 include/configs/mx6sabre_common.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

include/configs/mx6sabre_common.h +1 -1

index c81e9e9..1e10422 100644
@@ -251,7 +251,7 @@
 #define CONFIG_ENV_IS_IN_MMC
 
 #if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_ENV_OFFSET		(8 * 64 * 1024)
 #endif
 
 #define CONFIG_OF_LIBFDT

Signature · 1 line

1.7.4.1

Ye.Li

author

2014-11-12 06:02 UTC #1 lore raw

PATCH v2 2/2 imx: mx6q/dlsabreauto: And NAND flash support

The i.MX6Q/DL sabreauto board has one NAND socket, set the CONFIG_NAND_MXS and relevant NAND configurations to enable the MXS NAND flash driver.
Add board level codes to set IOMUX and clock for GPMI-NAND and BCH module.

Signed-off-by Ye.Li <[email protected]>

---
Changes since v1:
- Use "static" for gpmi pad setting variable.
- Resolve line over 80 characters warning.

 board/freescale/mx6qsabreauto/mx6qsabreauto.c |   66 +++++++++++++++++++++++++
 include/configs/mx6qsabreauto.h               |   16 ++++++
 2 files changed, 82 insertions(+), 0 deletions(-)

board/freescale/mx6qsabreauto/mx6qsabreauto.c +66 -0

index 42ae6fa..c35dcaf 100644
@@ -46,6 +46,11 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
 int dram_init(void)

@@ -200,6 +205,63 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+	MX6_PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(GPMI_PAD_CTRL1),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
+	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+	clrbits_le32(&mxc_ccm->CCGR4,
+		MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable ENFC_CLK_ROOT clock */
+	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
 	unsigned short val;

@@ -336,6 +398,10 @@ int board_early_init_f(void)
 #ifdef CONFIG_VIDEO_IPUV3
 	setup_display();
 #endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
 	return 0;
 }

include/configs/mx6qsabreauto.h +16 -0

index 235dd6d..3f1c88e 100644
@@ -48,4 +48,20 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
 
+/* NAND flash command */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
 #endif                         /* __MX6QSABREAUTO_CONFIG_H */

Signature · 1 line

1.7.4.1

Fabio Estevam

2014-11-12 11:28 UTC #2 lore raw

PATCH v2 2/2 imx: mx6q/dlsabreauto: And NAND flash support

Quoted 7 lines · Ye.Li

The i.MX6Q/DL sabreauto board has one NAND socket, set the CONFIG_NAND_MXS and relevant NAND configurations to enable the MXS NAND flash driver.
Add board level codes to set IOMUX and clock for GPMI-NAND and BCH module.
Signed-off-by Ye.Li <[email protected]>

Reviewed-by Fabio Estevam <[email protected]>

Thanks

Stefano Babic

2014-11-13 15:33 UTC #3 lore raw

PATCH v2 2/2 imx: mx6q/dlsabreauto: And NAND flash support

In reply to Ye.Li

Quoted 8 lines · Ye.Li

The i.MX6Q/DL sabreauto board has one NAND socket, set the CONFIG_NAND_MXS and relevant NAND configurations to enable the MXS NAND flash driver.
Add board level codes to set IOMUX and clock for GPMI-NAND and BCH module.
Signed-off-by Ye.Li <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2014-11-13 15:33 UTC #4 lore raw

PATCH v2 1/2 imx: mx6q/dl sabre_common: Move MMC ENV offset to 512KB position

In reply to Ye.Li

include/configs/mx6sabre_common.h

Quoted 16 lines · Ye.Li

Set the CONFIG_ENV_OFFSET from 384KB to 512KB offset, so we will have larger space for u-boot image.
When enabling NAND flash support feature, the u-boot image size has exceeded the 384KB, which causes overlay to the environment variables storage.
Signed-off-by Ye.Li <[email protected]>
Acked-by Fabio Estevam <[email protected]>
---
Changes since v1:
- None
 include/configs/mx6sabre_common.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
include/configs/mx6sabre_common.h +0 -0
index c81e9e9..1e10422 100644

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================