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Addition of new board Peach-Pi

PATCH New Akshay Saraswat 2 participants 9 messages Nov 13, 2014 – Nov 17, 2014

Subsystems (2)
Arm (32-bit) Arm Samsung Exynos
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Akshay Saraswat

author
#0 lore raw

v4 cover Addition of new board Peach-Pi

Now we are adding a new Peach-Pi board which is a variant of Peach-Pit and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, hence, most of the hardware config and settings are reused for this board.

Changes since v1:
- Rebased all the patches

Changes since v2:
- Rebased all the patches
- Added new patch "Enable update mode for DREX controller"

Changes since v3:
- Rebased all the patches
- Added "Tested-by" and "Acked-by"
- In patch 3/7 fixed warning "line over 80 characters"

Akshay Saraswat (5):
Exynos5800: Introduce new proid for Exynos5800
Exynos5800: Add DTS for new board Peach-Pi
Config: Exynos5800: Enable build for Peach-Pi
Config: Exynos5420: Refactor SDRAM Bank and Size
Exynos5: ddr3: Choose between single or double channel config

Alim Akhtar (1):
DMC: Exynos5: Enable update mode for DREX controller

Vadim Bendebury (1):
Peach-Pi: Use the enhanced usb_copy() prototype

 arch/arm/cpu/armv7/exynos/Kconfig              |   7 +-
 arch/arm/cpu/armv7/exynos/clock.c              |  19 +--
 arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |   2 +-
 arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c      |  29 +++++
 arch/arm/cpu/armv7/exynos/pinmux.c             |   2 +-
 arch/arm/cpu/armv7/exynos/spl_boot.c           |  10 +-
 arch/arm/dts/Makefile                          |   3 +-
 arch/arm/dts/exynos5800-peach-pi.dts           | 157 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-exynos/cpu.h         |  10 +-
 arch/arm/include/asm/arch-exynos/dmc.h         |   1 +
 arch/arm/include/asm/arch-exynos/gpio.h        |   4 +-
 board/samsung/smdk5420/Kconfig                 |  16 +++
 board/samsung/smdk5420/MAINTAINERS             |   2 +
 configs/peach-pi_defconfig                     |   5 +
 include/configs/exynos5420-common.h            |   9 +-
 include/configs/peach-pi.h                     |  50 ++++++++
 include/configs/peach-pit.h                    |   8 +-
 include/configs/smdk5420.h                     |   4 +
 18 files changed, 313 insertions(+), 25 deletions(-)
 create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts
 create mode 100644 configs/peach-pi_defconfig
 create mode 100644 include/configs/peach-pi.h
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH v4 1/7 Exynos5800: Introduce new proid for Exynos5800

This patch intends to add a new proid for Exynos5800 which is a variant of Exynos5420. Product id for Exynos5800 is 0x5422. Both Exynos5420 and Exynos5800 are pin to pin compitable. This gives us an advantage of reusing Exynos5420 clock, pinmux, memory and other settings.

Signed-off-by Alim Akhtar <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

---
Changes since v3:
- Rebased this patch
- Added "Acked-by" and "Tested-by"

Changes since v2:
- Rebased this patch

Changes since v1:
- Rebased this patch

 arch/arm/cpu/armv7/exynos/clock.c              | 19 ++++++++++---------
 arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |  2 +-
 arch/arm/cpu/armv7/exynos/pinmux.c             |  2 +-
 arch/arm/include/asm/arch-exynos/cpu.h         | 10 +++++++++-
 arch/arm/include/asm/arch-exynos/gpio.h        |  4 ++--
 5 files changed, 23 insertions(+), 14 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +10 -9
index 7558eff..4ecce44 100644
@@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 			div = PLL_DIV_1024;
 		else if (proid_is_exynos4412())
 			div = PLL_DIV_65535;
-		else if (proid_is_exynos5250() || proid_is_exynos5420())
+		else if (proid_is_exynos5250() || proid_is_exynos5420()
+			 || proid_is_exynos5800())
 			div = PLL_DIV_65536;
 		else
 			return 0;

@@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void)
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_get_pll_clk(pllreg);
 		return exynos5_get_pll_clk(pllreg);
 	} else {

@@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void)
 unsigned long get_pwm_clk(void)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_get_pwm_clk();
 		return clock_get_periph_rate(PERIPH_ID_PWM0);
 	} else {

@@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void)
 unsigned long get_uart_clk(int dev_index)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_get_uart_clk(dev_index);
 		return exynos5_get_uart_clk(dev_index);
 	} else {

@@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index)
 unsigned long get_mmc_clk(int dev_index)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_get_mmc_clk(dev_index);
 		return exynos5_get_mmc_clk(dev_index);
 	} else {

@@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index)
 void set_mmc_clk(int dev_index, unsigned int div)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			exynos5420_set_mmc_clk(dev_index, div);
 		else
 			exynos5_set_mmc_clk(dev_index, div);

@@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void)
 	if (cpu_is_exynos4())
 		return exynos4_get_lcd_clk();
 	else {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_get_lcd_clk();
 		else
 			return exynos5_get_lcd_clk();

@@ -1682,7 +1683,7 @@ void set_lcd_clk(void)
 	else {
 		if (proid_is_exynos5250())
 			exynos5_set_lcd_clk();
-		else if (proid_is_exynos5420())
+		else if (proid_is_exynos5420() || proid_is_exynos5800())
 			exynos5420_set_lcd_clk();
 	}
 }

@@ -1696,7 +1697,7 @@ void set_mipi_clk(void)
 int set_spi_clk(int periph_id, unsigned int rate)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_set_spi_clk(periph_id, rate);
 		return exynos5_set_spi_clk(periph_id, rate);
 	} else {
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +1 -1
index b6a9bc1..0aff3d0 100644
@@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
 
 void system_clock_init(void)
 {
-	if (proid_is_exynos5420())
+	if (proid_is_exynos5420() || proid_is_exynos5800())
 		exynos5420_system_clock_init();
 	else
 		exynos5250_system_clock_init();
arch/arm/cpu/armv7/exynos/pinmux.c +1 -1
index 3d95dc3..94d0297 100644
@@ -837,7 +837,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
 int exynos_pinmux_config(int peripheral, int flags)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_pinmux_config(peripheral, flags);
 		else if (proid_is_exynos5250())
 			return exynos5_pinmux_config(peripheral, flags);
arch/arm/include/asm/arch-exynos/cpu.h +9 -1
index 78aceef..29674ad 100644
@@ -227,6 +227,13 @@ static inline void s5p_set_cpu_id(void)
 		/* Exynos5420 */
 		s5p_cpu_id = 0x5420;
 		break;
+	case 0x422:
+		/*
+		 * Exynos5800 is a variant of Exynos5420
+		 * and has product id 0x5422
+		 */
+		s5p_cpu_id = 0x5800;
+		break;
 	}
 }
 

@@ -255,6 +262,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210)
 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 IS_EXYNOS_TYPE(exynos5420, 0x5420)
+IS_EXYNOS_TYPE(exynos5800, 0x5800)
 
 #define SAMSUNG_BASE(device, base)				\
 static inline unsigned int __attribute__((no_instrument_function)) \

@@ -265,7 +273,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
 			return EXYNOS4X12_##base;		\
 		return EXYNOS4_##base;				\
 	} else if (cpu_is_exynos5()) {				\
-		if (proid_is_exynos5420())			\
+		if (proid_is_exynos5420() || proid_is_exynos5800())	\
 			return EXYNOS5420_##base;		\
 		return EXYNOS5_##base;				\
 	}							\
arch/arm/include/asm/arch-exynos/gpio.h +2 -2
index 02287de..9699954 100644
@@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
 static inline struct gpio_info *get_gpio_data(void)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return exynos5420_gpio_data;
 		else
 			return exynos5_gpio_data;

@@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void)
 static inline unsigned int get_bank_num(void)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420())
+		if (proid_is_exynos5420() || proid_is_exynos5800())
 			return EXYNOS5420_GPIO_NUM_PARTS;
 		else
 			return EXYNOS5_GPIO_NUM_PARTS;
Signature · 1 line
1.9.1
author
#2 lore raw

PATCH v4 2/7 Exynos5800: Add DTS for new board Peach-Pi

In reply to Akshay Saraswat

We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi differs from Peach-Pit in configuration factors like display resolution, memory size, SoC version etc.

Signed-off-by Alim Akhtar <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

---
Changes since v3:
- Rebased this patch
- Added "Acked-by" and "Tested-by"

Changes since v2:
- Rebased this patch

Changes since v1:
- Rebased this patch

 arch/arm/dts/Makefile                |   3 +-
 arch/arm/dts/exynos5800-peach-pi.dts | 157 +++++++++++++++++++++++++++++++++++
 2 files changed, 159 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts
arch/arm/dts/Makefile +2 -1
index 52f8926..4030220 100644
@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-smdk5250.dtb \
 	exynos5420-smdk5420.dtb \
-	exynos5420-peach-pit.dtb
+	exynos5420-peach-pit.dtb \
+	exynos5800-peach-pi.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
arch/arm/dts/exynos5800-peach-pi.dts new file +157 -0

157 lines not on this page · raw message

Signature · 1 line
1.9.1
author
#3 lore raw

PATCH v4 3/7 Config: Exynos5800: Enable build for Peach-Pi

In reply to Akshay Saraswat

This adds following things :
- New config and defconfig for Peach-Pi board.
- Alterations in Kconfig and MAINTAINERS.
- Addition of CONFIG_EXYNOS5800.
- ADdition of exynos5800-peach-pi in dts list.

Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

---
Changes since v3:
- Rebased this patch
- Added "Acked-by" and "Tested-by"
- Fixed warning "line over 80 characters" in file include/configs/exynos5420-common.h line # 13 and 42.

Changes since v2:
- Rebased this patch

Changes since v1:
- Rebased this patch

 arch/arm/cpu/armv7/exynos/Kconfig   |  7 +++++-
 board/samsung/smdk5420/Kconfig      | 16 +++++++++++++
 board/samsung/smdk5420/MAINTAINERS  |  2 ++
 configs/peach-pi_defconfig          |  5 ++++
 include/configs/exynos5420-common.h |  5 +++-
 include/configs/peach-pi.h          | 46 +++++++++++++++++++++++++++++++++++++
 include/configs/peach-pit.h         |  4 ++--
 7 files changed, 81 insertions(+), 4 deletions(-)
 create mode 100644 configs/peach-pi_defconfig
 create mode 100644 include/configs/peach-pi.h
arch/arm/cpu/armv7/exynos/Kconfig +6 -1
index 090be93..13dbd95 100644
@@ -44,11 +44,16 @@ config TARGET_SMDK5420
 	select SUPPORT_SPL
 	select OF_CONTROL if !SPL_BUILD
 
-config TARGET_PEACH_PIT
+config TARGET_PEACH_PI
 	bool "Peach Pi board"
 	select SUPPORT_SPL
 	select OF_CONTROL if !SPL_BUILD
 
+config TARGET_PEACH_PIT
+	bool "Peach Pit board"
+	select SUPPORT_SPL
+	select OF_CONTROL if !SPL_BUILD
+
 endchoice
 
 config SYS_SOC
board/samsung/smdk5420/Kconfig +16 -0
index d3a5b7f..e7aafe5 100644
@@ -1,3 +1,19 @@
+if TARGET_PEACH_PI
+
+config SYS_BOARD
+	string
+	default "smdk5420"
+
+config SYS_VENDOR
+	string
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	string
+	default "peach-pi"
+
+endif
+
 if TARGET_PEACH_PIT
 
 config SYS_BOARD
board/samsung/smdk5420/MAINTAINERS +2 -0
index e0f5c7a..1423f83 100644
@@ -6,3 +6,5 @@ F:	include/configs/peach-pit.h
 F:	configs/peach-pit_defconfig
 F:	include/configs/smdk5420.h
 F:	configs/smdk5420_defconfig
+F:	include/configs/peach-pi.h
+F:	configs/peach-pi_defconfig
configs/peach-pi_defconfig new file +5 -0
new file mode 100644
index 0000000..8ada0db
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
++S:CONFIG_TARGET_PEACH_PI=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
include/configs/exynos5420-common.h +4 -1
index b0f940c..03f941c 100644
@@ -10,6 +10,8 @@
 #define __CONFIG_EXYNOS5420_H
 
 #define CONFIG_EXYNOS5420
+/* A variant of Exynos5420 (Exynos5 Family) */
+#define CONFIG_EXYNOS5800
 
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SPI_FLASH

@@ -38,7 +40,8 @@
 
 #define CONFIG_SPL_MAX_FOOTPRINT	(30 * 1024)
 
-#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
+#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi"	\
+				"exynos5420-peach-pit exynos5420-smdk5420"
 
 #define CONFIG_MAX_I2C_NUM	11
include/configs/peach-pi.h new file +46 -0

46 lines not on this page · raw message

include/configs/peach-pit.h +2 -2
index 91bd37d..29a0996 100644
@@ -23,8 +23,8 @@
 /* select serial console configuration */
 #define CONFIG_SERIAL3		/* use SERIAL 3 */
 
-#define CONFIG_SYS_PROMPT	"Peach # "
-#define CONFIG_IDENT_STRING	" for Peach"
+#define CONFIG_SYS_PROMPT	"Peach-Pit # "
+#define CONFIG_IDENT_STRING	" for Peach-Pit"
 
 #define CONFIG_VIDEO_PARADE
Signature · 1 line
1.9.1
author
#4 lore raw

PATCH v4 4/7 DMC: Exynos5: Enable update mode for DREX controller

In reply to Akshay Saraswat

From: Alim Akhtar <[email protected]>

As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation.

Signed-off-by Alim Akhtar <[email protected]>
Signed-off-by Doug Anderson <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

---
Changes since v3:
- Rebased this patch
- Added "Acked-by" and "Tested-by"

Changes since v2:
- Rebased this patch

Changes since v1:
- Rebased this patch

 arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 19 +++++++++++++++++++
 arch/arm/include/asm/arch-exynos/dmc.h    |  1 +
 2 files changed, 20 insertions(+)
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +19 -0
index b86dd2d..4d73b45 100644
@@ -832,6 +832,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
 	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
 
+	/*
+	 * As per Exynos5800 UM ver 0.00 section 17.13.2.1
+	 * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
+	 * support the PHY initiated update. And it is recommended to set
+	 * this field to 1'b1 during initialization
+	 *
+	 * When we apply PHY-initiated mode, DLL lock value is determined
+	 * once at DMC init time and not updated later when we change the MIF
+	 * voltage based on ASV group in kernel. Applying MC-initiated mode
+	 * makes sure that DLL tracing is ON so that silicon is able to
+	 * compensate the voltage variation.
+	 */
+	val = readl(&drex0->concontrol);
+	val |= CONCONTROL_UPDATE_MODE;
+	writel(val , &drex0->concontrol);
+	val = readl(&drex1->concontrol);
+	val |= CONCONTROL_UPDATE_MODE;
+	writel(val , &drex1->concontrol);
+
 	return 0;
 }
 #endif
arch/arm/include/asm/arch-exynos/dmc.h +1 -0
index ec3f9b6..4990a1a 100644
@@ -450,6 +450,7 @@ enum mem_manuf {
 #define CONCONTROL_RD_FETCH_SHIFT	12
 #define CONCONTROL_RD_FETCH_MASK	(0x7 << CONCONTROL_RD_FETCH_SHIFT)
 #define CONCONTROL_AREF_EN_SHIFT	5
+#define CONCONTROL_UPDATE_MODE		(1 << 3)
 
 /* PRECHCONFIG register field */
 #define PRECHCONFIG_TP_CNT_SHIFT	24
Signature · 1 line
1.9.1
author
#5 lore raw

PATCH v4 5/7 Config: Exynos5420: Refactor SDRAM Bank and Size

In reply to Akshay Saraswat

Since, not every board may have all memory channels configured and all available banks of DMC used, we wish to refactor configs for Memory Bank size and numbers as per board memory config. For Example, Peach-Pit has 2GB memory and will be using only 4 banks but Peach-Pi has 3.5GB memory and will be using all 7 available SDRAM banks.

Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

---
Changes since v3:
- Rebased this patch
- Added "Acked-by" and "Tested-by"

Changes since v2:
- Rebased this patch

Changes since v1:
- Rebased this patch

 include/configs/exynos5420-common.h | 4 ----
 include/configs/peach-pi.h          | 4 ++++
 include/configs/peach-pit.h         | 4 ++++
 include/configs/smdk5420.h          | 4 ++++
 4 files changed, 12 insertions(+), 4 deletions(-)
include/configs/exynos5420-common.h +0 -4
index 03f941c..218d2b4 100644
@@ -57,10 +57,6 @@
  */
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
 
-/* DRAM Memory Banks */
-#define CONFIG_NR_DRAM_BANKS	7
-#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
-
 /* Miscellaneous configurable options */
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
include/configs/peach-pi.h +4 -0
index d8da7ef..8a82402 100644
@@ -43,4 +43,8 @@
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
 
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	7
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
 #endif	/* __CONFIG_PEACH_PI_H */
include/configs/peach-pit.h +4 -0
index 29a0996..ad5db57 100644
@@ -43,4 +43,8 @@
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
 
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	4
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
 #endif	/* __CONFIG_PEACH_PIT_H */
include/configs/smdk5420.h +4 -0
index fd2d482..5c9a3c0 100644
@@ -23,4 +23,8 @@
 #define CONFIG_IDENT_STRING	" for SMDK5420"
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	7
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
 #endif	/* __CONFIG_SMDK5420_H */
Signature · 1 line
1.9.1
author
#6 lore raw

PATCH v4 6/7 Exynos5: ddr3: Choose between single or double channel config

In reply to Akshay Saraswat

Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.

Signed-off-by Doug Anderson <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

---
Changes since v3:
- Rebased this patch
- Added "Acked-by" and "Tested-by"

Changes since v2:
- Rebased this patch

Changes since v1:
- Rebased this patch

 arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +10 -0
index 4d73b45..7c0b12a 100644
@@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 							+ DMC_OFFSET);
 	pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
 
+	if (CONFIG_NR_DRAM_BANKS > 4) {
+		/* Need both controllers. */
+		mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
+		mem->chips_per_channel = 2;
+		mem->chips_to_configure = 2;
+	} else {
+		/* 2GB requires a single controller */
+		mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
+	}
+
 	/* Enable PAUSE for DREX */
 	setbits_le32(&clk->pause, ENABLE_BIT);
Signature · 1 line
1.9.1
author
#7 lore raw

PATCH v4 7/7 Peach-Pi: Use the enhanced usb_copy() prototype

In reply to Akshay Saraswat

From: Vadim Bendebury <[email protected]>

Exynos5800 IROM has a different, from 5250 and 5420, prototype of the usb_copy() function. Luckily the earlier version did not expect any arguments, which means the same code could be used with old and new SoCs, the old ones just ignoring the arguments.

Signed-off-by Vadim Bendebury <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>
Tested-by Simon Glass <[email protected]>

---
Changes since v3:
- Rebased this patch
- Added "Acked-by" and "Tested-by"

Changes since v2:
- Added in this patch-set.

 arch/arm/cpu/armv7/exynos/spl_boot.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)
arch/arm/cpu/armv7/exynos/spl_boot.c +8 -2
index 658e4cb..dbd312c 100644
@@ -195,10 +195,16 @@ void copy_uboot_to_ram(void)
 	void (*end_bootop_from_emmc)(void);
 #endif
 #ifdef CONFIG_USB_BOOTING
-	u32 (*usb_copy)(void);
 	int is_cr_z_set;
 	unsigned int sec_boot_check;
 
+	/*
+	 * Note that older hardware (before Exynos5800) does not expect any
+	 * arguments, but it does not hurt to pass them, so a common function
+	 * prototype is used.
+	 */
+	u32 (*usb_copy)(u32 num_of_block, u32 *dst);
+
 	/* Read iRAM location to check for secondary USB boot mode */
 	sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
 	if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)

@@ -240,7 +246,7 @@ void copy_uboot_to_ram(void)
 		 */
 		is_cr_z_set = config_branch_prediction(0);
 		usb_copy = get_irom_func(USB_INDEX);
-		usb_copy();
+		usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
 		config_branch_prediction(is_cr_z_set);
 		break;
 #endif
Signature · 1 line
1.9.1
#8 lore raw

v4 cover Addition of new board Peach-Pi

In reply to Akshay Saraswat
Quoted 43 lines · Akshay Saraswat

Now we are adding a new Peach-Pi board which is a variant of Peach-Pit and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, hence, most of the hardware config and settings are reused for this board.

Changes since v1:
- Rebased all the patches

Changes since v2:
- Rebased all the patches
- Added new patch "Enable update mode for DREX controller"

Changes since v3:
- Rebased all the patches
- Added "Tested-by" and "Acked-by"
- In patch 3/7 fixed warning "line over 80 characters"

Akshay Saraswat (5):
Exynos5800: Introduce new proid for Exynos5800
Exynos5800: Add DTS for new board Peach-Pi
Config: Exynos5800: Enable build for Peach-Pi
Config: Exynos5420: Refactor SDRAM Bank and Size
Exynos5: ddr3: Choose between single or double channel config

Alim Akhtar (1):
DMC: Exynos5: Enable update mode for DREX controller

Vadim Bendebury (1):
Peach-Pi: Use the enhanced usb_copy() prototype

 arch/arm/cpu/armv7/exynos/Kconfig              |   7 +-
 arch/arm/cpu/armv7/exynos/clock.c              |  19 +--
 arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |   2 +-
 arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c      |  29 +++++
 arch/arm/cpu/armv7/exynos/pinmux.c             |   2 +-
 arch/arm/cpu/armv7/exynos/spl_boot.c           |  10 +-
 arch/arm/dts/Makefile                          |   3 +-
 arch/arm/dts/exynos5800-peach-pi.dts           | 157 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-exynos/cpu.h         |  10 +-
 arch/arm/include/asm/arch-exynos/dmc.h         |   1 +
 arch/arm/include/asm/arch-exynos/gpio.h        |   4 +-
 board/samsung/smdk5420/Kconfig                 |  16 +++
 board/samsung/smdk5420/MAINTAINERS             |   2 +
 configs/peach-pi_defconfig                     |   5 +
Quoted 9 lines
 include/configs/exynos5420-common.h            |   9 +-
 include/configs/peach-pi.h                     |  50 ++++++++
 include/configs/peach-pit.h                    |   8 +-
 include/configs/smdk5420.h                     |   4 +
 18 files changed, 313 insertions(+), 25 deletions(-)
 create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts
 create mode 100644 configs/peach-pi_defconfig
 create mode 100644 include/configs/peach-pi.h

applied to u-boot-samsung.

Thanks,
Minkyu Kang.