Update gdsys board support

index af0d602..a9cfc10 100644
@@ -35,6 +35,7 @@
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
 

@@ -59,8 +60,14 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
 #undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])

index 593b9b8..ce9af8f 100644
@@ -333,6 +333,57 @@ static const struct amd_flash_info jedec_table[] = {
 		}
 	},
 	{
+		.mfr_id		= (u16)AMD_MANUFACT,
+		.dev_id		= AM29LV800BT,
+		.name		= "AMD AM29LV800BT",
+		.uaddr		= {
+			[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+		},
+		.DevSize	= SIZE_1MiB,
+		.CmdSet		= CFI_CMDSET_AMD_LEGACY,
+		.NumEraseRegions= 4,
+		.regions	= {
+			ERASEINFO(0x10000, 15),
+			ERASEINFO(0x08000, 1),
+			ERASEINFO(0x02000, 2),
+			ERASEINFO(0x04000, 1),
+		}
+	},
+	{
+		.mfr_id		= (u16)MX_MANUFACT,
+		.dev_id		= AM29LV800BT,
+		.name		= "MXIC MX29LV800BT",
+		.uaddr		= {
+			[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+		},
+		.DevSize	= SIZE_1MiB,
+		.CmdSet		= CFI_CMDSET_AMD_LEGACY,
+		.NumEraseRegions= 4,
+		.regions	= {
+			ERASEINFO(0x10000, 15),
+			ERASEINFO(0x08000, 1),
+			ERASEINFO(0x02000, 2),
+			ERASEINFO(0x04000, 1),
+		}
+	},
+	{
+		.mfr_id		= (u16)EON_ALT_MANU,
+		.dev_id		= AM29LV800BT,
+		.name		= "EON EN29LV800BT",
+		.uaddr		= {
+			[1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+		},
+		.DevSize	= SIZE_1MiB,
+		.CmdSet		= CFI_CMDSET_AMD_LEGACY,
+		.NumEraseRegions= 4,
+		.regions	= {
+			ERASEINFO(0x10000, 15),
+			ERASEINFO(0x08000, 1),
+			ERASEINFO(0x02000, 2),
+			ERASEINFO(0x04000, 1),
+		}
+	},
+	{
 		.mfr_id		= (u16)STM_MANUFACT,
 		.dev_id		= STM29F400BB,
 		.name		= "ST Micro M29F400BB",

index 5454c9e..30aa080 100644
@@ -158,6 +158,7 @@ extern flash_info_t *flash_get_info(ulong base);
 #define EXCEL_MANUFACT	0x004A004A	/* Excel Semiconductor			*/
 #define AMIC_MANUFACT	0x00370037	/* AMIC    manuf. ID in D23..D16, D7..D0 */
 #define WINB_MANUFACT	0x00DA00DA	/* Winbond manuf. ID in D23..D16, D7..D0 */
+#define EON_ALT_MANU	0x001C001C	/* EON     manuf. ID in D23..D16, D7..D0 */
 
 /* Manufacturers inside bank 1 have ids like 0x01xx01xx */
 #define EON_MANUFACT	0x011C011C	/* EON     manuf. ID in D23..D16, D7..D0 */

index 1b25ed8..1f1d00f 100644
@@ -31,7 +31,8 @@ int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	unsigned int fpga;
 	ulong	addr, length;
 	int rc = 0;
-	u16	linebuf[DISP_LINE_LEN/sizeof(u16)];
+	u16 linebuf[DISP_LINE_LEN/sizeof(u16)];
+	ulong nbytes;
 
 	/*
 	 * We use the last specified parameters, unless new ones are

@@ -63,13 +64,28 @@ int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			length = simple_strtoul(argv[3], NULL, 16);
 	}
 
-	/* Print the lines. */
-	for (k = 0; k < DISP_LINE_LEN / sizeof(u16); ++k)
-		fpga_get_reg(fpga, (u16 *)fpga_ptr[fpga] + k, k * sizeof(u16),
-			     &linebuf[k]);
-	print_buffer(addr, (void *)linebuf, sizeof(u16),
-		     length, DISP_LINE_LEN / sizeof(u16));
-	addr += sizeof(u16)*length;
+	nbytes = length * sizeof(u16);
+	do {
+		ulong linebytes = (nbytes > DISP_LINE_LEN) ?
+				  DISP_LINE_LEN : nbytes;
+
+		for (k = 0; k < linebytes / sizeof(u16); ++k)
+			fpga_get_reg(fpga,
+				     (u16 *)fpga_ptr[fpga] + addr
+				     / sizeof(u16) + k,
+				     addr + k * sizeof(u16),
+				     &linebuf[k]);
+		print_buffer(addr, (void *)linebuf, sizeof(u16),
+			     linebytes / sizeof(u16),
+			     DISP_LINE_LEN / sizeof(u16));
+
+		nbytes -= linebytes;
+		addr += linebytes;
+		if (ctrlc()) {
+			rc = 1;
+			break;
+		}
+	} while (nbytes > 0);
 
 	dp_last_fpga = fpga;
 	dp_last_addr = addr;

index 1c765e4..55ecdf1 100644
@@ -289,7 +289,6 @@ int osd_probe(unsigned screen)
 {
 	u16 version;
 	u16 features;
-	u8 value;
 	int old_bus = i2c_get_bus_num();
 	bool pixclock_present = false;
 	bool output_driver_present = false;

@@ -330,7 +329,8 @@ int osd_probe(unsigned screen)
 #ifdef CONFIG_SYS_CH7301_I2C
 	i2c_set_bus_num(ch7301_i2c[screen]);
 	if (!i2c_probe(CH7301_I2C_ADDR)) {
-		value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+		u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+
 		if (value == 0x17) {
 			i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
 			i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);

@@ -345,8 +345,7 @@ int osd_probe(unsigned screen)
 #ifdef CONFIG_SYS_SIL1178_I2C
 	i2c_set_bus_num(sil1178_i2c[screen]);
 	if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
-		value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
-		if (value == 0x06) {
+		if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
 			/*
 			 * magic initialization sequence,
 			 * adapted from datasheet

index 1bac970..fffed73 100644
@@ -180,11 +180,11 @@ static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
 	unsigned feature_carriers;
 	unsigned feature_video_channels;
 
-	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+	int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
 
-	FPGA_GET_REG(0, versions, &versions);
-	FPGA_GET_REG(0, fpga_version, &fpga_version);
-	FPGA_GET_REG(0, fpga_features, &fpga_features);
+	FPGA_GET_REG(fpga, versions, &versions);
+	FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+	FPGA_GET_REG(fpga, fpga_features, &fpga_features);
 
 	unit_type = (versions & 0xf000) >> 12;
 	feature_compression = (fpga_features & 0xe000) >> 13;

index fffed73..1d7e141 100644
@@ -369,10 +369,11 @@ int last_stage_init(void)
 	unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
 	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 	u16 fpga_features;
-	int feature_carrier_speed = fpga_features & (1<<4);
+	int feature_carrier_speed;
 	bool ch0_rgmii2_present = false;
 
 	FPGA_GET_REG(0, fpga_features, &fpga_features);
+	feature_carrier_speed = fpga_features & (1<<4);
 
 	if (!legacy) {
 		/* Turn on Parade DP501 */

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new file mode 100644
index 0000000..64b4049
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach at gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IHS_MDIO_H_
+#define _IHS_MDIO_H_
+
+struct ihs_mdio_info {
+	u32 fpga;
+	char *name;
+};
+
+int ihs_mdio_init(struct ihs_mdio_info *info);
+
+#endif

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new file mode 100644
index 0000000..afbdc65
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach at gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PHY_H_
+#define _PHY_H_
+
+int setup_88e1514(const char *bus, unsigned char addr);
+int setup_88e1518(const char *bus, unsigned char addr);
+
+#endif

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new file mode 100644
index 0000000..dc07d56
@@ -0,0 +1,10 @@
+#ifndef __MPC8308_H_
+#define __MPC8308_H_
+
+/* functions to be provided by board implementation */
+void mpc8308_init(void);
+void mpc8308_set_fpga_reset(unsigned state);
+void mpc8308_setup_hw(void);
+int mpc8308_get_fpga_done(unsigned fpga);
+
+#endif /* __MPC8308_H_ */

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