ARM: at91/dt: define RTT nodes

PATCH New Boris Brezillon 2 participants 6 messages Nov 14, 2014 – Nov 19, 2014

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Device tree bindings Arm/Microchip (AT91) SoC support

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Boris Brezillon

author

2014-11-14 10:08 UTC #0 lore raw

cover ARM: at91/dt: define RTT nodes

Hello,

This patch series define RTT and GPBR devices on all at91 SoCs embedding those blocks and enable them on the at91sam9g20ek and at91sam9m10g45ek boards (which are the boards I tested on).

Best Regards,

Boris

Boris Brezillon (4):
ARM: at91/dt: add RTT nodes to at91 dtsis
ARM: at91/dt: add GPBR nodes
ARM: at91/dt: enable the RTT block on the sam9g20ek board
ARM: at91/dt: enable the RTT block on the at91sam9m10g45ek board

 arch/arm/boot/dts/at91sam9260.dtsi          | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9261.dtsi          | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi          | 21 +++++++++++++++++++++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi          | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |  9 +++++++++
 arch/arm/boot/dts/at91sam9rl.dtsi           | 14 ++++++++++++++
 7 files changed, 100 insertions(+)

Signature · 1 line

1.9.1

Boris Brezillon

author

2014-11-14 10:08 UTC #1 lore raw

PATCH 1/4 ARM: at91/dt: add RTT nodes to at91 dtsis

at91sam926x, at91sam9g45 and at91sam9rl SoCs all have at least one RTT block.

Signed-off-by Boris Brezillon <[email protected]>

---
 arch/arm/boot/dts/at91sam9260.dtsi |  8 ++++++++
 arch/arm/boot/dts/at91sam9261.dtsi |  8 ++++++++
 arch/arm/boot/dts/at91sam9263.dtsi | 15 +++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi |  8 ++++++++
 arch/arm/boot/dts/at91sam9rl.dtsi  |  8 ++++++++
 5 files changed, 47 insertions(+)

arch/arm/boot/dts/at91sam9260.dtsi +8 -0

index cb100b0..9ea824e 100644
@@ -956,6 +956,14 @@
 				};
 			};
 
+			rtc at fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				status = "disabled";
+			};
+
 			watchdog at fffffd40 {
 				compatible = "atmel,at91sam9260-wdt";
 				reg = <0xfffffd40 0x10>;

arch/arm/boot/dts/at91sam9261.dtsi +8 -0

index a81aab4..06b11fc 100644
@@ -828,6 +828,14 @@
 				clocks = <&mck>;
 			};
 
+			rtc at fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
+				status = "disabled";
+			};
+
 			watchdog at fffffd40 {
 				compatible = "atmel,at91sam9260-wdt";
 				reg = <0xfffffd40 0x10>;

arch/arm/boot/dts/at91sam9263.dtsi +15 -0

index 653e439..7f37b7e 100644
@@ -922,6 +922,21 @@
 				pinctrl-0 = <&pinctrl_can_rx_tx>;
 				clocks = <&can_clk>;
 				clock-names = "can_clk";
+			};
+
+			rtc at fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
+				status = "disabled";
+			};
+
+			rtc at fffffd50 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd50 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
 				status = "disabled";
 			};
 		};

arch/arm/boot/dts/at91sam9g45.dtsi +8 -0

index d3f6513..3771088 100644
@@ -1192,6 +1192,14 @@
 				};
 			};
 
+			rtc at fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				status = "disabled";
+			};
+
 			rtc at fffffdb0 {
 				compatible = "atmel,at91rm9200-rtc";
 				reg = <0xfffffdb0 0x30>;

arch/arm/boot/dts/at91sam9rl.dtsi +8 -0

index f0b4352..6d77b02 100644
@@ -1059,6 +1059,14 @@
 					clocks = <&slow_rc_osc &slow_osc>;
 				};
 			};
+
+			rtc at fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				status = "disabled";
+			};
 		};
 	};

Signature · 1 line

1.9.1

Boris Brezillon

author

2014-11-14 10:08 UTC #2 lore raw

PATCH 2/4 ARM: at91/dt: add GPBR nodes

In reply to Boris Brezillon

Add GPBR (General Purpose Block Backup Registers) nodes.

Signed-off-by Boris Brezillon <[email protected]>

---
 arch/arm/boot/dts/at91sam9260.dtsi | 6 ++++++
 arch/arm/boot/dts/at91sam9261.dtsi | 6 ++++++
 arch/arm/boot/dts/at91sam9263.dtsi | 6 ++++++
 arch/arm/boot/dts/at91sam9g45.dtsi | 6 ++++++
 arch/arm/boot/dts/at91sam9rl.dtsi  | 6 ++++++
 5 files changed, 30 insertions(+)

arch/arm/boot/dts/at91sam9260.dtsi +6 -0

index 9ea824e..dd1313c 100644
@@ -974,6 +974,12 @@
 				atmel,idle-halt;
 				status = "disabled";
 			};
+
+			gpbr: syscon at fffffd50 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd50 0x10>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {

arch/arm/boot/dts/at91sam9261.dtsi +6 -0

index 06b11fc..cdb9ed6 100644
@@ -842,6 +842,12 @@
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				status = "disabled";
 			};
+
+			gpbr: syscon at fffffd50 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd50 0x10>;
+				status = "disabled";
+			};
 		};
 	};

arch/arm/boot/dts/at91sam9263.dtsi +6 -0

index 7f37b7e..1467750 100644
@@ -939,6 +939,12 @@
 				clocks = <&slow_xtal>;
 				status = "disabled";
 			};
+
+			gpbr: syscon at fffffd60 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd60 0x50>;
+				status = "disabled";
+			};
 		};
 
 		fb0: fb at 0x00700000 {

arch/arm/boot/dts/at91sam9g45.dtsi +6 -0

index 3771088..18453d9 100644
@@ -1206,6 +1206,12 @@
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				status = "disabled";
 			};
+
+			gpbr: syscon at fffffd60 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd60 0x10>;
+				status = "disabled";
+			};
 		};
 
 		fb0: fb at 0x00500000 {

arch/arm/boot/dts/at91sam9rl.dtsi +6 -0

index 6d77b02..2ff072b 100644
@@ -1067,6 +1067,12 @@
 				clocks = <&clk32k>;
 				status = "disabled";
 			};
+
+			gpbr: syscon at fffffd60 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd60 0x10>;
+				status = "disabled";
+			};
 		};
 	};

Signature · 1 line

1.9.1

Boris Brezillon

author

2014-11-14 10:08 UTC #3 lore raw

PATCH 3/4 ARM: at91/dt: enable the RTT block on the sam9g20ek board

In reply to Boris Brezillon

Enable the RTT and GPBR devices and specify the general purpose register used to store the current time.

Enable wakeup on RTT event on the shutdown controller device.

Signed-off-by Boris Brezillon <[email protected]>

---
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

arch/arm/boot/dts/at91sam9g20ek_common.dtsi +14 -0

index d291910..dfaacb1 100644
@@ -112,9 +112,23 @@
 				};
 			};
 
+			shdwc at fffffd10 {
+				atmel,wakeup-counter = <10>;
+				atmel,wakeup-rtt-timer;
+			};
+
+			rtc at fffffd20 {
+				atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+				status = "okay";
+			};
+
 			watchdog at fffffd40 {
 				status = "okay";
 			};
+
+			gpbr: syscon at fffffd50 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {

Signature · 1 line

1.9.1

Boris Brezillon

author

2014-11-14 10:08 UTC #4 lore raw

PATCH 4/4 ARM: at91/dt: enable the RTT block on the at91sam9m10g45ek board

In reply to Boris Brezillon

Enable the RTT and GPBR devices and specify the general purpose register used to store the current time.

Signed-off-by Boris Brezillon <[email protected]>

---
 arch/arm/boot/dts/at91sam9m10g45ek.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

arch/arm/boot/dts/at91sam9m10g45ek.dts +9 -0

index d8dd226..33ce7ca 100644
@@ -161,6 +161,15 @@
 				pinctrl-0 = <&pinctrl_pwm_leds>;
 			};
 
+			rtc at fffffd20 {
+				atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+				status = "okay";
+			};
+
+			gpbr: syscon at fffffd60 {
+				status = "okay";
+			};
+
 			rtc at fffffdb0 {
 				status = "okay";
 			};

Signature · 1 line

1.9.1

Nicolas Ferre

2014-11-19 13:26 UTC #5 lore raw

cover ARM: at91/dt: define RTT nodes

In reply to Boris Brezillon

On 14/11/2014 11:08, Boris Brezillon :

Quoted 8 lines

Hello,
This patch series define RTT and GPBR devices on all at91 SoCs embedding those blocks and enable them on the at91sam9g20ek and at91sam9m10g45ek boards (which are the boards I tested on).
Best Regards,

Quoted 7 lines

Boris
Boris Brezillon (4):
ARM: at91/dt: add RTT nodes to at91 dtsis
ARM: at91/dt: add GPBR nodes
ARM: at91/dt: enable the RTT block on the sam9g20ek board
ARM: at91/dt: enable the RTT block on the at91sam9m10g45ek board

On the whole series:

Acked-by Nicolas Ferre <[email protected]>

and stacked up on top of at91-3.19-dt2

Bye,

Quoted 9 lines

 arch/arm/boot/dts/at91sam9260.dtsi          | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9261.dtsi          | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi          | 21 +++++++++++++++++++++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi          | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |  9 +++++++++
 arch/arm/boot/dts/at91sam9rl.dtsi           | 14 ++++++++++++++
 7 files changed, 100 insertions(+)

Signature · 1 line

Nicolas Ferre