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mmc: fsl_esdhc: Update esdhc driver for iMX6SX

PATCH New Ye.Li 2 participants 2 messages Nov 4, 2014 – Nov 20, 2014 MMC, SD and SDIO

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Ye.Li

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#0 lore raw

PATCH v3 1/2 mmc: fsl_esdhc: Update esdhc driver for iMX6SX

The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected.

Signed-off-by Ye.Li <[email protected]>

---
Changes since v2:
- None

Changes since v1:
- Remove codes which set INT_STATUS_EN register according PIO or DMA mode.

 drivers/mmc/fsl_esdhc.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
drivers/mmc/fsl_esdhc.c +8 -0
index 2640607..59b470d 100644
@@ -23,6 +23,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define SDHCI_IRQ_EN_BITS		(IRQSTATEN_CC | IRQSTATEN_TC | \
+				IRQSTATEN_CINT | \
+				IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
+				IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
+				IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
+				IRQSTATEN_DINT)
+
 struct fsl_esdhc {
 	uint    dsaddr;		/* SDMA system address register */
 	uint    blkattr;	/* Block attributes register */

@@ -558,6 +565,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 				| SYSCTL_IPGEN | SYSCTL_CKEN);
 
+	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 
 	voltage_caps = 0;
Signature · 1 line
1.7.4.1
#1 lore raw

PATCH v3 1/2 mmc: fsl_esdhc: Update esdhc driver for iMX6SX

Quoted 6 lines · Ye.Li

The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected.

Signed-off-by Ye.Li <[email protected]>

---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
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