cpufreq: use generic cpufreq drivers for exynos platforms
Subsystems (7)
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v11:
- Rebased on top of git://linuxtv.org/snawrocki/samsung.git for-v3.19-exynos-clk
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver.
This series is based on the following branch.git://linuxtv.org/snawrocki/samsung.git for-v3.19-exynos-clk
This series depends on the following patch which can be picked fromgit://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git samsung/dt e540920cf21c (ARM: dts: add CPU nodes for Exynos4 SoCs).
This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19
(http://www.spinics.net/lists/linux-samsung-soc/msg37933.html).
Sylwester, could you consider to merge this in your tree?
Thomas Abraham (6):
clk: samsung: add infrastructure to register cpu clocks
clk: samsung: add cpu clock configuration data and instantiate cpu clock
ARM: dts: Exynos: add CPU OPP and regulator supply property
ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
clk: samsung: remove unused clock aliases and update clock flags
arch/arm/boot/dts/exynos4210-origen.dts | 4 + arch/arm/boot/dts/exynos4210-trats.dts | 4 + arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 + arch/arm/boot/dts/exynos4210.dtsi | 14 ++- arch/arm/boot/dts/exynos5250-arndale.dts | 4 + arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 + arch/arm/boot/dts/exynos5250-snow.dts | 4 + arch/arm/boot/dts/exynos5250.dtsi | 25 +++- arch/arm/boot/dts/exynos5420.dtsi | 38 ++++ arch/arm/mach-exynos/exynos.c | 26 +++- drivers/clk/samsung/Makefile | 2 +- drivers/clk/samsung/clk-exynos4.c | 63 +++++--- drivers/clk/samsung/clk-exynos5250.c | 44 ++++- drivers/clk/samsung/clk-exynos5420.c | 72 +++++++- drivers/cpufreq/Kconfig.arm | 22 --- drivers/cpufreq/Makefile | 2 - drivers/cpufreq/exynos4210-cpufreq.c | 184 -------------------- drivers/cpufreq/exynos5250-cpufreq.c | 210 ----------------------- include/dt-bindings/clock/exynos5250.h | 1 + include/dt-bindings/clock/exynos5420.h | 2 + 20 files changed, 266 insertions(+), 463 deletions(-) delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
PATCH v12 1/6 clk: samsung: add infrastructure to register cpu clocks
The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms.
--- drivers/clk/samsung/Makefile | 2 +- drivers/clk/samsung/clk-cpu.c | 335 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-cpu.h | 91 +++++++++++ 3 files changed, 427 insertions(+), 1 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c create mode 100644 drivers/clk/samsung/clk-cpu.h
drivers/clk/samsung/Makefile +1 -1
@@ -2,7 +2,7 @@ # Samsung Clock specific Makefile # -obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o +obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
drivers/clk/samsung/clk-cpu.c new file +335 -0
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drivers/clk/samsung/clk-cpu.h new file +91 -0
91 lines not on this page · raw message
Signature · 1 line
1.6.6.rc2
PATCH v12 2/6 clk: samsung: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210, Exynos5250 and Exynos5420.
--- drivers/clk/samsung/clk-exynos4.c | 15 ++++++++++ drivers/clk/samsung/clk-exynos5250.c | 25 +++++++++++++++++ drivers/clk/samsung/clk-exynos5420.c | 45 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5250.h | 1 + include/dt-bindings/clock/exynos5420.h | 2 + 5 files changed, 88 insertions(+), 0 deletions(-)
drivers/clk/samsung/clk-exynos4.c +15 -0
@@ -19,6 +19,7 @@#include <linux/syscore_ops.h> #include "clk.h" +#include "clk-cpu.h" /* Exynos4 clock controller register offsets */ #define SRC_LEFTBUS 0x4200
@@ -1354,6 +1355,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { VPLL_LOCK, VPLL_CON0, NULL), }; +static const struct exynos_cpuclk_cfg_data e4210_armclk_d[]__initconst = { + {1200000 ,E4210_CPU_DIV0 (7 ,1 ,4 ,3 ,7 ,3 ),E4210_CPU_DIV1 (0 ,5 ), }, + {1000000 ,E4210_CPU_DIV0 (7 ,1 ,4 ,3 ,7 ,3 ),E4210_CPU_DIV1 (0 ,4 ), }, + {800000 ,E4210_CPU_DIV0 (7 ,1 ,3 ,3 ,7 ,3 ),E4210_CPU_DIV1 (0 ,3 ), }, + {500000 ,E4210_CPU_DIV0 (7 ,1 ,3 ,3 ,7 ,3 ),E4210_CPU_DIV1 (0 ,3 ), }, + {400000 ,E4210_CPU_DIV0 (7 ,1 ,3 ,3 ,7 ,3 ),E4210_CPU_DIV1 (0 ,3 ), }, + {200000 ,E4210_CPU_DIV0 (0 ,1 ,1 ,1 ,3 ,1 ),E4210_CPU_DIV1 (0 ,3 ), }, + {0 }, +}; +static void __init exynos4_core_down_clock (enum exynos4_soc soc) {unsigned int tmp;
@@ -1457,6 +1468,10 @@ static void __init exynos4_clk_init(struct device_node *np,samsung_clk_register_fixed_factor (ctx, exynos4210_fixed_factor_clks,ARRAY_SIZE (exynos4210_fixed_factor_clks)); +exynos_register_cpu_clock (ctx,CLK_ARM_CLK ,"armclk" , + mout_core_p4210[0 ], mout_core_p4210[1 ],0x14200 , + e4210_armclk_d,ARRAY_SIZE (e4210_armclk_d), +CLK_CPU_NEEDS_DEBUG_ALT_DIV |CLK_CPU_HAS_DIV1 ); }else {samsung_clk_register_mux (ctx, exynos4x12_mux_clks,ARRAY_SIZE (exynos4x12_mux_clks));
drivers/clk/samsung/clk-exynos5250.c +25 -0
@@ -19,6 +19,7 @@#include <linux/syscore_ops.h> #include "clk.h" +#include "clk-cpu.h" #define APLL_LOCK 0x0#define APLL_CON0 0x100
@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { VPLL_LOCK, VPLL_CON0, NULL), }; +static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[]__initconst = { + {1700000 ,E5250_CPU_DIV0 (5 ,3 ,7 ,7 ,7 ,3 ),E5250_CPU_DIV1 (2 ,0 ), }, + {1600000 ,E5250_CPU_DIV0 (4 ,1 ,7 ,7 ,7 ,3 ),E5250_CPU_DIV1 (2 ,0 ), }, + {1500000 ,E5250_CPU_DIV0 (4 ,1 ,7 ,7 ,7 ,2 ),E5250_CPU_DIV1 (2 ,0 ), }, + {1400000 ,E5250_CPU_DIV0 (4 ,1 ,6 ,7 ,7 ,2 ),E5250_CPU_DIV1 (2 ,0 ), }, + {1300000 ,E5250_CPU_DIV0 (3 ,1 ,6 ,7 ,7 ,2 ),E5250_CPU_DIV1 (2 ,0 ), }, + {1200000 ,E5250_CPU_DIV0 (3 ,1 ,5 ,7 ,7 ,2 ),E5250_CPU_DIV1 (2 ,0 ), }, + {1100000 ,E5250_CPU_DIV0 (3 ,1 ,5 ,7 ,7 ,3 ),E5250_CPU_DIV1 (2 ,0 ), }, + {1000000 ,E5250_CPU_DIV0 (2 ,1 ,4 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {900000 ,E5250_CPU_DIV0 (2 ,1 ,4 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {800000 ,E5250_CPU_DIV0 (2 ,1 ,4 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {700000 ,E5250_CPU_DIV0 (1 ,1 ,3 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {600000 ,E5250_CPU_DIV0 (1 ,1 ,3 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {500000 ,E5250_CPU_DIV0 (1 ,1 ,2 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {400000 ,E5250_CPU_DIV0 (1 ,1 ,2 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {300000 ,E5250_CPU_DIV0 (1 ,1 ,1 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {200000 ,E5250_CPU_DIV0 (1 ,1 ,1 ,7 ,7 ,1 ),E5250_CPU_DIV1 (2 ,0 ), }, + {0 }, +}; +static const struct of_device_id ext_clk_match[]__initconst = { { .compatible ="samsung,clock-xxti" , .data = (void *)0 , }, { },
@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_div_clks));samsung_clk_register_gate (ctx, exynos5250_gate_clks,ARRAY_SIZE (exynos5250_gate_clks)); +exynos_register_cpu_clock (ctx,CLK_ARM_CLK ,"armclk" , + mout_cpu_p[0 ], mout_cpu_p[1 ],0x200 , + exynos5250_armclk_d,ARRAY_SIZE (exynos5250_armclk_d), +CLK_CPU_HAS_DIV1 );/* * Enable arm clock down (in idle) and set arm divider
drivers/clk/samsung/clk-exynos5420.c +45 -0
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include/dt-bindings/clock/exynos5250.h +1 -0
@@ -21,6 +21,7 @@#define CLK_FOUT_CPLL 6#define CLK_FOUT_EPLL 7#define CLK_FOUT_VPLL 8 +#define CLK_ARM_CLK 9/* gate for special clocks (sclk) */ #define CLK_SCLK_CAM_BAYER 128
include/dt-bindings/clock/exynos5420.h +2 -0
@@ -25,6 +25,8 @@#define CLK_FOUT_MPLL 10#define CLK_FOUT_BPLL 11#define CLK_FOUT_KPLL 12 +#define CLK_ARM_CLK 13 +#define CLK_KFC_CLK 14/* gate for special clocks (sclk) */ #define CLK_SCLK_UART0 128
Signature · 1 line
1.6.6.rc2
PATCH v12 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers.
--- arch/arm/boot/dts/exynos4210-origen.dts | 4 ++ arch/arm/boot/dts/exynos4210-trats.dts | 4 ++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 ++ arch/arm/boot/dts/exynos4210.dtsi | 14 ++++++++- arch/arm/boot/dts/exynos5250-arndale.dts | 4 ++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 ++ arch/arm/boot/dts/exynos5250-snow.dts | 4 ++ arch/arm/boot/dts/exynos5250.dtsi | 25 ++++++++++++++- arch/arm/boot/dts/exynos5420.dtsi | 38 +++++++++++++++++++++++ 9 files changed, 99 insertions(+), 2 deletions(-)
arch/arm/boot/dts/exynos4210-origen.dts +4 -0
@@ -334,3 +334,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck1_reg>; +};
arch/arm/boot/dts/exynos4210-trats.dts +4 -0
@@ -446,3 +446,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&varm_breg>; +};
arch/arm/boot/dts/exynos4210-universal_c210.dts +4 -0
@@ -492,3 +492,7 @@ &mdma1 { reg = <0x12840000 0x1000>; }; + +&cpu0 { + cpu0-supply = <&vdd_arm_reg>; +};
arch/arm/boot/dts/exynos4210.dtsi +13 -1
@@ -35,10 +35,22 @@ #address-cells = <1>; #size-cells = <0>; - cpu@900 { + cpu0: cpu@900 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x900>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <160000>; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; }; cpu@901 {
arch/arm/boot/dts/exynos5250-arndale.dts +4 -0
@@ -563,3 +563,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +};
arch/arm/boot/dts/exynos5250-smdk5250.dts +4 -0
@@ -406,3 +406,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +};
arch/arm/boot/dts/exynos5250-snow.dts +4 -0
@@ -345,6 +345,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &i2c_0 { status = "okay"; samsung,i2c-sda-delay = <100>;
arch/arm/boot/dts/exynos5250.dtsi +24 -1
@@ -58,11 +58,34 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <140000>; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; }; cpu@1 { device_type = "cpu";
arch/arm/boot/dts/exynos5420.dtsi +38 -0
@@ -59,8 +59,26 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu-cluster.0"; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; + + operating-points = < + 1800000 1250000 + 1700000 1212500 + 1600000 1175000 + 1500000 1137500 + 1400000 1112500 + 1300000 1062500 + 1200000 1037500 + 1100000 1012500 + 1000000 987500 + 900000 962500 + 800000 937500 + 700000 912500 + >; }; cpu1: cpu@1 {
@@ -69,6 +87,7 @@ reg = <0x1>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; }; cpu2: cpu@2 {
@@ -77,6 +96,7 @@ reg = <0x2>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; }; cpu3: cpu@3 {
@@ -85,14 +105,29 @@ reg = <0x3>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; + clock-names = "cpu-cluster.1"; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; + + operating-points = < + 1300000 1275000 + 1200000 1212500 + 1100000 1162500 + 1000000 1112500 + 900000 1062500 + 800000 1025000 + 700000 975000 + 600000 937500 + >; }; cpu5: cpu@101 {
@@ -101,6 +136,7 @@ reg = <0x101>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; }; cpu6: cpu@102 {
@@ -109,6 +145,7 @@ reg = <0x102>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; }; cpu7: cpu@103 {
@@ -117,6 +154,7 @@ reg = <0x103>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; }; };
Signature · 1 line
1.6.6.rc2
PATCH v12 4/6 ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver.
--- arch/arm/mach-exynos/exynos.c | 26 +++++++++++++++++++++++++- 1 files changed, 25 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/exynos.c +25 -1
@@ -282,6 +282,30 @@ static void __init exynos_init_irq(void)exynos_map_pmu (); } +static const struct of_device_id exynos_cpufreq_matches[] = { + { .compatible ="samsung,exynos5420" , .data ="arm-bL-cpufreq-dt" }, + { .compatible ="samsung,exynos5422" , .data ="arm-bL-cpufreq-dt" }, + { .compatible ="samsung,exynos5800" , .data ="arm-bL-cpufreq-dt" }, + { .compatible ="samsung,exynos5250" , .data ="cpufreq-dt" }, + { .compatible ="samsung,exynos4210" , .data ="cpufreq-dt" }, + { .compatible ="samsung,exynos5440" , .data ="exynos5440-cpufreq" }, + {/* sentinel */ } +}; + +static void __init exynos_cpufreq_init (void ) +{ +struct device_node *root =of_find_node_by_path ("/" ); +const struct of_device_id *match; + + match =of_match_node (exynos_cpufreq_matches, root); +if (!match) { +platform_device_register_simple ("exynos-cpufreq" ,-1 ,NULL ,0 ); +return ; + } + +platform_device_register_simple (match->data,-1 ,NULL ,0 ); +} +static void __init exynos_dt_machine_init (void ) {struct device_node *i2c_np;
@@ -321,7 +345,7 @@ static void __init exynos_dt_machine_init(void) of_machine_is_compatible("samsung,exynos5250"))platform_device_register (&exynos_cpuidle); -platform_device_register_simple ("exynos-cpufreq" ,-1 ,NULL ,0 ); +exynos_cpufreq_init ();of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL ); }
Signature · 1 line
1.6.6.rc2
PATCH v12 5/6 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed.
--- drivers/cpufreq/Kconfig.arm | 22 ---- drivers/cpufreq/Makefile | 2 - drivers/cpufreq/exynos4210-cpufreq.c | 184 ----------------------------- drivers/cpufreq/exynos5250-cpufreq.c | 210 ---------------------------------- 4 files changed, 0 insertions(+), 418 deletions(-) delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
drivers/cpufreq/Kconfig.arm +0 -22
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ config ARM_EXYNOS_CPUFREQ bool -config ARM_EXYNOS4210_CPUFREQ - bool "SAMSUNG EXYNOS4210" - depends on CPU_EXYNOS4210 - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS4210 - SoC (S5PV310 or S5PC210). - - If in doubt, say N. - config ARM_EXYNOS4X12_CPUFREQ bool "SAMSUNG EXYNOS4x12" depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ If in doubt, say N. -config ARM_EXYNOS5250_CPUFREQ - bool "SAMSUNG EXYNOS5250" - depends on SOC_EXYNOS5250 - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS5250 - SoC. - - If in doubt, say N. - config ARM_EXYNOS5440_CPUFREQ bool "SAMSUNG EXYNOS5440" depends on SOC_EXYNOS5440
drivers/cpufreq/Makefile +0 -2
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
drivers/cpufreq/exynos4210-cpufreq.c deleted +0 -184
184 lines not on this page · raw message
drivers/cpufreq/exynos5250-cpufreq.c deleted +0 -210
210 lines not on this page · raw message
Signature · 1 line
1.6.6.rc2
PATCH v12 6/6 clk: samsung: remove unused clock aliases and update clock flags
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags.
--- drivers/clk/samsung/clk-exynos4.c | 48 +++++++++++++++++----------------- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++----- drivers/clk/samsung/clk-exynos5420.c | 27 ++++++++++++------ 3 files changed, 53 insertions(+), 41 deletions(-)
drivers/clk/samsung/clk-exynos4.c +24 -24
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {MUX (0 ,"mout_fimd1" , group1_p4210,E4210_SRC_LCD1 ,0 ,4 ),MUX (0 ,"mout_mipi1" , group1_p4210,E4210_SRC_LCD1 ,12 ,4 ),MUX (CLK_SCLK_MPLL ,"sclk_mpll" , mout_mpll_p,SRC_CPU ,8 ,1 ), -MUX (CLK_MOUT_CORE ,"mout_core" , mout_core_p4210,SRC_CPU ,16 ,1 ), +MUX_F (CLK_MOUT_CORE ,"mout_core" , mout_core_p4210,SRC_CPU ,16 ,1 ,0 , +CLK_MUX_READ_ONLY ),MUX (0 ,"mout_hpm" , mout_core_p4210,SRC_CPU ,20 ,1 ),MUX (CLK_SCLK_VPLL ,"sclk_vpll" , sclk_vpll_p4210,SRC_TOP0 ,8 ,1 ), MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {DIV (0 ,"div_clkout_rightbus" ,"mout_clkout_rightbus" ,CLKOUT_CMU_RIGHTBUS ,8 ,6 ), -DIV (0 ,"div_core" ,"mout_core" ,DIV_CPU0 ,0 ,3 ), -DIV (0 ,"div_corem0" ,"div_core2" ,DIV_CPU0 ,4 ,3 ), -DIV (0 ,"div_corem1" ,"div_core2" ,DIV_CPU0 ,8 ,3 ), -DIV (0 ,"div_periph" ,"div_core2" ,DIV_CPU0 ,12 ,3 ), -DIV (0 ,"div_atb" ,"mout_core" ,DIV_CPU0 ,16 ,3 ), -DIV (0 ,"div_pclk_dbg" ,"div_atb" ,DIV_CPU0 ,20 ,3 ), -DIV (CLK_ARM_CLK ,"div_core2" ,"div_core" ,DIV_CPU0 ,28 ,3 ), -DIV (0 ,"div_copy" ,"mout_hpm" ,DIV_CPU1 ,0 ,3 ), -DIV (0 ,"div_hpm" ,"div_copy" ,DIV_CPU1 ,4 ,3 ), +DIV_F (0 ,"div_core" ,"mout_core" ,DIV_CPU0 ,0 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_corem0" ,"div_core2" ,DIV_CPU0 ,4 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_corem1" ,"div_core2" ,DIV_CPU0 ,8 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_periph" ,"div_core2" ,DIV_CPU0 ,12 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_atb" ,"mout_core" ,DIV_CPU0 ,16 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_pclk_dbg" ,"div_atb" ,DIV_CPU0 ,20 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (CLK_ARM_CLK ,"div_core2" ,"div_core" ,DIV_CPU0 ,28 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_copy" ,"mout_hpm" ,DIV_CPU1 ,0 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_hpm" ,"div_copy" ,DIV_CPU1 ,4 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ),DIV (0 ,"div_clkout_cpu" ,"mout_clkout_cpu" ,CLKOUT_CMU_CPU ,8 ,6 ), DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
@@ -769,7 +779,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {DIV (0 ,"div_spi_pre2" ,"div_spi2" ,DIV_PERIL2 ,8 ,8 ),DIV (0 ,"div_audio1" ,"mout_audio1" ,DIV_PERIL4 ,0 ,4 ),DIV (0 ,"div_audio2" ,"mout_audio2" ,DIV_PERIL4 ,16 ,4 ), -DIV (CLK_SCLK_APLL ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), +DIV_F (CLK_SCLK_APLL ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ),DIV_F (0 ,"div_mipi_pre0" ,"div_mipi0" ,DIV_LCD0 ,20 ,4 ,CLK_SET_RATE_PARENT ,0 ), DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
@@ -1186,17 +1197,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 0), }; -static struct samsung_clock_alias exynos4_aliases[]__initdata = { +static struct samsung_clock_alias exynos4x12_aliases[]__initdata = {ALIAS (CLK_MOUT_CORE ,NULL ,"moutcore" ),ALIAS (CLK_ARM_CLK ,NULL ,"armclk" ),ALIAS (CLK_SCLK_APLL ,NULL ,"mout_apll" ), -}; - -static struct samsung_clock_alias exynos4210_aliases[]__initdata = { -ALIAS (CLK_SCLK_MPLL ,NULL ,"mout_mpll" ), -}; - -static struct samsung_clock_alias exynos4x12_aliases[]__initdata = {ALIAS (CLK_MOUT_MPLL_USER_C ,NULL ,"mout_mpll" ), };
@@ -1463,8 +1467,6 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4210_div_clks));samsung_clk_register_gate (ctx, exynos4210_gate_clks,ARRAY_SIZE (exynos4210_gate_clks)); -samsung_clk_register_alias (ctx, exynos4210_aliases, -ARRAY_SIZE (exynos4210_aliases));samsung_clk_register_fixed_factor (ctx, exynos4210_fixed_factor_clks,ARRAY_SIZE (exynos4210_fixed_factor_clks));
@@ -1486,9 +1488,6 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); } -samsung_clk_register_alias (ctx, exynos4_aliases, -ARRAY_SIZE (exynos4_aliases)); -exynos4_core_down_clock (soc);exynos4_clk_sleep_init ();
@@ -1499,6 +1498,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4_soc ==EXYNOS4210 ?"Exynos4210" :"Exynos4x12" ,_get_rate ("sclk_apll" ),_get_rate ("sclk_mpll" ),_get_rate ("sclk_epll" ),_get_rate ("sclk_vpll" ), + exynos4_soc ==EXYNOS4210 ?_get_rate ("armclk" ) : _get_rate("div_core2")); }
drivers/clk/samsung/clk-exynos5250.c +11 -8
@@ -291,14 +291,14 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {/* * CMU_CPU */ -MUX_FA (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 , -CLK_SET_RATE_PARENT ,0 ,"mout_apll" ), -MUX_A (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ,"mout_cpu" ), +MUX_F (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 , +CLK_SET_RATE_PARENT ,0 ), +MUX_F (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ,0 ,CLK_MUX_READ_ONLY ),/* * CMU_CORE */ - MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), + MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),/* * CMU_TOP
@@ -380,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {/* * CMU_CPU */ -DIV (0 ,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ), -DIV (0 ,"div_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), - DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), +DIV_F (0 ,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_arm2" ,"div_arm" ,DIV_CPU0 ,28 ,3 , + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),/* * CMU_TOP
@@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)samsung_clk_of_add_provider (np, ctx);pr_info ("Exynos5250: clock setup completed, armclk=%ld\n" , -_get_rate ("div_arm2" )); +_get_rate ("armclk" )); }CLK_OF_DECLARE (exynos5250_clk,"samsung,exynos5250-clock" , exynos5250_clk_init);
drivers/clk/samsung/clk-exynos5420.c +18 -9
@@ -617,10 +617,14 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {MUX (0 ,"mout_mspll_kfc" , mout_mspll_cpu_p,SRC_TOP7 ,8 ,2 ),MUX (0 ,"mout_mspll_cpu" , mout_mspll_cpu_p,SRC_TOP7 ,12 ,2 ), -MUX (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ), -MUX (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ), -MUX (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 ), -MUX (0 ,"mout_kfc" , mout_kfc_p,SRC_KFC ,16 ,1 ), +MUX_F (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 , +CLK_SET_RATE_PARENT ,0 ), +MUX_F (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ,0 , +CLK_MUX_READ_ONLY ), +MUX_F (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 , +CLK_SET_RATE_PARENT ,0 ), +MUX_F (0 ,"mout_kfc" , mout_kfc_p,SRC_KFC ,16 ,1 ,0 , +CLK_MUX_READ_ONLY ),MUX (0 ,"mout_aclk200" , mout_group1_p,SRC_TOP0 ,8 ,2 ), MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
@@ -776,11 +780,16 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { };static struct samsung_div_clock exynos5x_div_clks[]__initdata = { -DIV (0 ,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ), -DIV (0 ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), -DIV (0 ,"armclk2" ,"div_arm" ,DIV_CPU0 ,28 ,3 ), -DIV (0 ,"div_kfc" ,"mout_kfc" ,DIV_KFC0 ,0 ,3 ), -DIV (0 ,"sclk_kpll" ,"mout_kpll" ,DIV_KFC0 ,24 ,3 ), +DIV_F (0 ,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"armclk2" ,"div_arm" ,DIV_CPU0 ,28 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"div_kfc" ,"mout_kfc" ,DIV_KFC0 ,0 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ), +DIV_F (0 ,"sclk_kpll" ,"mout_kpll" ,DIV_KFC0 ,24 ,3 , +CLK_GET_RATE_NOCACHE ,CLK_DIVIDER_READ_ONLY ),DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ),DIV (0 ,"dout_aclk400_mscl" ,"mout_aclk400_mscl" ,DIV_TOP0 ,4 ,3 ),
Signature · 1 line
1.6.6.rc2
PATCH v12 3/6 ARM: dts: Exynos: add CPU OPP and regulator supply property
In reply to Thomas AbrahamJavier, Doug,
Am 21.11.2014 um 14:31 schrieb Thomas Abraham:
Quoted 29 lines
arch/arm/boot/dts/exynos5250-arndale.dts +4
-0@@ -563,3 +563,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +};arch/arm/boot/dts/exynos5250-smdk5250.dts +4
-0@@ -406,3 +406,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +};arch/arm/boot/dts/exynos5250-snow.dts +0
-0
arch/arm/boot/dts/exynos5250-snow.dts line 354
Quoted 10 lines
arch/arm/boot/dts/exynos5250-snow.dts +4
-0@@ -345,6 +345,10 @@ }; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + &i2c_0 { status = "okay"; samsung,i2c-sda-delay = <100>;
Not sure whether I've asked before... Do you know what needs to be specified for exynos5250-spring.dts, which has in the meantime landed in kgene/for-next?
Regards,
Andreas
Quoted 40 lines
arch/arm/boot/dts/exynos5250.dtsi +24
-1@@ -58,11 +58,34 @@ #address-cells = <1>; #size-cells = <0>; - cpu at 0 { + cpu0: cpu at 0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <140000>; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; }; cpu at 1 { device_type = "cpu";
[snip]
Signature · 2 lines
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 21284 AG N?rnberg
Sylwester Nawrocki
maintainerv12 cover cpufreq: use generic cpufreq drivers for exynos platforms
In reply to Thomas AbrahamHi All,
Quoted 11 lines · Thomas Abraham
Changes since v11:
- Rebased on top ofgit://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clkThis patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using
arm_big_littlecpufreq driver.This series is based on the following branch.
git://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clk
Quoted 8 lines
This series depends on the following patch which can be picked from
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.gitsamsung/dte540920cf21c(ARM: dts: add CPU nodes for Exynos4 SoCs).This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19
(http://www.spinics.net/lists/linux-samsung-soc/msg37933.html).
Sylwester, could you consider to merge this in your tree?
This patch series has already conflicts in arch/arm/boot/dts/ with the arm-soc tree. It touches quite many files at arch/arm. Perhaps we could still have it merged through Kukjin's and arm-soc tree ?
Feel free to add for the whole series:
Signature · 2 lines
Thanks, Sylwester
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
In reply to Thomas AbrahamHi Thomas,
Quoted 2 lines · Thomas Abraham
Changes since v11:
- Rebased on top ofgit://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clk
Thanks for rebasing/reposting.
Quoted 8 lines
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using
arm_big_littlecpufreq driver.This series is based on the following branch.
git://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clk
Quoted 8 lines
This series depends on the following patch which can be picked from
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.gitsamsung/dte540920cf21c(ARM: dts: add CPU nodes for Exynos4 SoCs).This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19
(http://www.spinics.net/lists/linux-samsung-soc/msg37933.html).
Sylwester, could you consider to merge this in your tree?
I tested this on exynos5800-peach-pi, and noticed a few things.
First, since voltage scaling is not currently supported, the CPU cluster regulators (vdd_arm, and vdd_kfc) have to be set at sufficietnly high voltage to support all the OPPs, otherwise things will likely hang. I think you should include something like the patch below[1] in this series as well.
Second, as with earlier versions of this series, I'm still seeing lots of "wait_until_divider_stable: timeout in divider stablization" messages coming out when running powertop.
Speaking of powertop, in the "frequency stats" tab, I'm not seeing 0% time spent in all the P-states, so not sure what's going on there. The stats/time_in_state sysfs files under cpufreq seem to show the right values, so I'm not sure what's going on with powertop there.
Kevin
[1]
(quoted diff) +0 -0
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index e8fdda827fc9..5160735aad3b 100644
arch/arm/boot/dts/exynos5800-peach-pi.dts +4 -4
@@ -195,8 +195,8 @@ buck2_reg: BUCK2 { regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; regulator-ramp-delay = <12500>;
@@ -230,8 +230,8 @@ buck6_reg: BUCK6 { regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1275000>; regulator-always-on; regulator-boot-on; regulator-ramp-delay = <12500>;
Quoted 36 lines
Thomas Abraham (6):
clk: samsung: add infrastructure to register cpu clocks
clk: samsung: add cpu clock configuration data and instantiate cpu clock
ARM: dts: Exynos: add CPU OPP and regulator supply property
ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
clk: samsung: remove unused clock aliases and update clock flagsarch/arm/boot/dts/exynos4210-origen.dts | 4 + arch/arm/boot/dts/exynos4210-trats.dts | 4 + arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 + arch/arm/boot/dts/exynos4210.dtsi | 14 ++- arch/arm/boot/dts/exynos5250-arndale.dts | 4 + arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 + arch/arm/boot/dts/exynos5250-snow.dts | 4 + arch/arm/boot/dts/exynos5250.dtsi | 25 +++- arch/arm/boot/dts/exynos5420.dtsi | 38 ++++ arch/arm/mach-exynos/exynos.c | 26 +++- drivers/clk/samsung/Makefile | 2 +- drivers/clk/samsung/clk-exynos4.c | 63 +++++--- drivers/clk/samsung/clk-exynos5250.c | 44 ++++- drivers/clk/samsung/clk-exynos5420.c | 72 +++++++- drivers/cpufreq/Kconfig.arm | 22 --- drivers/cpufreq/Makefile | 2 - drivers/cpufreq/exynos4210-cpufreq.c | 184 -------------------- drivers/cpufreq/exynos5250-cpufreq.c | 210 ----------------------- include/dt-bindings/clock/exynos5250.h | 1 + include/dt-bindings/clock/exynos5420.h | 2 + 20 files changed, 266 insertions(+), 463 deletions(-) delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c--
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v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
Hi Thomas,
On Mon, Nov 24, 2014 at 10:58 AM, Kevin Hilman <[email protected]> wrote:
[...]
Quoted 3 lines
Second, as with earlier versions of this series, I'm still seeing lots of "
wait_until_divider_stable: timeout in divider stablization" messages coming out when running powertop.
I found a simpler way to reproduce these messages. If I simply use the userspace governor and cycle through all the A7 OPPs, I'll hit this message (script below[1]). Note that I'm also using my DTS change that fixes the vdd_arm and vdd_kfc voltages to a voltage that is high enough for all the OPPs.
Kevin
[1]
#!/bin/sh
cpu=cpu4
reg_name=vdd_kfc
cpu_reg=$(dirname find /sys/class/regulator/regulator.*/ -name name -exec grep -l $reg_name {} \;)
echo $cpu_reg
# Cycle through frequencies (and check voltage) cd /sys/devices/system/cpu/$cpu/cpufreq echo userspace > scaling_governor
for freq in cat scaling_available_frequencies; do
echo ${freq} > scaling_setspeed
echo -n "current freq: "
cat scaling_cur_freq
echo -n "current voltage: "
cat ${cpu_reg}/microvolts
sleep 1
done
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
In reply to Kevin HilmanQuoted 34 lines · Kevin Hilman
Hi Thomas,
Quoted 2 lines · Thomas Abraham
Changes since v11:
- Rebased on top ofgit://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clkThanks for rebasing/reposting.
Quoted 8 lines
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using
arm_big_littlecpufreq driver.This series is based on the following branch.
git://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clkQuoted 8 lines
This series depends on the following patch which can be picked from
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.gitsamsung/dte540920cf21c(ARM: dts: add CPU nodes for Exynos4 SoCs).This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19
(http://www.spinics.net/lists/linux-samsung-soc/msg37933.html).
Sylwester, could you consider to merge this in your tree?I tested this on exynos5800-peach-pi, and noticed a few things.
First, since voltage scaling is not currently supported, the CPU cluster regulators (
vdd_arm, andvdd_kfc) have to be set at sufficietnly high voltage to support all the OPPs, otherwise things will likely hang. I think you should include something like the patch below[1] in this series as well.
Quoted 3 lines
Second, as with earlier versions of this series, I'm still seeing lots of "
wait_until_divider_stable: timeout in divider stablization" messages coming out when running powertop.
And, I just found another issue:
On exynos5800-peach-pi, setting the cpufreq default governor to performance at compile time (CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y) makes the kernel boot hang when the cpufreq driver is initialized.
However, setting the compile-time default to the userspace governor, and then setting the performance governor via sysfs after the boot finishes seems to work fine.
Kevin
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
In reply to Thomas AbrahamQuoted 11 lines · Thomas Abraham
Changes since v11:
- Rebased on top ofgit://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clkThis patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using
arm_big_littlecpufreq driver.This series is based on the following branch.
git://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clk
Quoted 8 lines
This series depends on the following patch which can be picked from
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.gitsamsung/dte540920cf21c(ARM: dts: add CPU nodes for Exynos4 SoCs).This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19
(http://www.spinics.net/lists/linux-samsung-soc/msg37933.html).
Sylwester, could you consider to merge this in your tree?
CPUfreq for exynos is still not upstream. What's the status of this series? It's been ver a month since there's been any activity here (or any responses to the issues I reported.)
On a related note, this series only does frequency scaling. Is there any work going on to also enable voltage scaling for the CPU rails as well?
Thanks,
Kevin
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
2015-01-08 22:17 GMT+01:00 Kevin Hilman <[email protected]>:
Quoted 21 lines · Thomas Abraham
Quoted 11 lines
Changes since v11:
- Rebased on top ofgit://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clkThis patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using
arm_big_littlecpufreq driver.This series is based on the following branch.
git://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clkQuoted 8 lines
This series depends on the following patch which can be picked from
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.gitsamsung/dte540920cf21c(ARM: dts: add CPU nodes for Exynos4 SoCs).This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19
(http://www.spinics.net/lists/linux-samsung-soc/msg37933.html).
Sylwester, could you consider to merge this in your tree?
Quoted 7 lines
CPUfreq for exynos is still not upstream. What's the status of this series? It's been ver a month since there's been any activity here (or any responses to the issues I reported.)
On a related note, this series only does frequency scaling. Is there any work going on to also enable voltage scaling for the CPU rails as well?
Hi Thomas,
Do you plan to continue with this work? It would be very helpful.
I also wonder if Exynos 4412 could be re-added (without the boost if these bindings are not ready)?
Best regards,
Krzysztof
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
Hi Krzysztof, Thomas,
Quoted 29 lines
2015-01-08 22:17 GMT+01:00 Kevin Hilman <[email protected]>:
Quoted 28 lines
Quoted 16 lines · Thomas Abraham
Changes since v11:
- Rebased on top ofgit://linuxtv.org/snawrocki/samsung.git
for-v3.19-exynos-clkThis patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using
arm_big_littlecpufreq driver.This series is based on the following branch.
git://linuxtv.org/snawrocki/samsung.gitfor-v3.19-exynos-clkThis series depends on the following patch which can be picked from
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
samsung/dte540920cf21c(ARM: dts: add CPU nodes for Exynos4 SoCs).Quoted 5 lines
This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19
(http://www.spinics.net/lists/linux-samsung-soc/msg37933.html).
Sylwester, could you consider to merge this in your tree?CPUfreq for exynos is still not upstream. What's the status of this series? It's been ver a month since there's been any activity here (or any responses to the issues I reported.)
Quoted 7 lines
Quoted 3 lines
On a related note, this series only does frequency scaling. Is there any work going on to also enable voltage scaling for the CPU rails as well?
Hi Thomas,
Do you plan to continue with this work? It would be very helpful.
+1 from me.
Quoted 3 lines
I also wonder if Exynos 4412 could be re-added (without the boost if these bindings are not ready)?
I would prefer to have all platforms converted at once, since it might happen that some parts of the work would get lost.
Quoted 3 lines
Best regards,
Krzysztof
Signature · 5 lines
Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
Hello!
Quoted 7 lines · Lukasz Majewski
Hi Krzysztof, Thomas,
Quoted 4 lines
2015-01-08 22:17 GMT+01:00 Kevin Hilman <[email protected]>:
Hi Thomas,Do you plan to continue with this work? It would be very helpful.
Quoted 8 lines
+1 from me.
Quoted 3 lines
I also wonder if Exynos 4412 could be re-added (without the boost if these bindings are not ready)?
I would prefer to have all platforms converted at once, since it might happen that some parts of the work would get lost.
Joining in as well!
Reviving this patch series would be very much appreciated, especially if it moves again into the direction of storing most information into the DT (so that one can easily modify it in the board dts).
With best wishes,
Tobias
v12 cover cpufreq: use generic cpufreq drivers for exynos platforms
Hello Thomas,
Quoted 19 lines · Tobias Jakobi
Hello!
Quoted 7 lines · Lukasz Majewski
Hi Krzysztof, Thomas,
Quoted 4 lines
2015-01-08 22:17 GMT+01:00 Kevin Hilman <[email protected]>:
Hi Thomas,Do you plan to continue with this work? It would be very helpful.
Quoted 8 lines
+1 from me.
Quoted 3 lines
I also wonder if Exynos 4412 could be re-added (without the boost if these bindings are not ready)?
I would prefer to have all platforms converted at once, since it might happen that some parts of the work would get lost.
Quoted 9 lines
Joining in as well!
Reviving this patch series would be very much appreciated, especially if it moves again into the direction of storing most information into the DT (so that one can easily modify it in the board dts).
With best wishes,
Tobias
As others stated, it would be very useful to get this patch-set in but the current version has some issues as Kevin mentioned.
Are you planning to continue working on this series?
Best regards,
Javier