Skip to contentSkip to conversation

cpu cache info in drivers base?

-next Heiko Carstens 3 participants 4 messages Nov 24, 2014 – Nov 25, 2014 Linux-next tree

lore
Share & tools
lore
#0 lore raw

Hi there,

I'm just wondering what the point of the current cpu cache info within drivers/base is?
If I startup linux-next (as of today) all I get is an error message "error detecting cacheinfo..cpu0".
Which naturally comes from:

int __weak init_cache_level(unsigned int cpu)

{
	return -ENOENT;
}

Given that there is no implementation without __weak I'm wondering what the point is? Also it looks like no architecture has been converted to the new infrastructure, even though such patches have been posted in the past?

#1 lore raw

Hi Heiko,

Quoted 6 lines · Heiko Carstens

Hi there,

I'm just wondering what the point of the current cpu cache info within drivers/base is?
If I startup linux-next (as of today) all I get is an error message "error detecting cacheinfo..cpu0".

That's correct, I did post a patch[1] to suppress that given not all architectures might add support.

Quoted 11 lines

Which naturally comes from:

int __weak init_cache_level(unsigned int cpu)

{
	return -ENOENT;
}

Given that there is no implementation without __weak I'm wondering what the point is? Also it looks like no architecture has been converted to the new infrastructure, even though such patches have been posted in the past?

Yes, I asked Greg to hold off on the architecture patches for next versions as there may be conflicts(though we can have solve it using a common baseline, but I thought it was too late to try that). Also I have not got testing on few other architectures(ppc, ia64, amd). I will post those patches individually on respective arch lists and chase after the v3.19-rc1 release. Is that OK ?

Regards,
Sudeep

[1] https://lkml.org/lkml/2014/11/12/351

#2 lore raw
Quoted 25 lines · Sudeep Holla

Hi Heiko,

Quoted 6 lines · Heiko Carstens

Hi there,

I'm just wondering what the point of the current cpu cache info within drivers/base is?
If I startup linux-next (as of today) all I get is an error message "error detecting cacheinfo..cpu0".

That's correct, I did post a patch[1] to suppress that given not all architectures might add support.

Quoted 11 lines

Which naturally comes from:

int __weak init_cache_level(unsigned int cpu)

{
	return -ENOENT;
}

Given that there is no implementation without __weak I'm wondering what the point is? Also it looks like no architecture has been converted to the new infrastructure, even though such patches have been posted in the past?

Quoted 6 lines

Yes, I asked Greg to hold off on the architecture patches for next versions as there may be conflicts(though we can have solve it using a common baseline, but I thought it was too late to try that). Also I have not got testing on few other architectures(ppc, ia64, amd). I will post those patches individually on respective arch lists and chase after the v3.19-rc1 release. Is that OK ?

Sorry for the delay, that patch is now applied.

greg k-h

#3 lore raw
In reply to Sudeep Holla
Quoted 25 lines · Sudeep Holla

Hi Heiko,

Quoted 6 lines · Heiko Carstens

Hi there,

I'm just wondering what the point of the current cpu cache info within drivers/base is?
If I startup linux-next (as of today) all I get is an error message "error detecting cacheinfo..cpu0".

That's correct, I did post a patch[1] to suppress that given not all architectures might add support.

Quoted 11 lines

Which naturally comes from:

int __weak init_cache_level(unsigned int cpu)

{
	return -ENOENT;
}

Given that there is no implementation without __weak I'm wondering what the point is? Also it looks like no architecture has been converted to the new infrastructure, even though such patches have been posted in the past?

Quoted 6 lines

Yes, I asked Greg to hold off on the architecture patches for next versions as there may be conflicts(though we can have solve it using a common baseline, but I thought it was too late to try that). Also I have not got testing on few other architectures(ppc, ia64, amd). I will post those patches individually on respective arch lists and chase after the v3.19-rc1 release. Is that OK ?

Ok, thanks for clarifying!