arm: ls102xa: Add snoop disable for slave port 0, 1 and 2

PATCH New Alison Wang 2 participants 10 messages Oct 17, 2014 – Nov 25, 2014 Arm (32-bit)

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Alison Wang

author

2014-10-17 07:26 UTC #0 lore raw

PATCH v2 1/5 arm: ls102xa: Add snoop disable for slave port 0, 1 and 2

From: Jason Jin <[email protected]>

Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.

Signed-off-by Jason Jin <[email protected]>

Signed-off-by Minghuan Lian <[email protected]>

---
Change log:
v2: Add tag "arm: ls102xa:" in the subject.

 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 board/freescale/ls1021aqds/ls1021aqds.c           |  7 +++++++
 board/freescale/ls1021atwr/ls1021atwr.c           | 10 ++++++++++
 3 files changed, 18 insertions(+)

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1 -0

index 7995fe2..a1f4fdb 100644
@@ -448,6 +448,7 @@ struct ccsr_ddr {
 
 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
 #define CCI400_CTRLORD_EN_BARRIER	0
+#define CCI400_SHAORD_NON_SHAREABLE	0x00000002
 
 /* CCI-400 registers */
 struct ccsr_cci400 {

board/freescale/ls1021aqds/ls1021aqds.c +7 -0

index 12e83f7..e32dbeb 100644
@@ -220,6 +220,13 @@ int board_init(void)
 	/* Set CCI-400 control override register to
 	 * enable barrier transaction */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

board/freescale/ls1021atwr/ls1021atwr.c +10 -0

index b522ff2..811c911 100644
@@ -272,6 +272,16 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	fsl_serdes_init();
 	config_serdes_mux();

Signature · 1 line

2.1.0.27.g96db324

Alison Wang

author

2014-10-17 07:26 UTC #1 lore raw

PATCH v2 2/5 arm: ls102xa: Remove bit reversing for SCFG registers

SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode.

Address: 157_0000h base + 200h offset = 157_0200h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31

This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode in u-boot or kernel directly.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v2: Remove the defines for SCFG_SCFGREVCR_REV and
SCFG_SCFGREVCR_NOREV.

 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 --
 board/freescale/ls1021aqds/ls1021aqds.c           | 2 --
 board/freescale/ls1021atwr/ls1021atwr.c           | 5 -----
 3 files changed, 9 deletions(-)

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +0 -2

index a1f4fdb..73f335d 100644
@@ -95,8 +95,6 @@ struct ccsr_gur {
 	u32	sdhcpcr;
 };
 
-#define SCFG_SCFGREVCR_REV		0xffffffff
-#define SCFG_SCFGREVCR_NOREV		0
 #define SCFG_ETSECDMAMCR_LE_BD_FR	0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000

board/freescale/ls1021aqds/ls1021aqds.c +0 -2

index e32dbeb..56028f8 100644
@@ -136,9 +136,7 @@ int board_early_init_f(void)
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 #ifdef CONFIG_FSL_IFC

board/freescale/ls1021atwr/ls1021atwr.c +0 -5

index 811c911..ff7130e 100644
@@ -250,11 +250,8 @@ int board_early_init_f(void)
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
-	udelay(10);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 #ifdef CONFIG_FSL_IFC

@@ -262,9 +259,7 @@ int board_early_init_f(void)
 #endif
 
 #ifdef CONFIG_FSL_DCU_FB
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 	return 0;

Signature · 1 line

2.1.0.27.g96db324

York Sun

2014-11-25 17:55 UTC #2 lore raw

PATCH v2 2/5 arm: ls102xa: Remove bit reversing for SCFG registers

Quoted 29 lines · Alison Wang

SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode.
Address: 157_0000h base + 200h offset = 157_0200h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31
This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode in u-boot or kernel directly.
Signed-off-by Alison Wang <[email protected]>
---
Change log:
v2: Remove the defines for SCFG_SCFGREVCR_REV and
SCFG_SCFGREVCR_NOREV.

Quoted 5 lines

 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 --
 board/freescale/ls1021aqds/ls1021aqds.c           | 2 --
 board/freescale/ls1021atwr/ls1021atwr.c           | 5 -----
 3 files changed, 9 deletions(-)

Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks.

York

Alison Wang

author

2014-10-17 07:26 UTC #3 lore raw

PATCH v2 3/5 ls102xa: ifc: nor: fix the write issue when bytes unaligned

In reply to Alison Wang

From: Yuan Yao <[email protected]>

Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash write should swap the bytes when handle unaligned tail bytes.

Because of the ending, if the date bus width is 16-bits and the number of bytes is odd, we should swap the byte when write the last one.

Signed-off-by Yuan Yao <[email protected]>

---
Change log:
v2: Change the commits to match with the subject.

 include/configs/ls1021aqds.h | 1 +
 include/configs/ls1021atwr.h | 1 +
 2 files changed, 2 insertions(+)

include/configs/ls1021aqds.h +1 -0

index bb47813..7e78e78 100644
@@ -109,6 +109,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */

include/configs/ls1021atwr.h +1 -0

index 45b2272..2427f2e 100644
@@ -93,6 +93,7 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
 
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 /* CPLD */

Signature · 1 line

2.1.0.27.g96db324

York Sun

2014-11-25 17:55 UTC #4 lore raw

PATCH v2 3/5 ls102xa: ifc: nor: fix the write issue when bytes unaligned

Quoted 10 lines · Alison Wang

From: Yuan Yao <[email protected]>
Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash write should swap the bytes when handle unaligned tail bytes.
Because of the ending, if the date bus width is 16-bits and the number of bytes is odd, we should swap the byte when write the last one.

Quoted 8 lines

Signed-off-by Yuan Yao <[email protected]>
---
Change log:
v2: Change the commits to match with the subject.
 include/configs/ls1021aqds.h | 1 +
 include/configs/ls1021atwr.h | 1 +
 2 files changed, 2 insertions(+)

Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks.

York

Alison Wang

author

2014-10-17 07:26 UTC #5 lore raw

PATCH v2 4/5 arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board

In reply to Alison Wang

SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board.

As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC.

As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v2: Add the compatibility in SD boot.

 board/freescale/common/sys_eeprom.c |  4 ++--
 include/configs/ls1021atwr.h        | 11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

board/freescale/common/sys_eeprom.c +2 -2

index 6144c53..3426b8a 100644
@@ -90,7 +90,7 @@ static void show_eeprom(void)
 	/* EEPROM tag ID, either CCID or NXID */
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif

@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
 
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif

include/configs/ls1021atwr.h +11 -0

index 2427f2e..1914e3d 100644
@@ -155,6 +155,17 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 
+/* EEPROM */
+#ifndef CONFIG_SD_BOOT
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#endif
+
 /*
  * MMC
  */

Signature · 1 line

2.1.0.27.g96db324

York Sun

2014-11-25 17:56 UTC #6 lore raw

PATCH v2 4/5 arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board

Quoted 10 lines · Alison Wang

SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board.
As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC.
As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot.

Quoted 9 lines

Signed-off-by Alison Wang <[email protected]>
---
Change log:
v2: Add the compatibility in SD boot.
 board/freescale/common/sys_eeprom.c |  4 ++--
 include/configs/ls1021atwr.h        | 11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks.

York

Alison Wang

author

2014-10-17 07:26 UTC #7 lore raw

PATCH v2 5/5 arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing

In reply to Alison Wang

EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1 as other functionality except RGMII. The workaround is to select ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.

Signed-off-by Alison Wang <[email protected]>

---
Change log:
v2: New patch.

 board/freescale/ls1021aqds/ls1021aqds.c | 1 +
 1 file changed, 1 insertion(+)

board/freescale/ls1021aqds/ls1021aqds.c +1 -0

index 56028f8..b744250 100644
@@ -137,6 +137,7 @@ int board_early_init_f(void)
 
 #ifdef CONFIG_TSEC_ENET
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 #endif
 
 #ifdef CONFIG_FSL_IFC

Signature · 1 line

2.1.0.27.g96db324

York Sun

2014-11-25 17:56 UTC #8 lore raw

PATCH v2 5/5 arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing

Quoted 5 lines · Alison Wang

EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1 as other functionality except RGMII. The workaround is to select ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.

Quoted 7 lines

Signed-off-by Alison Wang <[email protected]>
---
Change log:
v2: New patch.
 board/freescale/ls1021aqds/ls1021aqds.c | 1 +
 1 file changed, 1 insertion(+)

Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks.

York

York Sun

2014-11-25 17:54 UTC #9 lore raw

PATCH v2 1/5 arm: ls102xa: Add snoop disable for slave port 0, 1 and 2

In reply to Alison Wang

Quoted 7 lines · Alison Wang

From: Jason Jin <[email protected]>
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by Jason Jin <[email protected]>
Signed-off-by Minghuan Lian <[email protected]>

Quoted 8 lines

---
Change log:
v2: Add tag "arm: ls102xa:" in the subject.

 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 board/freescale/ls1021aqds/ls1021aqds.c           |  7 +++++++
 board/freescale/ls1021atwr/ls1021atwr.c           | 10 ++++++++++
 3 files changed, 18 insertions(+)

Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks.

York