arm64: Add DTS support for FSL's LS2085A SoC
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PATCH v5 4/6 arm64: Add DTS support for FSL's LS2085A SoC
Hi Marc,
[big snip..]
Quoted 10 lines
Review
Quoted 7 lines
(quoted diff) +6
-0+ timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */ + <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */ + <1 11 0x1>, /* Virtual PPI, edge triggered */ + <1 10 0x1>; /* Hypervisor PPI, edge triggered */Are you sure about this "edge triggered"? The A57 TRM suggests otherwise:
Quoted 3 lines
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1
382454511590.html
Actually I did read the TRM but was confused by the "edge triggered" conventions used by Juno ARMv8 DTSI (see [1]). I see other ARMv8 DTSI also using the "edge triggered" notion, so I was wondering if I am missing some A57 errata or these DTSI also need fixing.
Regards,
Bhupesh
PATCH v5 4/6 arm64: Add DTS support for FSL's LS2085A SoC
Quoted 14 lines · bhupesh.sharma at freescale.com
Hi Marc,
[big snip..]
Quoted 10 lines
Review
Quoted 7 lines
(quoted diff) +6
-0+ timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */ + <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */ + <1 11 0x1>, /* Virtual PPI, edge triggered */ + <1 10 0x1>; /* Hypervisor PPI, edge triggered */Are you sure about this "edge triggered"? The A57 TRM suggests otherwise:
Quoted 7 lines
Quoted 3 lines
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1
382454511590.htmlActually I did read the TRM but was confused by the "edge triggered" conventions used by Juno ARMv8 DTSI (see [1]). I see other ARMv8 DTSI also using the "edge triggered" notion, so I was wondering if I am missing some A57 errata or these DTSI also need fixing.
Yeah, the Juno DT is wrong as well. Funny how only the wrong bits get copied over and over... I'll get Juno fixed.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...