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spi: sh-msiof: Configure MSIOF sync signal timing in device tree

RFC PATCH Superseded Yoshihiro Shimoda 3 participants 5 messages Nov 28, 2014 – Dec 15, 2014 2 messages not in the archive

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#0 lore raw

RFC PATCH 1/1 spi: sh-msiof: Configure MSIOF sync signal timing in device tree

The MSIOF controller has DTDL and SYNCDL in SITMDR1 and SIRMDR1 registers. So, this patch adds new properties like the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

The DTDL is the chip select (SYNC) setup time.
b'000: No bit delay
b'001: 1-clock-cycle delay
b'010: 2-clock-cycle delay
b'101: 0.5-clock-cycle delay
b'110: 1.5-clock-cycle delay

The SYNCDL is the chip select (SYNC) hold time.
b'000: No bit delay
b'001: 1-clock-cycle delay
b'010: 2-clock-cycle delay
b'011: 3-clock-cycle delay
b'101: 0.5-clock-cycle delay
b'110: 1.5-clock-cycle delay

---

I would like to add new properties for sh-msiof driver to adjust
the SYNC siginal timing using DTDL and SYNCDL. In the current driver, these parameters are hardcoded to 0. And then, I checked other spi drivers, and I found the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

If this patch is reasonable, I will modify the sh-msiof driver. Or, should we add a new function for this timing adjusting in the spi framework?

 Documentation/devicetree/bindings/spi/sh-msiof.txt |    8 ++++++++
 drivers/spi/spi-sh-msiof.c                         |    2 ++
 2 files changed, 10 insertions(+)
Documentation/devicetree/bindings/spi/sh-msiof.txt +8 -0
index d11c372..5fe8ffd 100644
@@ -30,6 +30,14 @@ Optional properties:
 			 specifiers, one for transmission, and one for
 			 reception.
 - dma-names            : Must contain a list of two DMA names, "tx" and "rx".
+- renesas,tdmr-dtdl    : delay sync signal (setup) in transmit mode
+			 (default is 0, we can set it to 0, 1, 2, 5, or 6)
+- renesas,tdmr-syncdl  : delay sync signal (hold) in transmit mode
+			 (default is 0, we can set it to 0, 1, 2, 3, 5, or 6)
+- renesas,rdmr-dtdl    : delay sync signal (setup) in receive mode
+			 (default is 0, we can set it to 0, 1, 2, 5, or 6)
+- renesas,rdmr-syncdl  : delay sync signal (hold) in receive mode
+			 (default is 0, we can set it to 0, 1, 2, 3, 5, or 6)
 
 Optional properties, deprecated for soctype-specific bindings:
 - renesas,tx-fifo-size : Overrides the default tx fifo size given in words
drivers/spi/spi-sh-msiof.c +2 -0
index 3f36540..09e0c38 100644
@@ -296,11 +296,13 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
 	tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
 	tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
 	tmp |= lsb_first << MDR1_BITLSB_SHIFT;
+printk("%s: TMDR1 = %x\n", __func__, tmp | MDR1_TRMD | TMDR1_PCON);
 	sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
 	if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
 		/* These bits are reserved if RX needs TX */
 		tmp &= ~0x0000ffff;
 	}
+printk("%s: RMDR1 = %x\n", __func__, tmp);
 	sh_msiof_write(p, RMDR1, tmp);
 
 	tmp = 0;
Signature · 6 lines
1.7.9.5

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#2 lore raw

Hi Shimoda-san,

Thank you for the patch.

Quoted 50 lines · On Friday 28 November 2014 12:45:27 Yoshihiro Shimoda wrote:

The MSIOF controller has DTDL and SYNCDL in SITMDR1 and SIRMDR1 registers. So, this patch adds new properties like the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

The DTDL is the chip select (SYNC) setup time.
b'000: No bit delay
b'001: 1-clock-cycle delay
b'010: 2-clock-cycle delay
b'101: 0.5-clock-cycle delay
b'110: 1.5-clock-cycle delay

The SYNCDL is the chip select (SYNC) hold time.
b'000: No bit delay
b'001: 1-clock-cycle delay
b'010: 2-clock-cycle delay
b'011: 3-clock-cycle delay
b'101: 0.5-clock-cycle delay
b'110: 1.5-clock-cycle delay

---

I would like to add new properties for sh-msiof driver to adjust
the SYNC siginal timing using DTDL and SYNCDL. In the current driver, these parameters are hardcoded to 0. And then, I checked other spi drivers, and I found the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

If this patch is reasonable, I will modify the sh-msiof driver. Or, should we add a new function for this timing adjusting in the spi framework?

 Documentation/devicetree/bindings/spi/sh-msiof.txt |    8 ++++++++
 drivers/spi/spi-sh-msiof.c                         |    2 ++
 2 files changed, 10 insertions(+)
(quoted diff) +0 -0

b/Documentation/devicetree/bindings/spi/sh-msiof.txt index d11c372..5fe8ffd 100644

Documentation/devicetree/bindings/spi/sh-msiof.txt +0 -0
@@ -30,6 +30,14 @@ Optional properties:
 			 specifiers, one for transmission, and one for
 			 reception.
 - dma-names            : Must contain a list of two DMA names, "tx" and

"rx".
+- renesas,tdmr-dtdl : delay sync signal (setup) in transmit mode

Documentation/devicetree/bindings/spi/sh-msiof.txt Optional properties: · line 40

Quoted 7 lines
Documentation/devicetree/bindings/spi/sh-msiof.txt +7 -0
+			 (default is 0, we can set it to 0, 1, 2, 5, or 6)
+- renesas,tdmr-syncdl  : delay sync signal (hold) in transmit mode
+			 (default is 0, we can set it to 0, 1, 2, 3, 5, or 6)
+- renesas,rdmr-dtdl    : delay sync signal (setup) in receive mode
+			 (default is 0, we can set it to 0, 1, 2, 5, or 6)
+- renesas,rdmr-syncdl  : delay sync signal (hold) in receive mode
+			 (default is 0, we can set it to 0, 1, 2, 3, 5, or 6)

Was it really the intent of this patch to add DT properties without providing an implementation in the sh-msiof driver ?

Quoted 9 lines

Optional properties, deprecated for soctype-specific bindings:
- renesas,tx-fifo-size : Overrides the default tx fifo size given in words

drivers/spi/spi-sh-msiof.c +0 -0
index 3f36540..09e0c38 100644
@@ -296,11 +296,13 @@ static void sh_msiof_spi_set_pin_regs(struct

sh_msiof_spi_priv *p, tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;

drivers/spi/spi-sh-msiof.c static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, · line 305

Quoted 9 lines
drivers/spi/spi-sh-msiof.c +2 -0
 	tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
 	tmp |= lsb_first << MDR1_BITLSB_SHIFT;
+printk("%s: TMDR1 = %x\n", __func__, tmp | MDR1_TRMD | TMDR1_PCON);
 	sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
 	if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
 		/* These bits are reserved if RX needs TX */
 		tmp &= ~0x0000ffff;
 	}
+printk("%s: RMDR1 = %x\n", __func__, tmp);

I suppose these printk are debugging leftovers.

Quoted 3 lines
drivers/spi/spi-sh-msiof.c +0 -0
 	sh_msiof_write(p, RMDR1, tmp);
 
 	tmp = 0;
Signature · 7 lines
Regards,

Laurent Pinchart
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#3 lore raw

Hi Shimoda-san, Laurent,

Quoted 14 lines · Laurent Pinchart
Quoted 13 lines · On Friday 28 November 2014 12:45:27 Yoshihiro Shimoda wrote:

The MSIOF controller has DTDL and SYNCDL in SITMDR1 and SIRMDR1 registers. So, this patch adds new properties like the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

The DTDL is the chip select (SYNC) setup time.
b'000: No bit delay
b'001: 1-clock-cycle delay
b'010: 2-clock-cycle delay
b'101: 0.5-clock-cycle delay
b'110: 1.5-clock-cycle delay

Quoted 7 lines
Quoted 7 lines

The SYNCDL is the chip select (SYNC) hold time.
b'000: No bit delay
b'001: 1-clock-cycle delay
b'010: 2-clock-cycle delay
b'011: 3-clock-cycle delay
b'101: 0.5-clock-cycle delay
b'110: 1.5-clock-cycle delay

You forgot to quote the last line from the DTDL and SYNCDL paragraphs:

| In case of SPI mode, only 000 is allowed to set to this field.

And the spi-sh-msiof driver is using the MSIOF in SPI mode???

Quoted 28 lines
Quoted 28 lines

---

I would like to add new properties for sh-msiof driver to adjust
the SYNC siginal timing using DTDL and SYNCDL. In the current driver, these parameters are hardcoded to 0. And then, I checked other spi drivers, and I found the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

If this patch is reasonable, I will modify the sh-msiof driver. Or, should we add a new function for this timing adjusting in the spi framework?

 Documentation/devicetree/bindings/spi/sh-msiof.txt |    8 ++++++++
 drivers/spi/spi-sh-msiof.c                         |    2 ++
 2 files changed, 10 insertions(+)
(quoted diff) +0 -0

b/Documentation/devicetree/bindings/spi/sh-msiof.txt index d11c372..5fe8ffd 100644

Documentation/devicetree/bindings/spi/sh-msiof.txt +0 -0
@@ -30,6 +30,14 @@ Optional properties:
                       specifiers, one for transmission, and one for
                       reception.
 - dma-names            : Must contain a list of two DMA names, "tx" and

"rx".

Quoted 8 lines

Documentation/devicetree/bindings/spi/sh-msiof.txt Optional properties: · line 40

Quoted 8 lines

+- renesas,tdmr-dtdl : delay sync signal (setup) in transmit mode

Documentation/devicetree/bindings/spi/sh-msiof.txt +7 -0
+                      (default is 0, we can set it to 0, 1, 2, 5, or 6)
+- renesas,tdmr-syncdl  : delay sync signal (hold) in transmit mode
+                      (default is 0, we can set it to 0, 1, 2, 3, 5, or 6)
+- renesas,rdmr-dtdl    : delay sync signal (setup) in receive mode
+                      (default is 0, we can set it to 0, 1, 2, 5, or 6)
+- renesas,rdmr-syncdl  : delay sync signal (hold) in receive mode
+                      (default is 0, we can set it to 0, 1, 2, 3, 5, or 6)

In general, it's frowned upon the specify actual register values in DT. So I think it's better to specify the delay values instead of the bitfield values,
and drop the "tdmr" and "rdmr" from the names.
As DT supports integers only, that should become a fixed point value. E.g. delay in deci-clocks (0, 5, 10, 15, 20)?
Or as a percentage of the clock cycle (0, 50, 100, 150, 200)?

Do you really need two sets of values, for both transmit and receive? I.e. do you need different values for transmit and receive for your use case? SPI does both transmit and receive using the same clock and chip select. I know some MSIOF implementations can handle both indepedently.

And to answer your last question: if several drivers need this, it makes sense to make this general, and add support in the SPI core. Mark?

Quoted 2 lines

Was it really the intent of this patch to add DT properties without providing an implementation in the sh-msiof driver ?

Given the sentence "If this patch is reasonable, I will modify the sh-msiof driver." in the introduction, I think so.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

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#5 lore raw

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#6 lore raw
In reply to a message not in the archive

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