arm64: Add the support for new 64-bit Exynos5433 SoC
Subsystems (7)
Chanwoo Choi
maintainerv2 cover arm64: Add the support for new 64-bit Exynos5433 SoC
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock control for Exynos5433 using common clk framework
This patchst is based on linux-samsung.git (branch: v3.19-next/dt-samsung-64)
This patchset has the dependency as following list:
: The Exynos7 patchset[1] specified dependent patchset for 64-bit SoC.
So, this patchset used same dependent patchset of Exynos7 patchset and Exynos7 patchset about pinctrl patch. Additionally, SPI/MMC/PDMA patch [2-5] is used for kernel booting and mounting rootfs.
1. [PATCH v7 0/7] Enable support for Samsung Exynos7 SoC
- [1] http://www.spinics.net/lists/linux-samsung-soc/msg38734.html
2. [PATCH] spi: s3c64xx: add support for exynos7 SPI controller
- [2] http://www.spinics.net/lists/linux-samsung-soc/msg38607.html
3. [PATCH V7] mmc: dw_mmc: Add IDMAC 64-bit address mode support
- [3] https://lkml.org/lkml/2014/10/20/58
4. [PATCH] mmc: dw_mmc: exynos: Add support for exynos7
- [4] http://www.spinics.net/lists/linux-mmc/msg28294.html
5. [PATCH] dmaengine: pl330: Correct device assignment
- [5] https://lkml.org/lkml/2014/11/6/207
Changes from v1:
- Merge two patches (patch2, patch3) to solve incomplete description [by Arnd]
- Exynos5433 Clock driver
: Fix wrong register and code clean by using space instead of tab [Pankaj] : Add CLK_IGNORE_UNUSED flag to pclk_sysreg_* clock for accessing system control register : Remove duplicate definition on the patch for CMU_BUS{0|1|2} domain
- Exynos5433 SoC DTS
: Remove un-supported properties of arch_timer [by Marc and Mark]
: Remove 'clock-frequency' property from 'cpus' dt node
: Fix interrupt type from edge rising triggering to level high triggering
because Cortex-A53/A57 use level triggering.
: Fix defult address-size/size-celss from 1 to 2 because Exynos5433 is 64-bit SoC : Modify 'fin_pll' dt node to remove un-needed and ugly code
: Move 'chipid' dt node under 'soc'
: Use lowercase on all case in exynos5433.dtsi
: Add PSCI dt node for secondary cpu boot
: Add 'samsung,exynos5433' compatible to MCT dt node
- Divide pinctrl patch from this patchset
- Add new following patches:
: clocksource: exynos_mct: Add the support for Exynos 64bit SoC
: arm64: Enable Exynos5433 SoC in the defconfig
Chanwoo Choi (18):
clk: samsung: exynos5433: Add clocks using common clock framework
clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
clk: samsung: exynos5433: Add clocks for CMU_G2D domain
clk: samsung: exynos5433: Add clocks for CMU_MIF domain
clk: samsung: exynos5433: Add clocks for CMU_DISP domain
clk: samsung: exynos5433: Add clocks for CMU_AUD domain
clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
clk: samsung: exynos5433: Add clocks for CMU_G3D domain
clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
serial: samsung: Add the support for Exynos5433 SoC
clocksource: exynos_mct: Add the support for Exynos 64bit SoC
arm64: Enable Exynos5433 SoC in the defconfig
Jaehoon Chung (1):
arm64: dts: exynos: Add MSHC dt node for Exynos5433
.../devicetree/bindings/clock/exynos5433-clock.txt | 167 + arch/arm64/Kconfig | 10 + arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 ++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 675 ++++ arch/arm64/configs/defconfig | 1 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5433.c | 3369 ++++++++++++++++++++ drivers/clocksource/Kconfig | 1 - drivers/clocksource/exynos_mct.c | 4 + drivers/tty/serial/samsung.c | 56 +- include/dt-bindings/clock/exynos5433.h | 843 +++++ 11 files changed, 5804 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5433.c create mode 100644 include/dt-bindings/clock/exynos5433.h
Signature · 1 line
1.8.5.5
Chanwoo Choi
maintainerPATCH v2 1/19 clk: samsung: exynos5433: Add clocks using common clock framework
This patch adds the support for CMU (Clock Management Units) of Exynos5433 which is 64bit SoC and has Octa-cores. This patch supports necessary clocks (PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation for Exynos5433 clock controller.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 106 +++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5433.c | 967 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 199 +++++ 4 files changed, 1273 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5433.c create mode 100644 include/dt-bindings/clock/exynos5433.h
Documentation/devicetree/bindings/clock/exynos5433-clock.txt new file +106 -0
@@ -0,0 +1,106 @@ +* Samsung Exynos5433 CMU (Clock Management Units) + +The Exynos5433 clock controller generates and supplies clock to various +controllers within the Exynos5433 SoC. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS + domains and bus clocks. + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF + which generates clocks for LLI (Low Latency Interface) IP. + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF + which generates clocks for DRAM Memory Controller domain. + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5433.h header and can be used in device +tree sources. + +Example 1: Examples of clock controller nodes are listed below. + + cmu_top: clock-controller at 0x10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x0c04>; + #clock-cells = <1>; + }; + + cmu_cpif: clock-controller at 0x10fc0000 { + compatible = "samsung,exynos5433-cmu-cpif"; + reg = <0x10fc0000 0x0c04>; + #clock-cells = <1>; + }; + + cmu_mif: clock-controller at 0x105b0000 { + compatible = "samsung,exynos5433-cmu-mif"; + reg = <0x105b0000 0x100c>; + #clock-cells = <1>; + }; + + cmu_peric: clock-controller at 0x14c80000 { + compatible = "samsung,exynos5433-cmu-peric"; + reg = <0x14c80000 0x0b08>; + #clock-cells = <1>; + }; + + cmu_peris: clock-controller at 0x10040000 { + compatible = "samsung,exynos5433-cmu-peris"; + reg = <0x10040000 0x0b20>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller at 0x156e0000 { + compatible = "samsung,exynos5433-cmu-fsys"; + reg = <0x156e0000 0x0b04>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the clock + controller. + + serial_0: serial at 14C10000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14C10000 0x100>; + interrupts = <0 421 0>; + clocks = <&cmu_peric CLK_PCLK_UART0>, + <&cmu_peric CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + status = "disabled"; + }; + +Example 3: SPI controller node that consumes the clock generated by the clock + controller. + + spi_0: spi at 14d20000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d20000 0x100>; + interrupts = <0 432 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI0>, + <&cmu_top CLK_SCLK_SPI0_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + };
drivers/clk/samsung/Makefile +1 -0
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o +obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
drivers/clk/samsung/clk-exynos5433.c new file +967 -0
967 lines not on this page · raw message
include/dt-bindings/clock/exynos5433.h new file +199 -0
199 lines not on this page · raw message
Signature · 1 line
1.8.5.5
PATCH 1/19 clk: samsung: exynos5433: Add clocks using common clock framework
Hi Chanwoo,
Quoted 20 lines · Chanwoo Choi
This patch adds the support for CMU (Clock Management Units) of Exynos5433 which is 64bit SoC and has Octa-cores. This patch supports necessary clocks (PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation for Exynos5433 clock controller.
Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- .../devicetree/bindings/clock/exynos5433-clock.txt | 106 +++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5433.c | 967 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 199 +++++ 4 files changed, 1273 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/exynos5433-clock.txtcreate mode 100644drivers/clk/samsung/clk-exynos5433.c
create mode 100644include/dt-bindings/clock/exynos5433.h
[snip]
drivers/clk/samsung/clk-exynos5433.c line 335
Quoted 8 lines
drivers/clk/samsung/clk-exynos5433.c new file +8
-0+ +static struct samsung_div_clock top_div_clks[]__initdata = { +/* DIV_TOP2 */ +DIV (CLK_DIV_ACLK_FSYS_200 ,"div_aclk_fsys_200" ,"mout_bus_pll_user" , +DIV_TOP2 ,0 ,3 ), + +/* DIV_TOP3 */ + DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",
As per UM, this clock name should be imem_sssx_266
Quoted 12 lines
drivers/clk/samsung/clk-exynos5433.c new file +12
-0+ "mout_bus_pll_user", DIV_TOP3, 24, 3), +DIV (CLK_DIV_ACLK_IMEM_200 ,"div_aclk_imem_200" , +"mout_bus_pll_user" ,DIV_TOP3 ,20 ,3 ), +DIV (CLK_DIV_ACLK_IMEM_266 ,"div_aclk_imem_266" , +"mout_bus_pll_user" ,DIV_TOP3 ,16 ,3 ), +DIV (CLK_DIV_ACLK_PERIC_66_B ,"div_aclk_peric_66_b" , +"div_aclk_peric_66_a" ,DIV_TOP3 ,12 ,3 ), +DIV (CLK_DIV_ACLK_PERIC_66_A ,"div_aclk_peric_66_a" , +"mout_bus_pll_user" ,DIV_TOP3 ,8 ,3 ), +DIV (CLK_DIV_ACLK_PERIS_66_B ,"div_aclk_peris_66_b" , +"div_aclk_peris_66_a" ,DIV_TOP3 ,4 ,3 ), + DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
[snip]
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c new file +10
-0+ +static void __init exynos5433_cmu_mif_init (struct device_node *np) +{ +samsung_cmu_register_one (np, &mif_cmu_info); +} +CLK_OF_DECLARE (exynos5433_cmu_mif,"samsung,exynos5433-cmu-mif" , + exynos5433_cmu_mif_init); + +/* +* Register offset definitions for CMU_PERIC
drivers/clk/samsung/clk-exynos5433.c line 680
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c new file +10
-0+*/ +#define DIV_PERIC 0x0600 +#define ENABLE_ACLK_PERIC 0x0800 +#define ENABLE_PCLK_PERIC0 0x0900 +#define ENABLE_PCLK_PERIC1 0x0904 +#define ENABLE_SCLK_PERIC 0x0A00 +#define ENABLE_IP_PERIC0 0x0B00 +#define ENABLE_IP_PERIC1 0x0B04 +#define ENABLE_IP_PERIC2 0x0B08 +
nit: Just for consistency, all these offset should be in small case.
drivers/clk/samsung/clk-exynos5433.c line 691
Quoted 11 lines
drivers/clk/samsung/clk-exynos5433.c new file +11
-0+static unsigned long peric_clk_regs[]__initdata = { +DIV_PERIC , +ENABLE_ACLK_PERIC , +ENABLE_PCLK_PERIC0 , +ENABLE_PCLK_PERIC1 , +ENABLE_SCLK_PERIC , +ENABLE_IP_PERIC0 , +ENABLE_IP_PERIC1 , +ENABLE_IP_PERIC2 , +}; +
[snip]
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 1/19 clk: samsung: exynos5433: Add clocks using common clock framework
Hi Pankaj,
Quoted 26 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 20 lines · Chanwoo Choi
This patch adds the support for CMU (Clock Management Units) of Exynos5433 which is 64bit SoC and has Octa-cores. This patch supports necessary clocks (PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation for Exynos5433 clock controller.
Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- .../devicetree/bindings/clock/exynos5433-clock.txt | 106 +++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5433.c | 967 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 199 +++++ 4 files changed, 1273 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/exynos5433-clock.txtcreate mode 100644drivers/clk/samsung/clk-exynos5433.c
create mode 100644include/dt-bindings/clock/exynos5433.h[snip]
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c line 335
Quoted 8 lines
drivers/clk/samsung/clk-exynos5433.c new file +8
-0+ +static struct samsung_div_clock top_div_clks[]__initdata = { +/* DIV_TOP2 */ +DIV (CLK_DIV_ACLK_FSYS_200 ,"div_aclk_fsys_200" ,"mout_bus_pll_user" , +DIV_TOP2 ,0 ,3 ), + +/* DIV_TOP3 */ + DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",As per UM, this clock name should be
imem_sssx_266
I fixed it on patch6 for CMU_MIF domain.
But, as you comment, I'll fix it on this patch(patch1).
Quoted 53 lines
Quoted 13 lines
drivers/clk/samsung/clk-exynos5433.c new file +12
-0+ "mout_bus_pll_user", DIV_TOP3, 24, 3), +DIV (CLK_DIV_ACLK_IMEM_200 ,"div_aclk_imem_200" , +"mout_bus_pll_user" ,DIV_TOP3 ,20 ,3 ), +DIV (CLK_DIV_ACLK_IMEM_266 ,"div_aclk_imem_266" , +"mout_bus_pll_user" ,DIV_TOP3 ,16 ,3 ), +DIV (CLK_DIV_ACLK_PERIC_66_B ,"div_aclk_peric_66_b" , +"div_aclk_peric_66_a" ,DIV_TOP3 ,12 ,3 ), +DIV (CLK_DIV_ACLK_PERIC_66_A ,"div_aclk_peric_66_a" , +"mout_bus_pll_user" ,DIV_TOP3 ,8 ,3 ), +DIV (CLK_DIV_ACLK_PERIS_66_B ,"div_aclk_peris_66_b" , +"div_aclk_peris_66_a" ,DIV_TOP3 ,4 ,3 ), + DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",[snip]
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c new file +10
-0+ +static void __init exynos5433_cmu_mif_init (struct device_node *np) +{ +samsung_cmu_register_one (np, &mif_cmu_info); +} +CLK_OF_DECLARE (exynos5433_cmu_mif,"samsung,exynos5433-cmu-mif" , + exynos5433_cmu_mif_init); + +/* +* Register offset definitions for CMU_PERIC drivers/clk/samsung/clk-exynos5433.c line 680
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c new file +10
-0+*/ +#define DIV_PERIC 0x0600 +#define ENABLE_ACLK_PERIC 0x0800 +#define ENABLE_PCLK_PERIC0 0x0900 +#define ENABLE_PCLK_PERIC1 0x0904 +#define ENABLE_SCLK_PERIC 0x0A00 +#define ENABLE_IP_PERIC0 0x0B00 +#define ENABLE_IP_PERIC1 0x0B04 +#define ENABLE_IP_PERIC2 0x0B08 +nit: Just for consistency, all these offset should be in small case.
Quoted 11 lines
drivers/clk/samsung/clk-exynos5433.c new file +11
-0+static unsigned long peric_clk_regs[]__initdata = { +DIV_PERIC , +ENABLE_ACLK_PERIC , +ENABLE_PCLK_PERIC0 , +ENABLE_PCLK_PERIC1 , +ENABLE_SCLK_PERIC , +ENABLE_IP_PERIC0 , +ENABLE_IP_PERIC1 , +ENABLE_IP_PERIC2 , +}; +[snip]
Quoted 5 lines
Thanks,
Pankaj Dubey
Thanks for your review.
Best Regards,
Chanwoo Choi
Chanwoo Choi
maintainerPATCH v2 2/19 clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
In reply to Chanwoo ChoiThis patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433. CMU_TOP domain provides source clocks to other CMU domains.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- drivers/clk/samsung/clk-exynos5433.c | 90 ++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 31 +++++++++++- 2 files changed, 119 insertions(+), 2 deletions(-)
drivers/clk/samsung/clk-exynos5433.c +90 -0
@@ -208,6 +208,7 @@ PNAME(mout_mphy_pll_user_p) = { "fin_pll", "sclk_mphy_pll", };PNAME (mout_mfc_pll_user_p) = {"fin_pll" ,"sclk_mfc_pll" , };PNAME (mout_bus_pll_user_p) = {"fin_pll" ,"sclk_bus_pll" , };PNAME (mout_bus_pll_user_t_p) = {"fin_pll" ,"mout_bus_pll_user" , }; +PNAME (mout_mphy_pll_user_t_p) = {"fin_pll" ,"mout_mphy_pll_user" , };PNAME (mout_bus_mfc_pll_user_p) = {"mout_bus_pll_user" ,"mout_mfc_pll_user" ,};PNAME (mout_mfc_bus_pll_user_p) = {"mout_mfc_pll_user" ,"mout_bus_pll_user" ,};
@@ -215,6 +216,12 @@ PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", "mout_mfc_pll_user", };PNAME (mout_aclk_cam1_552_a_p) = {"mout_isp_pll" ,"mout_bus_pll_user" , }; +PNAME (mout_aclk_mfc_400_c_p) = {"mout_aclk_mfc_400_b" , +"mout_mphy_pll_user" , }; +PNAME (mout_aclk_mfc_400_b_p) = {"mout_aclk_mfc_400_a" , +"mout_bus_pll_user" , }; +PNAME (mout_aclk_mfc_400_a_p) = {"mout_mfc_pll_user" ,"mout_isp_pll" , }; +PNAME (mout_bus_mphy_pll_user_p) = {"mout_bus_pll_user" ,"mout_mphy_pll_user" , };PNAME (mout_aclk_mscl_b_p) = {"mout_aclk_mscl_400_a" ,
@@ -231,11 +238,26 @@ PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };PNAME (mout_sclk_mmc0_c_p) = {"mout_sclk_mmc0_b" ,"mout_mphy_pll_user" ,};PNAME (mout_sclk_mmc0_b_p) = {"mout_sclk_mmc0_a" ,"mout_mfc_pll_user" , }; +PNAME (mout_sclk_spdif_p) = {"sclk_audio0" ,"sclk_audio1" , +"fin_pll" ,"ioclk_spdif_extclk" , }; +PNAME (mout_sclk_audio1_p) = {"ioclk_audiocdclk1" ,"fin_pll" , +"mout_aud_pll_user_t" ,}; +PNAME (mout_sclk_audio0_p) = {"ioclk_audiocdclk0" ,"fin_pll" , +"mout_aud_pll_user_t" ,}; +static struct samsung_fixed_factor_clock top_fixed_factor_clks[]__initdata = {FFACTOR (0 ,"sclk_bus_pll" ,"fout_bus_pll" ,1 ,1 ,0 ),FFACTOR (0 ,"sclk_mfc_pll" ,"fout_mfc_pll" ,1 ,1 ,0 ), }; +static struct samsung_fixed_rate_clock top_fixed_clks[]__initdata = { +/* Xi2s{0|1}CDCLK input clock for I2S/PCM */ +FRATE (0 ,"ioclk_audiocdclk1" ,NULL ,CLK_IS_ROOT ,100000000 ), +FRATE (0 ,"ioclk_audiocdclk0" ,NULL ,CLK_IS_ROOT ,100000000 ), +/* Xi2s1SDI input clock for SPDIF */ +FRATE (0 ,"ioclk_spdif_extclk" ,NULL ,CLK_IS_ROOT ,100000000 ), +}; +static struct samsung_mux_clock top_mux_clks[]__initdata = {/* MUX_SEL_TOP0 */ MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
@@ -281,6 +303,14 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {MUX (CLK_MOUT_ACLK_G2D_400_A ,"mout_aclk_g2d_400_a" , mout_bus_mfc_pll_user_p,MUX_SEL_TOP3 ,0 ,1 ), +/* MUX_SEL_TOP4 */ +MUX (CLK_MOUT_ACLK_MFC_400_C ,"mout_aclk_mfc_400_c" , + mout_aclk_mfc_400_c_p,MUX_SEL_TOP4 ,8 ,1 ), +MUX (CLK_MOUT_ACLK_MFC_400_B ,"mout_aclk_mfc_400_b" , + mout_aclk_mfc_400_b_p,MUX_SEL_TOP4 ,4 ,1 ), +MUX (CLK_MOUT_ACLK_MFC_400_A ,"mout_aclk_mfc_400_a" , + mout_aclk_mfc_400_a_p,MUX_SEL_TOP4 ,0 ,1 ), +/* MUX_SEL_TOP_MSCL */ MUX (CLK_MOUT_SCLK_JPEG_C ,"mout_sclk_jpeg_c" , mout_sclk_jpeg_c_p, MUX_SEL_TOP_MSCL, 8, 1),
@@ -289,6 +319,20 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {MUX (CLK_MOUT_SCLK_JPEG_A ,"mout_sclk_jpeg_a" , mout_bus_pll_user_t_p,MUX_SEL_TOP_MSCL ,0 ,1 ), +/* MUX_SEL_TOP_CAM1 */ +MUX (CLK_MOUT_SCLK_ISP_SENSOR2 ,"mout_sclk_isp_sensor2" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_CAM1 ,24 ,1 ), +MUX (CLK_MOUT_SCLK_ISP_SENSOR1 ,"mout_sclk_isp_sensor1" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_CAM1 ,20 ,1 ), +MUX (CLK_MOUT_SCLK_ISP_SENSOR0 ,"mout_sclk_isp_sensor0" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_CAM1 ,16 ,1 ), +MUX (CLK_MOUT_SCLK_ISP_UART ,"mout_sclk_isp_uart" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_CAM1 ,8 ,1 ), +MUX (CLK_MOUT_SCLK_ISP_SPI1 ,"mout_sclk_isp_spi1" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_CAM1 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_ISP_SPI0 ,"mout_sclk_isp_spi0" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_CAM1 ,0 ,1 ), +/* MUX_SEL_TOP_FSYS0 */ MUX (CLK_MOUT_SCLK_MMC2_B ,"mout_sclk_mmc2_b" , mout_sclk_mmc2_b_p, MUX_SEL_TOP_FSYS0, 28, 1),
@@ -307,6 +351,16 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {MUX (CLK_MOUT_SCLK_MMC0_A ,"mout_sclk_mmc0_a" , mout_bus_pll_user_t_p,MUX_SEL_TOP_FSYS0 ,0 ,1 ), +/* MUX_SEL_TOP_FSYS1 */ +MUX (CLK_MOUT_SCLK_PCIE_100 ,"mout_sclk_pcie_100" , mout_bus_pll_user_t_p, +MUX_SEL_TOP_FSYS1 ,12 ,1 ), +MUX (CLK_MOUT_SCLK_UFSUNIPRO ,"mout_sclk_ufsunipro" , + mout_mphy_pll_user_t_p,MUX_SEL_TOP_FSYS1 ,8 ,1 ), +MUX (CLK_MOUT_SCLK_USBHOST30 ,"mout_sclk_usbhost30" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_FSYS1 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_USBDRD30 ,"mout_sclk_usbdrd30" , + mout_bus_pll_user_t_p,MUX_SEL_TOP_FSYS1 ,0 ,1 ), +/* MUX_SEL_TOP_PERIC0 */ MUX (CLK_MOUT_SCLK_SPI4 ,"mout_sclk_spi4" , mout_bus_pll_user_t_p, MUX_SEL_TOP_PERIC0, 28, 1),
@@ -324,6 +378,16 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = { MUX_SEL_TOP_PERIC0, 4, 1),MUX (CLK_MOUT_SCLK_SPI0 ,"mout_sclk_spi0" , mout_bus_pll_user_t_p,MUX_SEL_TOP_PERIC0 ,0 ,1 ), + +/* MUX_SEL_TOP_PERIC1 */ +MUX (CLK_MOUT_SCLK_SLIMBUS ,"mout_sclk_slimbus" , mout_aud_pll_user_p, +MUX_SEL_TOP_PERIC1 ,16 ,1 ), +MUX (CLK_MOUT_SCLK_SPDIF ,"mout_sclk_spdif" , mout_sclk_spdif_p, +MUX_SEL_TOP_PERIC1 ,12 ,2 ), +MUX (CLK_MOUT_SCLK_AUDIO1 ,"mout_sclk_audio1" , mout_sclk_audio1_p, +MUX_SEL_TOP_PERIC1 ,4 ,2 ), +MUX (CLK_MOUT_SCLK_AUDIO0 ,"mout_sclk_audio0" , mout_sclk_audio0_p, + MUX_SEL_TOP_PERIC1, 0, 2), }; static struct samsung_div_clock top_div_clks[] __initdata = {
@@ -387,6 +451,16 @@ static struct samsung_div_clock top_div_clks[] __initdata = {DIV (CLK_DIV_SCLK_UART0 ,"div_sclk_uart0" ,"mout_sclk_uart1" ,DIV_TOP_PERIC2 ,0 ,4 ), +/* DIV_TOP_PERIC3 */ +DIV (CLK_DIV_SCLK_I2S1 ,"div_sclk_i2s1" ,"sclk_audio1" , +DIV_TOP_PERIC3 ,16 ,6 ), +DIV (CLK_DIV_SCLK_PCM1 ,"div_sclk_pcm1" ,"sclk_audio1" , +DIV_TOP_PERIC3 ,8 ,8 ), +DIV (CLK_DIV_SCLK_AUDIO1 ,"div_sclk_audio1" ,"mout_sclk_audio1" , +DIV_TOP_PERIC3 ,4 ,4 ), +DIV (CLK_DIV_SCLK_AUDIO0 ,"div_sclk_audio0" ,"mout_sclk_audio0" , +DIV_TOP_PERIC3 ,0 ,4 ), +/* DIV_TOP_PERIC4 */ DIV (CLK_DIV_SCLK_SPI4_B ,"div_sclk_spi4_b" ,"div_sclk_spi4_a" , DIV_TOP_PERIC4, 16, 8),
@@ -420,6 +494,12 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),GATE (CLK_SCLK_SPI3_PERIC ,"sclk_spi3_peric" ,"div_sclk_spi3_b" ,ENABLE_SCLK_TOP_PERIC ,11 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_SPDIF_PERIC ,"sclk_spdif_peric" ,"mout_sclk_spdif" , +ENABLE_SCLK_TOP_PERIC ,9 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_I2S1_PERIC ,"sclk_i2s1_peric" ,"div_sclk_i2s1" , +ENABLE_SCLK_TOP_PERIC ,8 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_PCM1_PERIC ,"sclk_pcm1_peric" ,"div_sclk_pcm1" , +ENABLE_SCLK_TOP_PERIC ,7 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_UART2_PERIC ,"sclk_uart2_peric" ,"div_sclk_uart2" ,ENABLE_SCLK_TOP_PERIC ,5 ,0 ,0 ), GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
@@ -432,6 +512,14 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),GATE (CLK_SCLK_SPI0_PERIC ,"sclk_spi0_peric" ,"div_sclk_spi0_b" ,ENABLE_SCLK_TOP_PERIC ,0 ,CLK_SET_RATE_PARENT ,0 ), + +/* MUX_ENABLE_TOP_PERIC1 */ +GATE (CLK_SCLK_SLIMBUS ,"sclk_slimbus" ,"mout_sclk_slimbus" , +MUX_ENABLE_TOP_PERIC1 ,16 ,0 ,0 ), +GATE (CLK_SCLK_AUDIO1 ,"sclk_audio1" ,"div_sclk_audio1" , +MUX_ENABLE_TOP_PERIC1 ,4 ,0 ,0 ), +GATE (CLK_SCLK_AUDIO0 ,"sclk_audio0" ,"div_sclk_audio0" , + MUX_ENABLE_TOP_PERIC1, 0, 0, 0), };/*
@@ -518,6 +606,8 @@ static struct samsung_cmu_info top_cmu_info __initdata = { .nr_div_clks = ARRAY_SIZE(top_div_clks), .gate_clks = top_gate_clks, .nr_gate_clks = ARRAY_SIZE(top_gate_clks), + .fixed_clks = top_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), .fixed_factor_clks = top_fixed_factor_clks, .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), .nr_clk_ids = TOP_NR_CLK,
include/dt-bindings/clock/exynos5433.h +29 -2
@@ -51,6 +51,23 @@#define CLK_MOUT_SCLK_SPI2 44#define CLK_MOUT_SCLK_SPI1 45#define CLK_MOUT_SCLK_SPI0 46 +#define CLK_MOUT_ACLK_MFC_400_C 47 +#define CLK_MOUT_ACLK_MFC_400_B 48 +#define CLK_MOUT_ACLK_MFC_400_A 49 +#define CLK_MOUT_SCLK_ISP_SENSOR2 50 +#define CLK_MOUT_SCLK_ISP_SENSOR1 51 +#define CLK_MOUT_SCLK_ISP_SENSOR0 52 +#define CLK_MOUT_SCLK_ISP_UART 53 +#define CLK_MOUT_SCLK_ISP_SPI1 54 +#define CLK_MOUT_SCLK_ISP_SPI0 55 +#define CLK_MOUT_SCLK_PCIE_100 56 +#define CLK_MOUT_SCLK_UFSUNIPRO 57 +#define CLK_MOUT_SCLK_USBHOST30 58 +#define CLK_MOUT_SCLK_USBDRD30 59 +#define CLK_MOUT_SCLK_SLIMBUS 60 +#define CLK_MOUT_SCLK_SPDIF 61 +#define CLK_MOUT_SCLK_AUDIO1 62 +#define CLK_MOUT_SCLK_AUDIO0 63#define CLK_DIV_ACLK_FSYS_200 100#define CLK_DIV_ACLK_IMEM_SSSX 101
@@ -79,6 +96,10 @@#define CLK_DIV_SCLK_SPI4_A 124#define CLK_DIV_SCLK_SPI3_B 125#define CLK_DIV_SCLK_SPI3_A 126 +#define CLK_DIV_SCLK_I2S1 127 +#define CLK_DIV_SCLK_PCM1 128 +#define CLK_DIV_SCLK_AUDIO1 129 +#define CLK_DIV_SCLK_AUDIO0 130#define CLK_ACLK_PERIC_66 200#define CLK_ACLK_PERIS_66 201
@@ -94,8 +115,14 @@#define CLK_SCLK_SPI2_PERIC 211#define CLK_SCLK_SPI1_PERIC 212#define CLK_SCLK_SPI0_PERIC 213 - -#define TOP_NR_CLK 214 +#define CLK_SCLK_SPDIF_PERIC 214 +#define CLK_SCLK_I2S1_PERIC 215 +#define CLK_SCLK_PCM1_PERIC 216 +#define CLK_SCLK_SLIMBUS 217 +#define CLK_SCLK_AUDIO1 218 +#define CLK_SCLK_AUDIO0 219 + +#define TOP_NR_CLK 220/* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1
Signature · 1 line
1.8.5.5
Re: [PATCH 02/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
Hi Chanwoo,
Quoted 9 lines · Chanwoo Choi
This patch adds the MUX (multiplexer) clocks for
CMU_TOPdomain of Exynos5433.CMU_TOPdomain provides source clocks to other CMU domains.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>---
Reviewed all registers and clock relationships w.r.t UM I have and all changes are OK. So
Reviewed-by Pankaj Dubey <[email protected]>
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerRe: [PATCH 02/19] clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
Hi Pankaj,
Quoted 13 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 9 lines · Chanwoo Choi
This patch adds the MUX (multiplexer) clocks for
CMU_TOPdomain of Exynos5433.CMU_TOPdomain provides source clocks to other CMU domains.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>---
Quoted 3 lines
Reviewed all registers and clock relationships w.r.t UM I have and all changes are OK. So
Reviewed-by Pankaj Dubey <[email protected]>
Thanks for your review.
Best Regards,
Chanwoo Choi
Chanwoo Choi
maintainerPATCH v2 3/19 clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
In reply to Chanwoo ChoiThis patch adds missing divider/gate clocks of CMU_PERIC domain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]
Signed-off-by Inha Song <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++- 2 files changed, 112 insertions(+), 2 deletions(-)
drivers/clk/samsung/clk-exynos5433.c +79 -1
@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {FRATE (0 ,"ioclk_audiocdclk0" ,NULL ,CLK_IS_ROOT ,100000000 ),/* Xi2s1SDI input clock for SPDIF */ FRATE (0 ,"ioclk_spdif_extclk" ,NULL ,CLK_IS_ROOT ,100000000 ), +/* XspiCLK[4:0] input clock for SPI */ +FRATE (0 ,"ioclk_spi4_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi3_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi2_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi1_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi0_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +/* Xi2s1SCLK input clock for I2S1_BCLK */ + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), }; static struct samsung_mux_clock top_mux_clks[] __initdata = {
@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",* Register offset definitions for CMU_PERIC */ #define DIV_PERIC 0x0600 +#define DIV_STAT_PERIC 0x0700#define ENABLE_ACLK_PERIC 0x0800#define ENABLE_PCLK_PERIC0 0x0900#define ENABLE_PCLK_PERIC1 0x0904
@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",static unsigned long peric_clk_regs[]__initdata = {DIV_PERIC , +DIV_STAT_PERIC ,ENABLE_ACLK_PERIC ,ENABLE_PCLK_PERIC0 ,ENABLE_PCLK_PERIC1 ,
@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = { ENABLE_IP_PERIC2, }; +static struct samsung_div_clock peric_div_clks[]__initdata = { +/* DIV_PERIC */ +DIV (CLK_DIV_SCLK_SCI ,"div_sclk_sci" ,"fin_pll" ,DIV_PERIC ,4 ,8 ), +DIV (CLK_DIV_SCLK_SC_IN ,"div_sclk_sc_in" ,"fin_pll" ,DIV_PERIC ,0 ,4 ), +}; +static struct samsung_gate_clock peric_gate_clks[]__initdata = { +/* ENABLE_ACLK_PERIC */ +GATE (CLK_ACLK_AHB2APB_PERIC2P ,"aclk_ahb2apb_peric2p" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_PERIC1P ,"aclk_ahb2apb_peric1p" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_PERIC0P ,"aclk_ahb2apb_peric0p" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_PERICNP_66 ,"aclk_pericnp_66" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,0 ,CLK_IGNORE_UNUSED ,0 ), +/* ENABLE_PCLK_PERIC0 */ +GATE (CLK_PCLK_SCI ,"pclk_sci" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +31 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_GPIO_FINGER ,"pclk_gpio_finger" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,30 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_GPIO_ESE ,"pclk_gpio_ese" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,29 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_PWM ,"pclk_pwm" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +28 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_SPDIF ,"pclk_spdif" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +26 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_PCM1 ,"pclk_pcm1" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +25 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_I2S1 ,"pclk_i2s" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +24 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_PCLK_SPI2 ,"pclk_spi2" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,23 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_PCLK_SPI1 ,"pclk_spi1" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,22 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_PCLK_SPI0 ,"pclk_spi0" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,21 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_ADCIF ,"pclk_adcif" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +20 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_GPIO_TOUCH ,"pclk_gpio_touch" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,19 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_GPIO_NFC ,"pclk_gpio_nfc" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,18 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_GPIO_PERIC ,"pclk_gpio_peric" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,17 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_PMU_PERIC ,"pclk_pmu_peric" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,16 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_SYSREG_PERIC ,"pclk_sysreg_peric" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,15 , +CLK_SET_RATE_PARENT |CLK_IGNORE_UNUSED ,0 ),GATE (CLK_PCLK_UART2 ,"pclk_uart2" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,14 ,CLK_SET_RATE_PARENT ,0 ), GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
@@ -841,11 +894,34 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),/* ENABLE_SCLK_PERIC */ +GATE (CLK_SCLK_IOCLK_SPI4 ,"sclk_ioclk_spi4" ,"ioclk_spi4_clk_in" , +ENABLE_SCLK_PERIC ,21 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_SPI3 ,"sclk_ioclk_spi3" ,"ioclk_spi3_clk_in" , +ENABLE_SCLK_PERIC ,20 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_SPI4 ,"sclk_spi4" ,"sclk_spi4_peric" ,ENABLE_SCLK_PERIC ,19 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_SPI3 ,"sclk_spi3" ,"sclk_spi3_peric" ,ENABLE_SCLK_PERIC ,18 ,CLK_SET_RATE_PARENT ,0 ), - +GATE (CLK_SCLK_SCI ,"sclk_sci" ,"div_sclk_sci" ,ENABLE_SCLK_PERIC , +17 ,0 ,0 ), +GATE (CLK_SCLK_SC_IN ,"sclk_sc_in" ,"div_sclk_sc_in" ,ENABLE_SCLK_PERIC , +16 ,0 ,0 ), +GATE (CLK_SCLK_PWM ,"sclk_pwm" ,"fin_pll" ,ENABLE_SCLK_PERIC ,15 ,0 ,0 ), +GATE (CLK_SCLK_IOCLK_SPI2 ,"sclk_ioclk_spi2" ,"ioclk_spi2_clk_in" , +ENABLE_SCLK_PERIC ,13 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_SPI1 ,"sclk_ioclk_spi1" ,"ioclk_spi1_clk_in" , +ENABLE_SCLK_PERIC ,12 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_SPI0 ,"sclk_ioclk_spi0" ,"ioclk_spi0_clk_in" , +ENABLE_SCLK_PERIC ,11 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_I2S1_BCLK ,"sclk_ioclk_i2s1_bclk" , +"ioclk_i2s1_bclk_in" ,ENABLE_SCLK_PERIC ,10 , +CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_SPDIF ,"sclk_spdif" ,"sclk_spdif_peric" , +ENABLE_SCLK_PERIC ,8 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_PCM1 ,"sclk_pcm1" ,"sclk_pcm1_peric" , +ENABLE_SCLK_PERIC ,7 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_I2S1 ,"sclk_i2s1" ,"sclk_i2s1_peric" , +ENABLE_SCLK_PERIC ,6 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_SPI2 ,"sclk_spi2" ,"sclk_spi2_peric" ,ENABLE_SCLK_PERIC ,5 ,CLK_SET_RATE_PARENT ,0 ), GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
@@ -861,6 +937,8 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { };static struct samsung_cmu_info peric_cmu_info__initdata = { + .div_clks = peric_div_clks, + .nr_div_clks =ARRAY_SIZE (peric_div_clks), .gate_clks = peric_gate_clks, .nr_gate_clks =ARRAY_SIZE (peric_gate_clks), .nr_clk_ids =PERIC_NR_CLK ,
include/dt-bindings/clock/exynos5433.h +33 -1
@@ -181,8 +181,40 @@#define CLK_SCLK_UART2 34#define CLK_SCLK_UART1 35#define CLK_SCLK_UART0 36 +#define CLK_ACLK_AHB2APB_PERIC2P 37 +#define CLK_ACLK_AHB2APB_PERIC1P 38 +#define CLK_ACLK_AHB2APB_PERIC0P 39 +#define CLK_ACLK_PERICNP_66 40 +#define CLK_PCLK_SCI 41 +#define CLK_PCLK_GPIO_FINGER 42 +#define CLK_PCLK_GPIO_ESE 43 +#define CLK_PCLK_PWM 44 +#define CLK_PCLK_SPDIF 45 +#define CLK_PCLK_PCM1 46 +#define CLK_PCLK_I2S1 47 +#define CLK_PCLK_ADCIF 48 +#define CLK_PCLK_GPIO_TOUCH 49 +#define CLK_PCLK_GPIO_NFC 50 +#define CLK_PCLK_GPIO_PERIC 51 +#define CLK_PCLK_PMU_PERIC 52 +#define CLK_PCLK_SYSREG_PERIC 53 +#define CLK_SCLK_IOCLK_SPI4 54 +#define CLK_SCLK_IOCLK_SPI3 55 +#define CLK_SCLK_SCI 56 +#define CLK_SCLK_SC_IN 57 +#define CLK_SCLK_PWM 58 +#define CLK_SCLK_IOCLK_SPI2 59 +#define CLK_SCLK_IOCLK_SPI1 60 +#define CLK_SCLK_IOCLK_SPI0 61 +#define CLK_SCLK_IOCLK_I2S1_BCLK 62 +#define CLK_SCLK_SPDIF 63 +#define CLK_SCLK_PCM1 64 +#define CLK_SCLK_I2S1 65 -#define PERIC_NR_CLK 37 +#define CLK_DIV_SCLK_SCI 70 +#define CLK_DIV_SCLK_SC_IN 71 + +#define PERIC_NR_CLK 72/* CMU_PERIS */ #define CLK_PCLK_HPM_APBIF 1
Signature · 1 line
1.8.5.5
Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
Hi Chanwoo,
Quoted 44 lines · Chanwoo Choi
This patch adds missing divider/gate clocks of
CMU_PERICdomain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]Signed-off-by Inha Song <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++- 2 files changed, 112 insertions(+), 2 deletions(-)drivers/clk/samsung/clk-exynos5433.c +9
-0@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {FRATE (0 ,"ioclk_audiocdclk0" ,NULL ,CLK_IS_ROOT ,100000000 ),/* Xi2s1SDI input clock for SPDIF */ FRATE (0 ,"ioclk_spdif_extclk" ,NULL ,CLK_IS_ROOT ,100000000 ), +/* XspiCLK[4:0] input clock for SPI */ +FRATE (0 ,"ioclk_spi4_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi3_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi2_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi1_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi0_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +/* Xi2s1SCLK input clock for I2S1_BCLK */ + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), }; static struct samsung_mux_clock top_mux_clks[] __initdata = {@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",* Register offset definitions for CMU_PERIC */ #define DIV_PERIC 0x0600 +#define DIV_STAT_PERIC 0x0700#define ENABLE_ACLK_PERIC 0x0800#define ENABLE_PCLK_PERIC0 0x0900#define ENABLE_PCLK_PERIC1 0x0904
drivers/clk/samsung/clk-exynos5433.c CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", · line 782
Quoted 4 lines
drivers/clk/samsung/clk-exynos5433.c +1
-0@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",static unsigned long peric_clk_regs[]__initdata = {DIV_PERIC , +DIV_STAT_PERIC ,
IMO, this line should have been added in first place itself when you added peric_clk_regs.
drivers/clk/samsung/clk-exynos5433.c static unsigned long peric_clk_regs[] __initdata = { · line 794
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +3
-0ENABLE_ACLK_PERIC ,ENABLE_PCLK_PERIC0 , ENABLE_PCLK_PERIC1,@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = { ENABLE_IP_PERIC2, }; +static struct samsung_div_clock peric_div_clks[]__initdata = { +/* DIV_PERIC */ +DIV (CLK_DIV_SCLK_SCI ,"div_sclk_sci" ,"fin_pll" ,DIV_PERIC ,4 ,8 ),
As per UM I have DIV_SCLK_SCI has 4 bit wide as [7:4] please cross verify.
Quoted 133 lines
drivers/clk/samsung/clk-exynos5433.c +66
-1+ DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "fin_pll", DIV_PERIC, 0, 4), +}; +static struct samsung_gate_clock peric_gate_clks[]__initdata = { +/* ENABLE_ACLK_PERIC */ +GATE (CLK_ACLK_AHB2APB_PERIC2P ,"aclk_ahb2apb_peric2p" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_PERIC1P ,"aclk_ahb2apb_peric1p" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_PERIC0P ,"aclk_ahb2apb_peric0p" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_PERICNP_66 ,"aclk_pericnp_66" ,"aclk_peric_66" , +ENABLE_ACLK_PERIC ,0 ,CLK_IGNORE_UNUSED ,0 ), +/* ENABLE_PCLK_PERIC0 */ +GATE (CLK_PCLK_SCI ,"pclk_sci" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +31 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_GPIO_FINGER ,"pclk_gpio_finger" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,30 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_GPIO_ESE ,"pclk_gpio_ese" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,29 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_PWM ,"pclk_pwm" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +28 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_SPDIF ,"pclk_spdif" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +26 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_PCM1 ,"pclk_pcm1" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +25 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_I2S1 ,"pclk_i2s" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +24 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_PCLK_SPI2 ,"pclk_spi2" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,23 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_PCLK_SPI1 ,"pclk_spi1" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,22 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_PCLK_SPI0 ,"pclk_spi0" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,21 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_ADCIF ,"pclk_adcif" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 , +20 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_GPIO_TOUCH ,"pclk_gpio_touch" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,19 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_GPIO_NFC ,"pclk_gpio_nfc" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,18 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_GPIO_PERIC ,"pclk_gpio_peric" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,17 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_PMU_PERIC ,"pclk_pmu_peric" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,16 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_PCLK_SYSREG_PERIC ,"pclk_sysreg_peric" ,"aclk_peric_66" , +ENABLE_PCLK_PERIC0 ,15 , +CLK_SET_RATE_PARENT |CLK_IGNORE_UNUSED ,0 ),GATE (CLK_PCLK_UART2 ,"pclk_uart2" ,"aclk_peric_66" ,ENABLE_PCLK_PERIC0 ,14 ,CLK_SET_RATE_PARENT ,0 ), GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,@@ -841,11 +894,34 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),/* ENABLE_SCLK_PERIC */ +GATE (CLK_SCLK_IOCLK_SPI4 ,"sclk_ioclk_spi4" ,"ioclk_spi4_clk_in" , +ENABLE_SCLK_PERIC ,21 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_SPI3 ,"sclk_ioclk_spi3" ,"ioclk_spi3_clk_in" , +ENABLE_SCLK_PERIC ,20 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_SPI4 ,"sclk_spi4" ,"sclk_spi4_peric" ,ENABLE_SCLK_PERIC ,19 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_SPI3 ,"sclk_spi3" ,"sclk_spi3_peric" ,ENABLE_SCLK_PERIC ,18 ,CLK_SET_RATE_PARENT ,0 ), - +GATE (CLK_SCLK_SCI ,"sclk_sci" ,"div_sclk_sci" ,ENABLE_SCLK_PERIC , +17 ,0 ,0 ), +GATE (CLK_SCLK_SC_IN ,"sclk_sc_in" ,"div_sclk_sc_in" ,ENABLE_SCLK_PERIC , +16 ,0 ,0 ), +GATE (CLK_SCLK_PWM ,"sclk_pwm" ,"fin_pll" ,ENABLE_SCLK_PERIC ,15 ,0 ,0 ), +GATE (CLK_SCLK_IOCLK_SPI2 ,"sclk_ioclk_spi2" ,"ioclk_spi2_clk_in" , +ENABLE_SCLK_PERIC ,13 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_SPI1 ,"sclk_ioclk_spi1" ,"ioclk_spi1_clk_in" , +ENABLE_SCLK_PERIC ,12 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_SPI0 ,"sclk_ioclk_spi0" ,"ioclk_spi0_clk_in" , +ENABLE_SCLK_PERIC ,11 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_IOCLK_I2S1_BCLK ,"sclk_ioclk_i2s1_bclk" , +"ioclk_i2s1_bclk_in" ,ENABLE_SCLK_PERIC ,10 , +CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_SPDIF ,"sclk_spdif" ,"sclk_spdif_peric" , +ENABLE_SCLK_PERIC ,8 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_PCM1 ,"sclk_pcm1" ,"sclk_pcm1_peric" , +ENABLE_SCLK_PERIC ,7 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_I2S1 ,"sclk_i2s1" ,"sclk_i2s1_peric" , +ENABLE_SCLK_PERIC ,6 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_SPI2 ,"sclk_spi2" ,"sclk_spi2_peric" ,ENABLE_SCLK_PERIC ,5 ,CLK_SET_RATE_PARENT ,0 ), GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,@@ -861,6 +937,8 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { };static struct samsung_cmu_info peric_cmu_info__initdata = { + .div_clks = peric_div_clks, + .nr_div_clks =ARRAY_SIZE (peric_div_clks), .gate_clks = peric_gate_clks, .nr_gate_clks =ARRAY_SIZE (peric_gate_clks), .nr_clk_ids =PERIC_NR_CLK ,include/dt-bindings/clock/exynos5433.h +28
-0@@ -181,8 +181,40 @@#define CLK_SCLK_UART2 34#define CLK_SCLK_UART1 35#define CLK_SCLK_UART0 36 +#define CLK_ACLK_AHB2APB_PERIC2P 37 +#define CLK_ACLK_AHB2APB_PERIC1P 38 +#define CLK_ACLK_AHB2APB_PERIC0P 39 +#define CLK_ACLK_PERICNP_66 40 +#define CLK_PCLK_SCI 41 +#define CLK_PCLK_GPIO_FINGER 42 +#define CLK_PCLK_GPIO_ESE 43 +#define CLK_PCLK_PWM 44 +#define CLK_PCLK_SPDIF 45 +#define CLK_PCLK_PCM1 46 +#define CLK_PCLK_I2S1 47 +#define CLK_PCLK_ADCIF 48 +#define CLK_PCLK_GPIO_TOUCH 49 +#define CLK_PCLK_GPIO_NFC 50 +#define CLK_PCLK_GPIO_PERIC 51 +#define CLK_PCLK_PMU_PERIC 52 +#define CLK_PCLK_SYSREG_PERIC 53 +#define CLK_SCLK_IOCLK_SPI4 54 +#define CLK_SCLK_IOCLK_SPI3 55 +#define CLK_SCLK_SCI 56 +#define CLK_SCLK_SC_IN 57 +#define CLK_SCLK_PWM 58 +#define CLK_SCLK_IOCLK_SPI2 59 +#define CLK_SCLK_IOCLK_SPI1 60 +#define CLK_SCLK_IOCLK_SPI0 61 +#define CLK_SCLK_IOCLK_I2S1_BCLK 62 +#define CLK_SCLK_SPDIF 63 +#define CLK_SCLK_PCM1 64
include/dt-bindings/clock/exynos5433.h line 220
Quoted 10 lines
include/dt-bindings/clock/exynos5433.h +5
-1+#define CLK_SCLK_I2S1 65 -#define PERIC_NR_CLK 37 +#define CLK_DIV_SCLK_SCI 70 +#define CLK_DIV_SCLK_SC_IN 71 + +#define PERIC_NR_CLK 72/* CMU_PERIS */ #define CLK_PCLK_HPM_APBIF 1
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerRe: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
Hi Pankaj,
Quoted 48 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 45 lines · Chanwoo Choi
This patch adds missing divider/gate clocks of
CMU_PERICdomain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]Signed-off-by Inha Song <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++- 2 files changed, 112 insertions(+), 2 deletions(-)drivers/clk/samsung/clk-exynos5433.c +9
-0@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {FRATE (0 ,"ioclk_audiocdclk0" ,NULL ,CLK_IS_ROOT ,100000000 ),/* Xi2s1SDI input clock for SPDIF */ FRATE (0 ,"ioclk_spdif_extclk" ,NULL ,CLK_IS_ROOT ,100000000 ), +/* XspiCLK[4:0] input clock for SPI */ +FRATE (0 ,"ioclk_spi4_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi3_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi2_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi1_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi0_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +/* Xi2s1SCLK input clock for I2S1_BCLK */ + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), }; static struct samsung_mux_clock top_mux_clks[] __initdata = {@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",* Register offset definitions for CMU_PERIC */ #define DIV_PERIC 0x0600 +#define DIV_STAT_PERIC 0x0700#define ENABLE_ACLK_PERIC 0x0800#define ENABLE_PCLK_PERIC0 0x0900#define ENABLE_PCLK_PERIC1 0x0904@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", · line 782
Quoted 3 lines
drivers/clk/samsung/clk-exynos5433.c +1
-0static unsigned long peric_clk_regs[]__initdata = {DIV_PERIC , +DIV_STAT_PERIC ,IMO, this line should have been added in first place itself when you added
peric_clk_regs.
Why? I want to locate it according to address base.
Quoted 8 lines
Quoted 8 lines
drivers/clk/samsung/clk-exynos5433.c +0
-0ENABLE_ACLK_PERIC ,ENABLE_PCLK_PERIC0 , ENABLE_PCLK_PERIC1,@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = { ENABLE_IP_PERIC2, };
Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c static unsigned long peric_clk_regs[] __initdata = { · line 794
Quoted 3 lines
drivers/clk/samsung/clk-exynos5433.c +3
-0+static struct samsung_div_clock peric_div_clks[]__initdata = { +/* DIV_PERIC */ +DIV (CLK_DIV_SCLK_SCI ,"div_sclk_sci" ,"fin_pll" ,DIV_PERIC ,4 ,8 ),As per UM I have
DIV_SCLK_SCIhas 4 bit wide as [7:4] please cross verify.
You're right. It is my mistake. I'll fix it.
Best Regards,
Chanwoo Choi
Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
Quoted 51 lines · Chanwoo Choi
Hi Pankaj,
Quoted 48 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 45 lines · Chanwoo Choi
This patch adds missing divider/gate clocks of
CMU_PERICdomain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]Signed-off-by Inha Song <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++- 2 files changed, 112 insertions(+), 2 deletions(-)drivers/clk/samsung/clk-exynos5433.c +9
-0@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {FRATE (0 ,"ioclk_audiocdclk0" ,NULL ,CLK_IS_ROOT ,100000000 ),/* Xi2s1SDI input clock for SPDIF */ FRATE (0 ,"ioclk_spdif_extclk" ,NULL ,CLK_IS_ROOT ,100000000 ), +/* XspiCLK[4:0] input clock for SPI */ +FRATE (0 ,"ioclk_spi4_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi3_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi2_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi1_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi0_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +/* Xi2s1SCLK input clock for I2S1_BCLK */ + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), }; static struct samsung_mux_clock top_mux_clks[] __initdata = {@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",* Register offset definitions for CMU_PERIC */ #define DIV_PERIC 0x0600 +#define DIV_STAT_PERIC 0x0700#define ENABLE_ACLK_PERIC 0x0800#define ENABLE_PCLK_PERIC0 0x0900#define ENABLE_PCLK_PERIC1 0x0904@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
Quoted 7 lines
Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", · line 782
Quoted 3 lines
drivers/clk/samsung/clk-exynos5433.c +1
-0static unsigned long peric_clk_regs[]__initdata = {DIV_PERIC , +DIV_STAT_PERIC ,IMO, this line should have been added in first place itself when you added
peric_clk_regs.Why? I want to locate it according to address base.
Since DIV_PERIC and DIV_STAT_PERIC both has same address base, why not to add DIV_STAT_PERIC at the same place when you added DIV_PERIC?
Anyways, this was just my opinion as I don't see any dependency why we should add it here? I left this up to you.
Quoted 15 lines
Quoted 9 lines
Quoted 9 lines
drivers/clk/samsung/clk-exynos5433.c +0
-0ENABLE_ACLK_PERIC ,ENABLE_PCLK_PERIC0 , ENABLE_PCLK_PERIC1,@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = { ENABLE_IP_PERIC2, };Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c static unsigned long peric_clk_regs[] __initdata = { · line 794
Quoted 3 lines
drivers/clk/samsung/clk-exynos5433.c +3
-0+static struct samsung_div_clock peric_div_clks[]__initdata = { +/* DIV_PERIC */ +DIV (CLK_DIV_SCLK_SCI ,"div_sclk_sci" ,"fin_pll" ,DIV_PERIC ,4 ,8 ),As per UM I have
DIV_SCLK_SCIhas 4 bit wide as [7:4] please cross verify.
Quoted 5 lines
You're right. It is my mistake. I'll fix it.
Best Regards,
Chanwoo Choi
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerRe: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
Quoted 60 lines · Pankaj Dubey
Quoted 57 lines · Chanwoo Choi
Hi Pankaj,
Quoted 53 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 44 lines · Chanwoo Choi
This patch adds missing divider/gate clocks of
CMU_PERICdomain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]Signed-off-by Inha Song <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++- 2 files changed, 112 insertions(+), 2 deletions(-)drivers/clk/samsung/clk-exynos5433.c +9
-0@@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {FRATE (0 ,"ioclk_audiocdclk0" ,NULL ,CLK_IS_ROOT ,100000000 ),/* Xi2s1SDI input clock for SPDIF */ FRATE (0 ,"ioclk_spdif_extclk" ,NULL ,CLK_IS_ROOT ,100000000 ), +/* XspiCLK[4:0] input clock for SPI */ +FRATE (0 ,"ioclk_spi4_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi3_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi2_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi1_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +FRATE (0 ,"ioclk_spi0_clk_in" ,NULL ,CLK_IS_ROOT ,50000000 ), +/* Xi2s1SCLK input clock for I2S1_BCLK */ + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), }; static struct samsung_mux_clock top_mux_clks[] __initdata = {@@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",* Register offset definitions for CMU_PERIC */ #define DIV_PERIC 0x0600 +#define DIV_STAT_PERIC 0x0700#define ENABLE_ACLK_PERIC 0x0800#define ENABLE_PCLK_PERIC0 0x0900#define ENABLE_PCLK_PERIC1 0x0904drivers/clk/samsung/clk-exynos5433.c CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", · line 782
Quoted 4 lines
drivers/clk/samsung/clk-exynos5433.c +1
-0@@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",static unsigned long peric_clk_regs[]__initdata = {DIV_PERIC , +DIV_STAT_PERIC ,IMO, this line should have been added in first place itself when you added
peric_clk_regs.
Quoted 3 lines
Quoted 1 line
Why? I want to locate it according to address base.
Since
DIV_PERICandDIV_STAT_PERICboth has same address base, why not to addDIV_STAT_PERICat the same place when you addedDIV_PERIC?
I mean the register offset instead of address base. DIV_PERIC(0x0600) is less than DIV_STAT_PERIC(0x0700).
So, I want to locate DIV_STAT_PERIC on behind DIV_PERIC in ascending order.
But, It is just minor issue.
Best Regards,
Chanwoo Choi
Quoted 26 lines
Anyways, this was just my opinion as I don't see any dependency why we should add it here? I left this up to you.
Quoted 15 lines
Quoted 9 lines
Quoted 9 lines
drivers/clk/samsung/clk-exynos5433.c +0
-0ENABLE_ACLK_PERIC ,ENABLE_PCLK_PERIC0 , ENABLE_PCLK_PERIC1,@@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = { ENABLE_IP_PERIC2, };Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c static unsigned long peric_clk_regs[] __initdata = { · line 794
Quoted 3 lines
drivers/clk/samsung/clk-exynos5433.c +3
-0+static struct samsung_div_clock peric_div_clks[]__initdata = { +/* DIV_PERIC */ +DIV (CLK_DIV_SCLK_SCI ,"div_sclk_sci" ,"fin_pll" ,DIV_PERIC ,4 ,8 ),As per UM I have
DIV_SCLK_SCIhas 4 bit wide as [7:4] please cross verify.Quoted 5 lines
You're right. It is my mistake. I'll fix it.
Best Regards,
Chanwoo ChoiThanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 4/19 clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
In reply to Chanwoo ChoiThis patch adds missing gate clocks of CMU_PERIS domain which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs. The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- drivers/clk/samsung/clk-exynos5433.c | 146 ++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 33 +++++++- 2 files changed, 176 insertions(+), 3 deletions(-)
drivers/clk/samsung/clk-exynos5433.c +144 -2
@@ -248,6 +248,7 @@ PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "fin_pll",static struct samsung_fixed_factor_clock top_fixed_factor_clks[]__initdata = {FFACTOR (0 ,"sclk_bus_pll" ,"fout_bus_pll" ,1 ,1 ,0 ),FFACTOR (0 ,"sclk_mfc_pll" ,"fout_mfc_pll" ,1 ,1 ,0 ), +FFACTOR (0 ,"oscclk_efuse_common" ,"fin_pll" ,1 ,1 ,0 ), };static struct samsung_fixed_rate_clock top_fixed_clks[]__initdata = {
@@ -957,15 +958,69 @@ CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",/* * Register offset definitions for CMU_PERIS */ -#define ENABLE_ACLK_PERIS 0x0800 -#define ENABLE_PCLK_PERIS 0x0900 +#define ENABLE_ACLK_PERIS 0x0800 +#define ENABLE_PCLK_PERIS 0x0900 +#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 +#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 +#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c +#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 +#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 +#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 +#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c +#define ENABLE_SCLK_PERIS 0x0a00 +#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 +#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 +#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c +#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 +#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 +#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 +#define ENABLE_IP_PERIS0 0x0b00 +#define ENABLE_IP_PERIS1 0x0b04 +#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 +#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c +#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 +#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 +#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 +#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c +#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20static unsigned long peris_clk_regs[]__initdata = {ENABLE_ACLK_PERIS ,ENABLE_PCLK_PERIS , +ENABLE_PCLK_PERIS_SECURE_TZPC , +ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF , +ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF , +ENABLE_PCLK_PERIS_SECURE_TOPRTC , +ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF , +ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF , +ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF , +ENABLE_SCLK_PERIS , +ENABLE_SCLK_PERIS_SECURE_SECKEY , +ENABLE_SCLK_PERIS_SECURE_CHIPID , +ENABLE_SCLK_PERIS_SECURE_TOPRTC , +ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE , +ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT , +ENABLE_SCLK_PERIS_SECURE_OTP_CON , +ENABLE_IP_PERIS0 , +ENABLE_IP_PERIS1 , +ENABLE_IP_PERIS_SECURE_TZPC , +ENABLE_IP_PERIS_SECURE_SECKEY , +ENABLE_IP_PERIS_SECURE_CHIPID , +ENABLE_IP_PERIS_SECURE_TOPRTC , +ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE , +ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT , +ENABLE_IP_PERIS_SECURE_OTP_CON , };static struct samsung_gate_clock peris_gate_clks[]__initdata = { +/* ENABLE_ACLK_PERIS */ +GATE (CLK_ACLK_AHB2APB_PERIS1P ,"aclk_ahb2apb_peris1p" ,"aclk_peris_66" , +ENABLE_ACLK_PERIS ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_PERIS0P ,"aclk_ahb2apb_peris0p" ,"aclk_peris_66" , +ENABLE_ACLK_PERIS ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_PERISNP_66 ,"aclk_perisnp_66" ,"aclk_peris_66" , +ENABLE_ACLK_PERIS ,0 ,CLK_IGNORE_UNUSED ,0 ), +/* ENABLE_PCLK_PERIS */ GATE (CLK_PCLK_HPM_APBIF ,"pclk_hpm_apbif" ,"aclk_peris_66" ,ENABLE_PCLK_PERIS ,30 ,CLK_IGNORE_UNUSED ,0 ),
@@ -987,6 +1042,93 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = { ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),GATE (CLK_PCLK_HDMI_CEC ,"pclk_hdmi_cec" ,"aclk_peris_66" ,ENABLE_PCLK_PERIS ,14 ,CLK_IGNORE_UNUSED ,0 ), + +/* ENABLE_PCLK_PERIS_SECURE_TZPC */ +GATE (CLK_PCLK_TZPC12 ,"pclk_tzpc12" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,12 ,0 ,0 ), +GATE (CLK_PCLK_TZPC11 ,"pclk_tzpc11" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,11 ,0 ,0 ), +GATE (CLK_PCLK_TZPC10 ,"pclk_tzpc10" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,10 ,0 ,0 ), +GATE (CLK_PCLK_TZPC9 ,"pclk_tzpc9" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,9 ,0 ,0 ), +GATE (CLK_PCLK_TZPC8 ,"pclk_tzpc8" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,8 ,0 ,0 ), +GATE (CLK_PCLK_TZPC7 ,"pclk_tzpc7" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,7 ,0 ,0 ), +GATE (CLK_PCLK_TZPC6 ,"pclk_tzpc6" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,6 ,0 ,0 ), +GATE (CLK_PCLK_TZPC5 ,"pclk_tzpc5" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,5 ,0 ,0 ), +GATE (CLK_PCLK_TZPC4 ,"pclk_tzpc4" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,4 ,0 ,0 ), +GATE (CLK_PCLK_TZPC3 ,"pclk_tzpc3" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,3 ,0 ,0 ), +GATE (CLK_PCLK_TZPC2 ,"pclk_tzpc2" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,2 ,0 ,0 ), +GATE (CLK_PCLK_TZPC1 ,"pclk_tzpc1" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,1 ,0 ,0 ), +GATE (CLK_PCLK_TZPC0 ,"pclk_tzpc0" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TZPC ,0 ,0 ,0 ), + +/* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ +GATE (CLK_PCLK_SECKEY_APBIF ,"pclk_seckey_apbif" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF ,0 ,0 ,0 ), + +/* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ +GATE (CLK_PCLK_CHIPID_APBIF ,"pclk_chipid_apbif" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF ,0 ,0 ,0 ), + +/* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ +GATE (CLK_PCLK_TOPRTC ,"pclk_toprtc" ,"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_TOPRTC ,0 ,0 ,0 ), + +/* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ +GATE (CLK_PCLK_CUSTOM_EFUSE_APBIF ,"pclk_custom_efuse_apbif" , +"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF ,0 ,0 ,0 ), + +/* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ +GATE (CLK_PCLK_ANTIRBK_CNT_APBIF ,"pclk_antirbk_cnt_apbif" , +"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF ,0 ,0 ,0 ), + +/* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ +GATE (CLK_PCLK_OTP_CON_APBIF ,"pclk_otp_con_apbif" , +"aclk_peris_66" , +ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF ,0 ,0 ,0 ), + +/* ENABLE_SCLK_PERIS */ +GATE (CLK_SCLK_ASV_TB ,"sclk_asv_tb" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS ,10 ,0 ,0 ), +GATE (CLK_SCLK_TMU1 ,"sclk_tmu1" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS ,4 ,0 ,0 ), +GATE (CLK_SCLK_TMU0 ,"sclk_tmu0" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS ,3 ,0 ,0 ), + +/* ENABLE_SCLK_PERIS_SECURE_SECKEY */ +GATE (CLK_SCLK_SECKEY ,"sclk_seckey" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS_SECURE_SECKEY ,0 ,0 ,0 ), + +/* ENABLE_SCLK_PERIS_SECURE_CHIPID */ +GATE (CLK_SCLK_CHIPID ,"sclk_chipid" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS_SECURE_CHIPID ,0 ,0 ,0 ), + +/* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ +GATE (CLK_SCLK_TOPRTC ,"sclk_toprtc" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS_SECURE_TOPRTC ,0 ,0 ,0 ), + +/* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ +GATE (CLK_SCLK_CUSTOM_EFUSE ,"sclk_custom_efuse" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE ,0 ,0 ,0 ), + +/* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ +GATE (CLK_SCLK_ANTIRBK_CNT ,"sclk_antirbk_cnt" ,"oscclk_efuse_common" , +ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT ,0 ,0 ,0 ), + +/* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ +GATE (CLK_SCLK_OTP_CON ,"sclk_otp_con" ,"oscclk_efuse_common" , + ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), }; static struct samsung_cmu_info peris_cmu_info __initdata = {
include/dt-bindings/clock/exynos5433.h +32 -1
@@ -227,8 +227,39 @@#define CLK_PCLK_WDT_ATLAS 8#define CLK_PCLK_MCT 9#define CLK_PCLK_HDMI_CEC 10 +#define CLK_ACLK_AHB2APB_PERIS1P 11 +#define CLK_ACLK_AHB2APB_PERIS0P 12 +#define CLK_ACLK_PERISNP_66 13 +#define CLK_PCLK_TZPC12 14 +#define CLK_PCLK_TZPC11 15 +#define CLK_PCLK_TZPC10 16 +#define CLK_PCLK_TZPC9 17 +#define CLK_PCLK_TZPC8 18 +#define CLK_PCLK_TZPC7 19 +#define CLK_PCLK_TZPC6 20 +#define CLK_PCLK_TZPC5 21 +#define CLK_PCLK_TZPC4 22 +#define CLK_PCLK_TZPC3 23 +#define CLK_PCLK_TZPC2 24 +#define CLK_PCLK_TZPC1 25 +#define CLK_PCLK_TZPC0 26 +#define CLK_PCLK_SECKEY_APBIF 27 +#define CLK_PCLK_CHIPID_APBIF 28 +#define CLK_PCLK_TOPRTC 29 +#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 +#define CLK_PCLK_ANTIRBK_CNT_APBIF 31 +#define CLK_PCLK_OTP_CON_APBIF 32 +#define CLK_SCLK_ASV_TB 33 +#define CLK_SCLK_TMU1 34 +#define CLK_SCLK_TMU0 35 +#define CLK_SCLK_SECKEY 36 +#define CLK_SCLK_CHIPID 37 +#define CLK_SCLK_TOPRTC 38 +#define CLK_SCLK_CUSTOM_EFUSE 39 +#define CLK_SCLK_ANTIRBK_CNT 40 +#define CLK_SCLK_OTP_CON 41 -#define PERIS_NR_CLK 11 +#define PERIS_NR_CLK 42/* CMU_FSYS */ #define CLK_MOUT_ACLK_FSYS_200_USER 1
Signature · 1 line
1.8.5.5
Re: [PATCH 04/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
Hi Chanwoo,
Quoted 9 lines · Chanwoo Choi
This patch adds missing gate clocks of
CMU_PERISdomain which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs. The special clocks ofCMU_PERISusefin_pllsource clock directly.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>
Quoted 5 lines
--- drivers/clk/samsung/clk-exynos5433.c | 146 ++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 33 +++++++- 2 files changed, 176 insertions(+), 3 deletions(-)
Verified all registers and clock relationship against UM I have, and changes are OK.
Reviewed-by Pankaj Dubey <[email protected]>
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerRe: [PATCH 04/19] clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
Hi Pankaj,
Quoted 18 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 9 lines · Chanwoo Choi
This patch adds missing gate clocks of
CMU_PERISdomain which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs. The special clocks ofCMU_PERISusefin_pllsource clock directly.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>Quoted 5 lines
--- drivers/clk/samsung/clk-exynos5433.c | 146 ++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 33 +++++++- 2 files changed, 176 insertions(+), 3 deletions(-)
Quoted 3 lines
Verified all registers and clock relationship against UM I have, and changes are OK.
Reviewed-by Pankaj Dubey <[email protected]>
Thanks for your review.
Best Regards,
Chanwoo Choi
Chanwoo Choi
maintainerPATCH v2 5/19 clk: samsung: exynos5433: Add clocks for CMU_G2D domain
In reply to Chanwoo ChoiThis patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 42 +++++- 3 files changed, 193 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +8 -0
@@ -19,6 +19,8 @@ Required Properties: which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. + - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D + which generates clocks for G2D/MDMA IPs. - reg: physical base address of the controller and length of memory mapped region.
@@ -70,6 +72,12 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_g2d: clock-controller at 0x12460000 { + compatible = "samsung,exynos5433-cmu-g2d"; + reg = <0x12460000 0x0b08>; + #clock-cells = <1>; + }; + Example 2: UART controller node that consumes the clock generated by the clock controller.
drivers/clk/samsung/clk-exynos5433.c +144 -0
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include/dt-bindings/clock/exynos5433.h +41 -1
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Signature · 1 line
1.8.5.5
Re: [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
Hi Chanwoo,
Quoted 1 line · Chanwoo Choi
This patch adds ths mux/divider/gate clocksof
CMU_G2Ddomain which includes
nit: %s/clocksof/clocks of
Quoted 8 lines
G2D/MDMA IPs. The
CMU_G2Dmust need the clocks related to G2D by providingCMU_TOPdomain. So, this patch add several clocks for G2D fromCMU_TOPdomain.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>
Quoted 6 lines
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 42 +++++- 3 files changed, 193 insertions(+), 1 deletion(-)
Verified all changes in clock file against UM I have with me, all changes are OK.
With small nit in commit message feel free to add:
Reviewed-by Pankaj Dubey <[email protected]>
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerRe: [PATCH 05/19] clk: samsung: exynos5433: Add clocks for CMU_G2D domain
Hi Pankaj,
Quoted 6 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 1 line · Chanwoo Choi
This patch adds ths mux/divider/gate clocksof
CMU_G2Ddomain which includesnit: %s/clocksof/clocks of
I'll fix it.
Quoted 16 lines
Quoted 9 lines
G2D/MDMA IPs. The
CMU_G2Dmust need the clocks related to G2D by providingCMU_TOPdomain. So, this patch add several clocks for G2D fromCMU_TOPdomain.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>Quoted 6 lines
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 42 +++++- 3 files changed, 193 insertions(+), 1 deletion(-)
Quoted 5 lines
Verified all changes in clock file against UM I have with me, all changes are OK.
With small nit in commit message feel free to add:
Reviewed-by Pankaj Dubey <[email protected]>
Thanks for your review.
Best Regards,
Chanwoo Choi
Chanwoo Choi
maintainerPATCH v2 6/19 clk: samsung: exynos5433: Add clocks for CMU_MIF domain
In reply to Chanwoo ChoiThis patch adds the mux/divider/gate clock fo CMU_MIF domain which includes the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect). The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- drivers/clk/samsung/clk-exynos5433.c | 590 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 190 ++++++++++- 2 files changed, 779 insertions(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5433.c +590 -0
@@ -737,6 +737,66 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",#define MFC_PLL_CON0 0x0130#define MFC_PLL_CON1 0x0134#define MFC_PLL_FREQ_DET 0x013c +#define MUX_SEL_MIF0 0x0200 +#define MUX_SEL_MIF1 0x0204 +#define MUX_SEL_MIF2 0x0208 +#define MUX_SEL_MIF3 0x020c +#define MUX_SEL_MIF4 0x0210 +#define MUX_SEL_MIF5 0x0214 +#define MUX_SEL_MIF6 0x0218 +#define MUX_SEL_MIF7 0x021c +#define MUX_ENABLE_MIF0 0x0300 +#define MUX_ENABLE_MIF1 0x0304 +#define MUX_ENABLE_MIF2 0x0308 +#define MUX_ENABLE_MIF3 0x030c +#define MUX_ENABLE_MIF4 0x0310 +#define MUX_ENABLE_MIF5 0x0314 +#define MUX_ENABLE_MIF6 0x0318 +#define MUX_ENABLE_MIF7 0x031c +#define MUX_STAT_MIF0 0x0400 +#define MUX_STAT_MIF1 0x0404 +#define MUX_STAT_MIF2 0x0408 +#define MUX_STAT_MIF3 0x040c +#define MUX_STAT_MIF4 0x0410 +#define MUX_STAT_MIF5 0x0414 +#define MUX_STAT_MIF6 0x0418 +#define MUX_STAT_MIF7 0x041c +#define DIV_MIF1 0x0604 +#define DIV_MIF2 0x0608 +#define DIV_MIF3 0x060c +#define DIV_MIF4 0x0610 +#define DIV_MIF5 0x0614 +#define DIV_MIF_PLL_FREQ_DET 0x0618 +#define DIV_STAT_MIF1 0x0704 +#define DIV_STAT_MIF2 0x0708 +#define DIV_STAT_MIF3 0x070c +#define DIV_STAT_MIF4 0x0710 +#define DIV_STAT_MIF5 0x0714 +#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 +#define ENABLE_ACLK_MIF0 0x0800 +#define ENABLE_ACLK_MIF1 0x0804 +#define ENABLE_ACLK_MIF2 0x0808 +#define ENABLE_ACLK_MIF3 0x080c +#define ENABLE_PCLK_MIF 0x0900 +#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 +#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 +#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c +#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 +#define ENABLE_SCLK_MIF 0x0a00 +#define ENABLE_IP_MIF0 0x0b00 +#define ENABLE_IP_MIF1 0x0b04 +#define ENABLE_IP_MIF2 0x0b08 +#define ENABLE_IP_MIF3 0x0b0c +#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 +#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 +#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 +#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c +#define CLKOUT_CMU_MIF 0x0c00 +#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 +#define DREX_FREQ_CTRL0 0x1000 +#define DREX_FREQ_CTRL1 0x1004 +#define PAUSE 0x1008 +#define DDRPHY_LOCK_CTRL 0x100cstatic unsigned long mif_clk_regs[]__initdata = {MEM0_PLL_LOCK ,
@@ -755,6 +815,66 @@ static unsigned long mif_clk_regs[] __initdata = {MFC_PLL_CON0 ,MFC_PLL_CON1 ,MFC_PLL_FREQ_DET , +MUX_SEL_MIF0 , +MUX_SEL_MIF1 , +MUX_SEL_MIF2 , +MUX_SEL_MIF3 , +MUX_SEL_MIF4 , +MUX_SEL_MIF5 , +MUX_SEL_MIF6 , +MUX_SEL_MIF7 , +MUX_ENABLE_MIF0 , +MUX_ENABLE_MIF1 , +MUX_ENABLE_MIF2 , +MUX_ENABLE_MIF3 , +MUX_ENABLE_MIF4 , +MUX_ENABLE_MIF5 , +MUX_ENABLE_MIF6 , +MUX_ENABLE_MIF7 , +MUX_STAT_MIF0 , +MUX_STAT_MIF1 , +MUX_STAT_MIF2 , +MUX_STAT_MIF3 , +MUX_STAT_MIF4 , +MUX_STAT_MIF5 , +MUX_STAT_MIF6 , +MUX_STAT_MIF7 , +DIV_MIF1 , +DIV_MIF2 , +DIV_MIF3 , +DIV_MIF4 , +DIV_MIF5 , +DIV_MIF_PLL_FREQ_DET , +DIV_STAT_MIF1 , +DIV_STAT_MIF2 , +DIV_STAT_MIF3 , +DIV_STAT_MIF4 , +DIV_STAT_MIF5 , +DIV_STAT_MIF_PLL_FREQ_DET , +ENABLE_ACLK_MIF0 , +ENABLE_ACLK_MIF1 , +ENABLE_ACLK_MIF2 , +ENABLE_ACLK_MIF3 , +ENABLE_PCLK_MIF , +ENABLE_PCLK_MIF_SECURE_DREX0_TZ , +ENABLE_PCLK_MIF_SECURE_DREX1_TZ , +ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT , +ENABLE_PCLK_MIF_SECURE_RTC , +ENABLE_SCLK_MIF , +ENABLE_IP_MIF0 , +ENABLE_IP_MIF1 , +ENABLE_IP_MIF2 , +ENABLE_IP_MIF3 , +ENABLE_IP_MIF_SECURE_DREX0_TZ , +ENABLE_IP_MIF_SECURE_DREX1_TZ , +ENABLE_IP_MIF_SECURE_MONOTONIC_CNT , +ENABLE_IP_MIF_SECURE_RTC , +CLKOUT_CMU_MIF , +CLKOUT_CMU_MIF_DIV_STAT , +DREX_FREQ_CTRL0 , +DREX_FREQ_CTRL1 , +PAUSE , + DDRPHY_LOCK_CTRL, }; static struct samsung_pll_clock mif_pll_clks[] __initdata = {
@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = { MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), }; +/* list of all parent clock list */ +PNAME (mout_mfc_pll_div2_p) = {"mout_mfc_pll" ,"dout_mfc_pll" , }; +PNAME (mout_bus_pll_div2_p) = {"mout_bus_pll" ,"dout_bus_pll" , }; +PNAME (mout_mem1_pll_div2_p) = {"mout_mem1_pll" ,"dout_mem1_pll" , }; +PNAME (mout_mem0_pll_div2_p) = {"mout_mem0_pll" ,"dout_mem0_pll" , }; +PNAME (mout_mfc_pll_p) = {"fin_pll" ,"fout_mfc_pll" , }; +PNAME (mout_bus_pll_p) = {"fin_pll" ,"fout_bus_pll" , }; +PNAME (mout_mem1_pll_p) = {"fin_pll" ,"fout_mem1_pll" , }; +PNAME (mout_mem0_pll_p) = {"fin_pll" ,"fout_mem0_pll" , }; + +PNAME (mout_clk2x_phy_c_p) = {"mout_mem0_pll_div2" ,"mout_clkm_phy_b" , }; +PNAME (mout_clk2x_phy_b_p) = {"mout_bus_pll_div2" ,"mout_clkm_phy_a" , }; +PNAME (mout_clk2x_phy_a_p) = {"mout_bus_pll_div2" ,"mout_mfc_pll_div2" , }; +PNAME (mout_clkm_phy_c_p) = {"mout_mem0_pll_div2" ,"mout_clkm_phy_b" , }; +PNAME (mout_clkm_phy_b_p) = {"mout_mem1_pll_div2" ,"mout_clkm_phy_a" , }; +PNAME (mout_clkm_phy_a_p) = {"mout_bus_pll_div2" ,"mout_mfc_pll_div2" , }; + +PNAME (mout_aclk_mifnm_200_p) = {"mout_mem0_pll_div2" ,"div_mif_pre" , }; +PNAME (mout_aclk_mifnm_400_p) = {"mout_mem1_pll_div2" ,"mout_bus_pll_div2" ,}; + +PNAME (mout_aclk_disp_333_b_p) = {"mout_aclk_disp_333_a" , +"mout_bus_pll_div2" , }; +PNAME (mout_aclk_disp_333_a_p) = {"mout_mfc_pll_div2" ,"sclk_mphy_pll" , }; + +PNAME (mout_sclk_decon_vclk_c_p) = {"mout_sclk_decon_vclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_vclk_b_p) = {"mout_sclk_decon_vclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_vclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_decon_eclk_c_p) = {"mout_sclk_decon_eclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_eclk_b_p) = {"mout_sclk_decon_eclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_eclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; + +PNAME (mout_sclk_decon_tv_eclk_c_p) = {"mout_sclk_decon_tv_eclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_tv_eclk_b_p) = {"mout_sclk_decon_tv_eclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_tv_eclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsd_c_p) = {"mout_sclk_dsd_b" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsd_b_p) = {"mout_sclk_dsd_a" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsd_a_p) = {"fin_pll" ,"mout_mfc_pll_div2" , }; + +PNAME (mout_sclk_dsim0_c_p) = {"mout_sclk_dsim0_b" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsim0_b_p) = {"mout_sclk_dsim0_a" ,"mout_mfc_pll_div2" }; +PNAME (mout_sclk_dsim0_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; + +PNAME (mout_sclk_decon_tv_vclk_c_p) = {"mout_sclk_decon_tv_vclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_tv_vclk_b_p) = {"mout_sclk_decon_tv_vclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_tv_vclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsim1_c_p) = {"mout_sclk_dsim1_b" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsim1_b_p) = {"mout_sclk_dsim1_a" ,"mout_mfc_pll_div2" ,}; +PNAME (mout_sclk_dsim1_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; + +static struct samsung_fixed_factor_clock mif_fixed_factor_clks[]__initdata = { +/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ +FFACTOR (CLK_DOUT_MFC_PLL ,"dout_mfc_pll" ,"mout_mfc_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_BUS_PLL ,"dout_bus_pll" ,"mout_bus_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_MEM1_PLL ,"dout_mem1_pll" ,"mout_mem1_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_MEM0_PLL ,"dout_mem0_pll" ,"mout_mem0_pll" ,1 ,1 ,0 ), +}; + +static struct samsung_mux_clock mif_mux_clks[]__initdata = { +/* MUX_SEL_MIF0 */ +MUX (CLK_MOUT_MFC_PLL_DIV2 ,"mout_mfc_pll_div2" , mout_mfc_pll_div2_p, +MUX_SEL_MIF0 ,28 ,1 ), +MUX (CLK_MOUT_BUS_PLL_DIV2 ,"mout_bus_pll_div2" , mout_bus_pll_div2_p, +MUX_SEL_MIF0 ,24 ,1 ), +MUX (CLK_MOUT_MEM1_PLL_DIV2 ,"mout_mem1_pll_div2" , mout_mem1_pll_div2_p, +MUX_SEL_MIF0 ,20 ,1 ), +MUX (CLK_MOUT_MEM0_PLL_DIV2 ,"mout_mem0_pll_div2" , mout_mem0_pll_div2_p, +MUX_SEL_MIF0 ,16 ,1 ), +MUX (CLK_MOUT_MFC_PLL ,"mout_mfc_pll" , mout_mfc_pll_p,MUX_SEL_MIF0 , +12 ,1 ), +MUX (CLK_MOUT_BUS_PLL ,"mout_bus_pll" , mout_bus_pll_p,MUX_SEL_MIF0 , +8 ,1 ), +MUX (CLK_MOUT_MEM1_PLL ,"mout_mem1_pll" , mout_mem1_pll_p,MUX_SEL_MIF0 , +4 ,1 ), +MUX (CLK_MOUT_MEM0_PLL ,"mout_mem0_pll" , mout_mem0_pll_p,MUX_SEL_MIF0 , +0 ,1 ), + +/* MUX_SEL_MIF1 */ +MUX (CLK_MOUT_CLK2X_PHY_C ,"mout_clk2x_phy_c" , mout_clk2x_phy_c_p, +MUX_SEL_MIF1 ,24 ,1 ), +MUX (CLK_MOUT_CLK2X_PHY_B ,"mout_clk2x_phy_b" , mout_clk2x_phy_b_p, +MUX_SEL_MIF1 ,20 ,1 ), +MUX (CLK_MOUT_CLK2X_PHY_A ,"mout_clk2x_phy_a" , mout_clk2x_phy_a_p, +MUX_SEL_MIF1 ,16 ,1 ), +MUX (CLK_MOUT_CLKM_PHY_C ,"mout_clkm_phy_c" , mout_clkm_phy_c_p, +MUX_SEL_MIF1 ,12 ,1 ), +MUX (CLK_MOUT_CLKM_PHY_B ,"mout_clkm_phy_b" , mout_clkm_phy_b_p, +MUX_SEL_MIF1 ,8 ,1 ), +MUX (CLK_MOUT_CLKM_PHY_A ,"mout_clkm_phy_a" , mout_clkm_phy_a_p, +MUX_SEL_MIF1 ,4 ,1 ), + +/* MUX_SEL_MIF2 */ +MUX (CLK_MOUT_ACLK_MIFNM_200 ,"mout_aclk_mifnm_200" , + mout_aclk_mifnm_200_p,MUX_SEL_MIF2 ,8 ,1 ), +MUX (CLK_MOUT_ACLK_MIFNM_400 ,"mout_aclk_mifnm_400" , + mout_aclk_mifnm_400_p,MUX_SEL_MIF2 ,0 ,1 ), + +/* MUX_SEL_MIF3 */ +MUX (CLK_MOUT_ACLK_DISP_333_B ,"mout_aclk_disp_333_b" , + mout_aclk_disp_333_b_p,MUX_SEL_MIF3 ,4 ,1 ), +MUX (CLK_MOUT_ACLK_DISP_333_A ,"mout_aclk_disp_333_a" , + mout_aclk_disp_333_a_p,MUX_SEL_MIF3 ,0 ,1 ), + +/* MUX_SEL_MIF4 */ +MUX (CLK_MOUT_SCLK_DECON_VCLK_C ,"mout_sclk_decon_vclk_c" , + mout_sclk_decon_vclk_c_p,MUX_SEL_MIF4 ,24 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_VCLK_B ,"mout_sclk_decon_vclk_b" , + mout_sclk_decon_vclk_b_p,MUX_SEL_MIF4 ,20 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_VCLK_A ,"mout_sclk_decon_vclk_a" , + mout_sclk_decon_vclk_a_p,MUX_SEL_MIF4 ,16 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_ECLK_C ,"mout_sclk_decon_eclk_c" , + mout_sclk_decon_eclk_c_p,MUX_SEL_MIF4 ,8 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_ECLK_B ,"mout_sclk_decon_eclk_b" , + mout_sclk_decon_eclk_b_p,MUX_SEL_MIF4 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_ECLK_A ,"mout_sclk_decon_eclk_a" , + mout_sclk_decon_eclk_a_p,MUX_SEL_MIF4 ,0 ,1 ), + +/* MUX_SEL_MIF5 */ +MUX (CLK_MOUT_SCLK_DECON_TV_ECLK_C ,"mout_sclk_decon_tv_eclk_c" , + mout_sclk_decon_tv_eclk_c_p,MUX_SEL_MIF5 ,24 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_TV_ECLK_B ,"mout_sclk_decon_tv_eclk_b" , + mout_sclk_decon_tv_eclk_b_p,MUX_SEL_MIF5 ,20 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_TV_ECLK_A ,"mout_sclk_decon_tv_eclk_a" , + mout_sclk_decon_tv_eclk_a_p,MUX_SEL_MIF5 ,16 ,1 ), +MUX (CLK_MOUT_SCLK_DSD_C ,"mout_sclk_dsd_c" , mout_sclk_dsd_c_p, +MUX_SEL_MIF5 ,8 ,1 ), +MUX (CLK_MOUT_SCLK_DSD_B ,"mout_sclk_dsd_b" , mout_sclk_dsd_b_p, +MUX_SEL_MIF5 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_DSD_A ,"mout_sclk_dsd_a" , mout_sclk_dsd_a_p, +MUX_SEL_MIF5 ,0 ,1 ), + +/* MUX_SEL_MIF6 */ +MUX (CLK_MOUT_SCLK_DSIM0_C ,"mout_sclk_dsim0_c" , mout_sclk_dsim0_c_p, +MUX_SEL_MIF6 ,8 ,1 ), +MUX (CLK_MOUT_SCLK_DSIM0_B ,"mout_sclk_dsim0_b" , mout_sclk_dsim0_b_p, +MUX_SEL_MIF6 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_DSIM0_A ,"mout_sclk_dsim0_a" , mout_sclk_dsim0_a_p, +MUX_SEL_MIF6 ,0 ,1 ), + +/* MUX_SEL_MIF7 */ +MUX (CLK_MOUT_SCLK_DECON_TV_VCLK_C ,"mout_sclk_decon_tv_vclk_c" , + mout_sclk_decon_tv_vclk_c_p,MUX_SEL_MIF7 ,24 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_TV_VCLK_B ,"mout_sclk_decon_tv_vclk_b" , + mout_sclk_decon_tv_vclk_b_p,MUX_SEL_MIF7 ,20 ,1 ), +MUX (CLK_MOUT_SCLK_DECON_TV_VCLK_A ,"mout_sclk_decon_tv_vclk_a" , + mout_sclk_decon_tv_vclk_a_p,MUX_SEL_MIF7 ,16 ,1 ), +MUX (CLK_MOUT_SCLK_DSIM1_C ,"mout_sclk_dsim1_c" , mout_sclk_dsim1_c_p, +MUX_SEL_MIF7 ,8 ,1 ), +MUX (CLK_MOUT_SCLK_DSIM1_B ,"mout_sclk_dsim1_b" , mout_sclk_dsim1_b_p, +MUX_SEL_MIF7 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_DSIM1_A ,"mout_sclk_dsim1_a" , mout_sclk_dsim1_a_p, +MUX_SEL_MIF7 ,0 ,1 ), +}; + +static struct samsung_div_clock mif_div_clks[]__initdata = { +/* DIV_MIF1 */ +DIV (CLK_DIV_SCLK_HPM_MIF ,"div_sclk_hpm_mif" ,"div_clk2x_phy" , +DIV_MIF1 ,16 ,2 ), +DIV (CLK_DIV_ACLK_DREX1 ,"div_aclk_drex1" ,"div_clk2x_phy" ,DIV_MIF1 , +12 ,2 ), +DIV (CLK_DIV_ACLK_DREX0 ,"div_aclk_drex0" ,"div_clk2x_phy" ,DIV_MIF1 , +8 ,2 ), +DIV (CLK_DIV_CLK2XPHY ,"div_clk2x_phy" ,"mout_clk2x_phy_c" ,DIV_MIF1 , +4 ,4 ), + +/* DIV_MIF2 */ +DIV (CLK_DIV_ACLK_MIF_266 ,"div_aclk_mif_266" ,"mout_bus_pll_div2" , +DIV_MIF2 ,20 ,3 ), +DIV (CLK_DIV_ACLK_MIFND_133 ,"div_aclk_mifnd_133" ,"div_mif_pre" , +DIV_MIF2 ,16 ,4 ), +DIV (CLK_DIV_ACLK_MIF_133 ,"div_aclk_mif_133" ,"div_mif_pre" , +DIV_MIF2 ,12 ,4 ), +DIV (CLK_DIV_ACLK_MIFNM_200 ,"div_aclk_mifnm_200" , +"mout_aclk_mifnm_200" ,DIV_MIF2 ,8 ,3 ), +DIV (CLK_DIV_ACLK_MIF_200 ,"div_aclk_mif_200" ,"div_aclk_mif_400" , +DIV_MIF2 ,4 ,2 ), +DIV (CLK_DIV_ACLK_MIF_400 ,"div_aclk_mif_400" ,"mout_aclk_mifnm_400" , +DIV_MIF2 ,0 ,3 ), + +/* DIV_MIF3 */ +DIV (CLK_DIV_ACLK_BUS2_400 ,"div_aclk_bus2_400" ,"div_mif_pre" , +DIV_MIF3 ,16 ,4 ), +DIV (CLK_DIV_ACLK_DISP_333 ,"div_aclk_disp_333" ,"mout_aclk_disp_333_b" , +DIV_MIF3 ,4 ,3 ), +DIV (CLK_DIV_ACLK_CPIF_200 ,"div_aclk_cpif_200" ,"mout_aclk_mifnm_200" , +DIV_MIF3 ,0 ,3 ), + +/* DIV_MIF4 */ +DIV (CLK_DIV_SCLK_DSIM1 ,"div_sclk_dsim1" ,"mout_sclk_dsim1_c" , +DIV_MIF4 ,24 ,4 ), +DIV (CLK_DIV_SCLK_DECON_TV_VCLK ,"div_sclk_decon_tv_vclk" , +"mout_sclk_decon_tv_vclk_c" ,DIV_MIF4 ,20 ,4 ), +DIV (CLK_DIV_SCLK_DSIM0 ,"div_sclk_dsim0" ,"mout_sclk_dsim0_c" , +DIV_MIF4 ,16 ,4 ), +DIV (CLK_DIV_SCLK_DSD ,"div_sclk_dsd" ,"mout_sclk_dsd_c" , +DIV_MIF4 ,12 ,4 ), +DIV (CLK_DIV_SCLK_DECON_TV_ECLK ,"div_sclk_decon_tv_eclk" , +"mout_sclk_decon_tv_eclk_c" ,DIV_MIF4 ,8 ,4 ), +DIV (CLK_DIV_SCLK_DECON_VCLK ,"div_sclk_decon_vclk" , +"mout_sclk_decon_vclk_c" ,DIV_MIF4 ,4 ,4 ), +DIV (CLK_DIV_SCLK_DECON_ECLK ,"div_sclk_decon_eclk" , +"mout_sclk_decon_eclk_c" ,DIV_MIF4 ,0 ,4 ), + +/* DIV_MIF5 */ +DIV (CLK_DIV_MIF_PRE ,"div_mif_pre" ,"mout_bus_pll_div2" ,DIV_MIF5 , +0 ,3 ), +}; + +static struct samsung_gate_clock mif_gate_clks[]__initdata = { +/* ENABLE_ACLK_MIF0 */ +GATE (CLK_CLK2X_PHY1 ,"clk2k_phy1" ,"div_clk2x_phy" ,ENABLE_ACLK_MIF0 , +19 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_CLK2X_PHY0 ,"clk2x_phy0" ,"div_clk2x_phy" ,ENABLE_ACLK_MIF0 , +18 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_CLKM_PHY1 ,"clkm_phy1" ,"mout_clkm_phy_c" ,ENABLE_ACLK_MIF0 , +17 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_CLKM_PHY0 ,"clkm_phy0" ,"mout_clkm_phy_c" ,ENABLE_ACLK_MIF0 , +16 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_RCLK_DREX1 ,"rclk_drex1" ,"fin_pll" ,ENABLE_ACLK_MIF0 , +15 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_RCLK_DREX0 ,"rclk_drex0" ,"fin_pll" ,ENABLE_ACLK_MIF0 , +14 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX1_TZ ,"aclk_drex1_tz" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF0 ,13 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX0_TZ ,"aclk_drex0_tz" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF0 ,12 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX1_PEREV ,"aclk_drex1_perev" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF0 ,11 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX0_PEREV ,"aclk_drex0_perev" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF0 ,10 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX1_MEMIF ,"aclk_drex1_memif" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF0 ,9 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX0_MEMIF ,"aclk_drex0_memif" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF0 ,8 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX1_SCH ,"aclk_drex1_sch" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF0 ,7 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX0_SCH ,"aclk_drex0_sch" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF0 ,6 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX1_BUSIF ,"aclk_drex1_busif" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF0 ,5 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX0_BUSIF ,"aclk_drex0_busif" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF0 ,4 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX1_BUSIF_RD ,"aclk_drex1_busif_rd" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF0 ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX0_BUSIF_RD ,"aclk_drex0_busif_rd" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF0 ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX1 ,"aclk_drex1" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF0 ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_DREX0 ,"aclk_drex0" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF0 ,1 ,CLK_IGNORE_UNUSED ,0 ), + +/* ENABLE_ACLK_MIF1 */ +GATE (CLK_ACLK_ASYNCAXIS_MIF_IMEM ,"aclk_asyncaxis_mif_imem" , +"div_aclk_mif_200" ,ENABLE_ACLK_MIF1 ,28 , +CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_NOC_P_CCI ,"aclk_asyncaxis_noc_p_cci" , +"div_aclk_mif_200" ,ENABLE_ACLK_MIF1 , +27 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_NOC_P_CCI ,"aclk_asyncaxim_noc_p_cci" , +"div_aclk_mif_133" ,ENABLE_ACLK_MIF1 , +26 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_CP1 ,"aclk_asyncaxis_cp1" , +"div_aclk_mifnm_200" ,ENABLE_ACLK_MIF1 , +25 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_CP1 ,"aclk_asyncaxim_cp1" , +"div_aclk_drex1" ,ENABLE_ACLK_MIF1 , +24 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_CP0 ,"aclk_asyncaxis_cp0" , +"div_aclk_mifnm_200" ,ENABLE_ACLK_MIF1 , +23 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_CP0 ,"aclk_asyncaxim_cp0" , +"div_aclk_drex0" ,ENABLE_ACLK_MIF1 , +22 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_DREX1_3 ,"aclk_asyncaxis_drex1_3" , +"div_aclk_mif_133" ,ENABLE_ACLK_MIF1 , +21 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_DREX1_3 ,"aclk_asyncaxim_drex1_3" , +"div_aclk_drex1" ,ENABLE_ACLK_MIF1 , +20 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_DREX1_1 ,"aclk_asyncaxis_drex1_1" , +"div_aclk_mif_133" ,ENABLE_ACLK_MIF1 , +19 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_DREX1_1 ,"aclk_asyncaxim_drex1_1" , +"div_aclk_drex1" ,ENABLE_ACLK_MIF1 , +18 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_DREX1_0 ,"aclk_asyncaxis_drex1_0" , +"div_aclk_mif_133" ,ENABLE_ACLK_MIF1 , +17 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_DREX1_0 ,"aclk_asyncaxim_drex1_0" , +"div_aclk_drex1" ,ENABLE_ACLK_MIF1 , +16 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_DREX0_3 ,"aclk_asyncaxis_drex0_3" , +"div_aclk_mif_133" ,ENABLE_ACLK_MIF1 , +15 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_DREX0_3 ,"aclk_asyncaxim_drex0_3" , +"div_aclk_drex0" ,ENABLE_ACLK_MIF1 , +14 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_DREX0_1 ,"aclk_asyncaxis_drex0_1" , +"div_aclk_mif_133" ,ENABLE_ACLK_MIF1 , +13 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_DREX0_1 ,"aclk_asyncaxim_drex0_1" , +"div_aclk_drex0" ,ENABLE_ACLK_MIF1 , +12 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIS_DREX0_0 ,"aclk_asyncaxis_drex0_0" , +"div_aclk_mif_133" ,ENABLE_ACLK_MIF1 , +11 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAXIM_DREX0_0 ,"aclk_asyncaxim_drex0_0" , +"div_aclk_drex0" ,ENABLE_ACLK_MIF1 , +10 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_MIF2P ,"aclk_ahb2apb_mif2p" ,"div_aclk_mif_133" , +ENABLE_ACLK_MIF1 ,9 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_MIF1P ,"aclk_ahb2apb_mif1p" ,"div_aclk_mif_133" , +ENABLE_ACLK_MIF1 ,8 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_MIF0P ,"aclk_ahb2apb_mif0p" ,"div_aclk_mif_133" , +ENABLE_ACLK_MIF1 ,7 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_IXIU_CCI ,"aclk_ixiu_cci" ,"div_aclk_mif_400" , +ENABLE_ACLK_MIF1 ,6 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_XIU_MIFSFRX ,"aclk_xiu_mifsfrx" ,"div_aclk_mif_200" , +ENABLE_ACLK_MIF1 ,5 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_MIFNP_133 ,"aclk_mifnp_133" ,"div_aclk_mif_133" , +ENABLE_ACLK_MIF1 ,4 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_MIFNM_200 ,"aclk_mifnm_200" ,"div_aclk_mifnm_200" , +ENABLE_ACLK_MIF1 ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_MIFND_133 ,"aclk_mifnd_133" ,"div_aclk_mifnd_133" , +ENABLE_ACLK_MIF1 ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_MIFND_400 ,"aclk_mifnd_400" ,"div_aclk_mif_400" , +ENABLE_ACLK_MIF1 ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_CCI ,"aclk_cci" ,"div_aclk_mif_400" ,ENABLE_ACLK_MIF1 , +0 ,CLK_IGNORE_UNUSED ,0 ), + +/* ENABLE_ACLK_MIF2 */ +GATE (CLK_ACLK_MIFND_266 ,"aclk_mifnd_266" ,"div_aclk_mif_266" , +ENABLE_ACLK_MIF2 ,20 ,0 ,0 ), +GATE (CLK_ACLK_PPMU_DREX1S3 ,"aclk_ppmu_drex1s3" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF2 ,17 ,0 ,0 ), +GATE (CLK_ACLK_PPMU_DREX1S1 ,"aclk_ppmu_drex1s1" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF2 ,16 ,0 ,0 ), +GATE (CLK_ACLK_PPMU_DREX1S0 ,"aclk_ppmu_drex1s0" ,"div_aclk_drex1" , +ENABLE_ACLK_MIF2 ,15 ,0 ,0 ), +GATE (CLK_ACLK_PPMU_DREX0S3 ,"aclk_ppmu_drex0s3" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF2 ,14 ,0 ,0 ), +GATE (CLK_ACLK_PPMU_DREX0S1 ,"aclk_ppmu_drex0s1" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF2 ,13 ,0 ,0 ), +GATE (CLK_ACLK_PPMU_DREX0S0 ,"aclk_ppmu_drex0s0" ,"div_aclk_drex0" , +ENABLE_ACLK_MIF2 ,12 ,0 ,0 ), +GATE (CLK_ACLK_AXIDS_CCI_MIFSFRX ,"aclk_axids_cci_mifsfrx" , +"div_aclk_mif_200" ,ENABLE_ACLK_MIF2 ,7 , +CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AXISYNCDNS_CCI ,"aclk_axisyncdns_cci" , +"div_aclk_mif_400" ,ENABLE_ACLK_MIF2 , +5 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AXISYNCDN_CCI ,"aclk_axisyncdn_cci" ,"div_aclk_mif_400" , +ENABLE_ACLK_MIF2 ,4 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AXISYNCDN_NOC_D ,"aclk_axisyncdn_noc_d" , +"div_aclk_mif_200" ,ENABLE_ACLK_MIF2 , +3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_ASYNCAPBS_MIF_CSSYS ,"aclk_asyncapbs_mif_cssys" , +"div_aclk_mifnd_133" ,ENABLE_ACLK_MIF2 ,0 ,0 ,0 ), + +/* ENABLE_ACLK_MIF3 */ +GATE (CLK_ACLK_BUS2_400 ,"aclk_bus2_400" ,"div_aclk_bus2_400" , +ENABLE_ACLK_MIF3 ,4 ,0 ,0 ), +GATE (CLK_ACLK_DISP_333 ,"aclk_disp_333" ,"div_aclk_disp_333" , +ENABLE_ACLK_MIF3 ,1 ,0 ,0 ), +GATE (CLK_ACLK_CPIF_200 ,"aclk_cpif_200" ,"div_aclk_cpif_200" , +ENABLE_ACLK_MIF3 ,0 ,CLK_IGNORE_UNUSED ,0 ), + +/* ENABLE_PCLK_MIF */ +GATE (CLK_PCLK_PPMU_DREX1S3 ,"pclk_ppmu_drex1s3" ,"div_aclk_drex1" , +ENABLE_PCLK_MIF ,29 ,0 ,0 ), +GATE (CLK_PCLK_PPMU_DREX1S1 ,"pclk_ppmu_drex1s1" ,"div_aclk_drex1" , +ENABLE_PCLK_MIF ,28 ,0 ,0 ), +GATE (CLK_PCLK_PPMU_DREX1S0 ,"pclk_ppmu_drex1s0" ,"div_aclk_drex1" , +ENABLE_PCLK_MIF ,27 ,0 ,0 ), +GATE (CLK_PCLK_PPMU_DREX0S3 ,"pclk_ppmu_drex0s3" ,"div_aclk_drex0" , +ENABLE_PCLK_MIF ,26 ,0 ,0 ), +GATE (CLK_PCLK_PPMU_DREX0S1 ,"pclk_ppmu_drex0s1" ,"div_aclk_drex0" , +ENABLE_PCLK_MIF ,25 ,0 ,0 ), +GATE (CLK_PCLK_PPMU_DREX0S0 ,"pclk_ppmu_drex0s0" ,"div_aclk_drex0" , +ENABLE_PCLK_MIF ,24 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_NOC_P_CCI ,"pclk_asyncaxi_noc_p_cci" , +"div_aclk_mif_133" ,ENABLE_PCLK_MIF ,21 , +CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_ASYNCAXI_CP1 ,"pclk_asyncaxi_cp1" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,19 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_CP0 ,"pclk_asyncaxi_cp0" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,18 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_DREX1_3 ,"pclk_asyncaxi_drex1_3" , +"div_aclk_mif_133" ,ENABLE_PCLK_MIF ,17 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_DREX1_1 ,"pclk_asyncaxi_drex1_1" , +"div_aclk_mif_133" ,ENABLE_PCLK_MIF ,16 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_DREX1_0 ,"pclk_asyncaxi_drex1_0" , +"div_aclk_mif_133" ,ENABLE_PCLK_MIF ,15 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_DREX0_3 ,"pclk_asyncaxi_drex0_3" , +"div_aclk_mif_133" ,ENABLE_PCLK_MIF ,14 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_DREX0_1 ,"pclk_asyncaxi_drex0_1" , +"div_aclk_mif_133" ,ENABLE_PCLK_MIF ,13 ,0 ,0 ), +GATE (CLK_PCLK_ASYNCAXI_DREX0_0 ,"pclk_asyncaxi_drex0_0" , +"div_aclk_mif_133" ,ENABLE_PCLK_MIF ,12 ,0 ,0 ), +GATE (CLK_PCLK_MIFSRVND_133 ,"pclk_mifsrvnd_133" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,11 ,0 ,0 ), +GATE (CLK_PCLK_PMU_MIF ,"pclk_pmu_mif" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,10 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_SYSREG_MIF ,"pclk_sysreg_mif" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,9 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_GPIO_ALIVE ,"pclk_gpio_alive" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,8 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_ABB ,"pclk_abb" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,7 ,0 ,0 ), +GATE (CLK_PCLK_PMU_APBIF ,"pclk_pmu_apbif" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,6 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_DDR_PHY1 ,"pclk_ddr_phy1" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,5 ,0 ,0 ), +GATE (CLK_PCLK_DREX1 ,"pclk_drex1" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_DDR_PHY0 ,"pclk_ddr_phy0" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,2 ,0 ,0 ), +GATE (CLK_PCLK_DREX0 ,"pclk_drex0" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF ,0 ,CLK_IGNORE_UNUSED ,0 ), + +/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ +GATE (CLK_PCLK_DREX0_TZ ,"pclk_drex0_tz" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF_SECURE_DREX0_TZ ,0 ,0 ,0 ), + +/* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ +GATE (CLK_PCLK_DREX1_TZ ,"pclk_drex1_tz" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF_SECURE_DREX1_TZ ,0 ,0 ,0 ), + +/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ +GATE (CLK_PCLK_MONOTONIC_CNT ,"pclk_monotonic_cnt" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF_SECURE_RTC ,0 ,0 ,0 ), + +/* ENABLE_PCLK_MIF_SECURE_RTC */ +GATE (CLK_PCLK_RTC ,"pclk_rtc" ,"div_aclk_mif_133" , +ENABLE_PCLK_MIF_SECURE_RTC ,0 ,0 ,0 ), + +/* ENABLE_SCLK_MIF */ +GATE (CLK_SCLK_DSIM1_DISP ,"sclk_dsim1_disp" ,"div_sclk_dsim1" , +ENABLE_SCLK_MIF ,15 ,0 ,0 ), +GATE (CLK_SCLK_DECON_TV_VCLK_DISP ,"sclk_decon_tv_vclk_disp" , +"div_sclk_decon_tv_vclk" ,ENABLE_SCLK_MIF ,14 ,0 ,0 ), +GATE (CLK_SCLK_DSIM0_DISP ,"sclk_dsim0_disp" ,"div_sclk_dsim0" , +ENABLE_SCLK_MIF ,9 ,0 ,0 ), +GATE (CLK_SCLK_DSD_DISP ,"sclk_dsd_disp" ,"div_sclk_dsd" , +ENABLE_SCLK_MIF ,8 ,0 ,0 ), +GATE (CLK_SCLK_DECON_TV_ECLK_DISP ,"sclk_decon_tv_eclk_disp" , +"div_sclk_decon_tv_eclk" ,ENABLE_SCLK_MIF ,7 ,0 ,0 ), +GATE (CLK_SCLK_DECON_VCLK_DISP ,"sclk_decon_vclk_disp" , +"div_sclk_decon_vclk" ,ENABLE_SCLK_MIF ,6 ,0 ,0 ), +GATE (CLK_SCLK_DECON_ECLK_DISP ,"sclk_decon_eclk_disp" , +"div_sclk_decon_eclk" ,ENABLE_SCLK_MIF ,5 ,0 ,0 ), +GATE (CLK_SCLK_HPM_MIF ,"sclk_hpm_mif" ,"div_sclk_hpm_mif" , +ENABLE_SCLK_MIF ,4 ,0 ,0 ), +}; +static struct samsung_cmu_info mif_cmu_info__initdata = { .pll_clks = mif_pll_clks, .nr_pll_clks =ARRAY_SIZE (mif_pll_clks), + .mux_clks = mif_mux_clks, + .nr_mux_clks =ARRAY_SIZE (mif_mux_clks), + .div_clks = mif_div_clks, + .nr_div_clks =ARRAY_SIZE (mif_div_clks), + .gate_clks = mif_gate_clks, + .nr_gate_clks =ARRAY_SIZE (mif_gate_clks), + .fixed_factor_clks = mif_fixed_factor_clks, + .nr_fixed_factor_clks =ARRAY_SIZE (mif_fixed_factor_clks), .nr_clk_ids =MIF_NR_CLK , .clk_regs = mif_clk_regs, .nr_clk_regs =ARRAY_SIZE (mif_clk_regs),
include/dt-bindings/clock/exynos5433.h +189 -1
197 lines not on this page · raw message
Signature · 1 line
1.8.5.5
Re: [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
Hi Chanwoo,
Quoted 1 line · Chanwoo Choi
This patch adds the mux/divider/gate clock fo
CMU_MIFdomain which includes
nit: %s/fo/of
Quoted 13 lines
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect). The
CMU_MIFdomain provides the source clocks for CMU_DISP/CMU_BUS2.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 590 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 190 ++++++++++- 2 files changed, 779 insertions(+), 1 deletion(-)
[snip]
Quoted 10 lines
static struct samsung_pll_clock mif_pll_clks[] __initdata = {drivers/clk/samsung/clk-exynos5433.c +4
-0@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = { MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), }; +/* list of all parent clock list */ +PNAME (mout_mfc_pll_div2_p) = {"mout_mfc_pll" ,"dout_mfc_pll" , }; +PNAME (mout_bus_pll_div2_p) = {"mout_bus_pll" ,"dout_bus_pll" , }; +PNAME (mout_mem1_pll_div2_p) = {"mout_mem1_pll" ,"dout_mem1_pll" , };
drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 904
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+PNAME (mout_mem0_pll_div2_p) = {"mout_mem0_pll" ,"dout_mem0_pll" , }; +PNAME (mout_mfc_pll_p) = {"fin_pll" ,"fout_mfc_pll" , }; +PNAME (mout_bus_pll_p) = {"fin_pll" ,"fout_bus_pll" , }; +PNAME (mout_mem1_pll_p) = {"fin_pll" ,"fout_mem1_pll" , }; +PNAME (mout_mem0_pll_p) = {"fin_pll" ,"fout_mem0_pll" , }; + +PNAME (mout_clk2x_phy_c_p) = {"mout_mem0_pll_div2" ,"mout_clkm_phy_b" , }; +PNAME (mout_clk2x_phy_b_p) = {"mout_bus_pll_div2" ,"mout_clkm_phy_a" , }; +PNAME (mout_clk2x_phy_a_p) = {"mout_bus_pll_div2" ,"mout_mfc_pll_div2" , }; +PNAME (mout_clkm_phy_c_p) = {"mout_mem0_pll_div2" ,"mout_clkm_phy_b" , };
As mout_clk2x_phy_c_p and mout_clkm_phy_c_p both has same parent list one of them can be dropped.
drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 906
Quoted 2 lines
drivers/clk/samsung/clk-exynos5433.c +2
-0+PNAME (mout_clkm_phy_b_p) = {"mout_mem1_pll_div2" ,"mout_clkm_phy_a" , }; +PNAME (mout_clkm_phy_a_p) = {"mout_bus_pll_div2" ,"mout_mfc_pll_div2" , };
As mout_clk2x_phy_a_p and mout_clkm_phy_a_p both has same parent list one of them can be dropped.
Quoted 31 lines
drivers/clk/samsung/clk-exynos5433.c +31
-0+ +PNAME (mout_aclk_mifnm_200_p) = {"mout_mem0_pll_div2" ,"div_mif_pre" , }; +PNAME (mout_aclk_mifnm_400_p) = {"mout_mem1_pll_div2" ,"mout_bus_pll_div2" ,}; + +PNAME (mout_aclk_disp_333_b_p) = {"mout_aclk_disp_333_a" , +"mout_bus_pll_div2" , }; +PNAME (mout_aclk_disp_333_a_p) = {"mout_mfc_pll_div2" ,"sclk_mphy_pll" , }; + +PNAME (mout_sclk_decon_vclk_c_p) = {"mout_sclk_decon_vclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_vclk_b_p) = {"mout_sclk_decon_vclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_vclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_decon_eclk_c_p) = {"mout_sclk_decon_eclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_eclk_b_p) = {"mout_sclk_decon_eclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_eclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; + +PNAME (mout_sclk_decon_tv_eclk_c_p) = {"mout_sclk_decon_tv_eclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_tv_eclk_b_p) = {"mout_sclk_decon_tv_eclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_tv_eclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsd_c_p) = {"mout_sclk_dsd_b" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsd_b_p) = {"mout_sclk_dsd_a" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsd_a_p) = {"fin_pll" ,"mout_mfc_pll_div2" , }; + +PNAME (mout_sclk_dsim0_c_p) = {"mout_sclk_dsim0_b" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsim0_b_p) = {"mout_sclk_dsim0_a" ,"mout_mfc_pll_div2" }; +PNAME (mout_sclk_dsim0_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , };
drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 947
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+ +PNAME (mout_sclk_decon_tv_vclk_c_p) = {"mout_sclk_decon_tv_vclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_tv_vclk_b_p) = {"mout_sclk_decon_tv_vclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_tv_vclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsim1_c_p) = {"mout_sclk_dsim1_b" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsim1_b_p) = {"mout_sclk_dsim1_a" ,"mout_mfc_pll_div2" ,}; +PNAME (mout_sclk_dsim1_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +
Same way I can see {"fin_pll", "mout_bus_pll_div2", } this combination of parents is repeated six times above in different PNAME, which can be replaced by one PNAME list with some common name, thus saving of 5 lines.
drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 955
Quoted 8 lines
drivers/clk/samsung/clk-exynos5433.c +8
-0+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[]__initdata = { +/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ +FFACTOR (CLK_DOUT_MFC_PLL ,"dout_mfc_pll" ,"mout_mfc_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_BUS_PLL ,"dout_bus_pll" ,"mout_bus_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_MEM1_PLL ,"dout_mem1_pll" ,"mout_mem1_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_MEM0_PLL ,"dout_mem0_pll" ,"mout_mem0_pll" ,1 ,1 ,0 ), +}; +
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerRe: [PATCH 06/19] clk: samsung: exynos5433: Add clocks for CMU_MIF domain
Hi Pankaj,
Quoted 6 lines · Pankaj Dubey
Hi Chanwoo,
Quoted 1 line · Chanwoo Choi
This patch adds the mux/divider/gate clock fo
CMU_MIFdomain which includesnit: %s/fo/of
I'll fix it.
Quoted 23 lines
Quoted 14 lines
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect). The
CMU_MIFdomain provides the source clocks for CMU_DISP/CMU_BUS2.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 590 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 190 ++++++++++- 2 files changed, 779 insertions(+), 1 deletion(-)[snip]
Quoted 6 lines
static struct samsung_pll_clock mif_pll_clks[] __initdata = {drivers/clk/samsung/clk-exynos5433.c +0
-0@@ -768,9 +888,479 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = { MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), };
Quoted 16 lines
Quoted 4 lines
drivers/clk/samsung/clk-exynos5433.c +4
-0+/* list of all parent clock list */ +PNAME (mout_mfc_pll_div2_p) = {"mout_mfc_pll" ,"dout_mfc_pll" , }; +PNAME (mout_bus_pll_div2_p) = {"mout_bus_pll" ,"dout_bus_pll" , }; +PNAME (mout_mem1_pll_div2_p) = {"mout_mem1_pll" ,"dout_mem1_pll" , };drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 904
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+PNAME (mout_mem0_pll_div2_p) = {"mout_mem0_pll" ,"dout_mem0_pll" , }; +PNAME (mout_mfc_pll_p) = {"fin_pll" ,"fout_mfc_pll" , }; +PNAME (mout_bus_pll_p) = {"fin_pll" ,"fout_bus_pll" , }; +PNAME (mout_mem1_pll_p) = {"fin_pll" ,"fout_mem1_pll" , }; +PNAME (mout_mem0_pll_p) = {"fin_pll" ,"fout_mem0_pll" , }; + +PNAME (mout_clk2x_phy_c_p) = {"mout_mem0_pll_div2" ,"mout_clkm_phy_b" , }; +PNAME (mout_clk2x_phy_b_p) = {"mout_bus_pll_div2" ,"mout_clkm_phy_a" , }; +PNAME (mout_clk2x_phy_a_p) = {"mout_bus_pll_div2" ,"mout_mfc_pll_div2" , }; +PNAME (mout_clkm_phy_c_p) = {"mout_mem0_pll_div2" ,"mout_clkm_phy_b" , };As
mout_clk2x_phy_c_pandmout_clkm_phy_c_pboth has same parent list one of them can be dropped.
OK, I'll use common parent to remove duplicat code.
Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 906
Quoted 3 lines
drivers/clk/samsung/clk-exynos5433.c +2
-0+PNAME (mout_clkm_phy_b_p) = {"mout_mem1_pll_div2" ,"mout_clkm_phy_a" , }; +PNAME (mout_clkm_phy_a_p) = {"mout_bus_pll_div2" ,"mout_mfc_pll_div2" , };As
mout_clk2x_phy_a_pandmout_clkm_phy_a_pboth has same parent list one of them can be dropped.
OK.
Quoted 36 lines
Quoted 36 lines
drivers/clk/samsung/clk-exynos5433.c +35
-0+ +PNAME (mout_aclk_mifnm_200_p) = {"mout_mem0_pll_div2" ,"div_mif_pre" , }; +PNAME (mout_aclk_mifnm_400_p) = {"mout_mem1_pll_div2" ,"mout_bus_pll_div2" ,}; + +PNAME (mout_aclk_disp_333_b_p) = {"mout_aclk_disp_333_a" , +"mout_bus_pll_div2" , }; +PNAME (mout_aclk_disp_333_a_p) = {"mout_mfc_pll_div2" ,"sclk_mphy_pll" , }; + +PNAME (mout_sclk_decon_vclk_c_p) = {"mout_sclk_decon_vclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_vclk_b_p) = {"mout_sclk_decon_vclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_vclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_decon_eclk_c_p) = {"mout_sclk_decon_eclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_eclk_b_p) = {"mout_sclk_decon_eclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_eclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; + +PNAME (mout_sclk_decon_tv_eclk_c_p) = {"mout_sclk_decon_tv_eclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_tv_eclk_b_p) = {"mout_sclk_decon_tv_eclk_a" , +"mout_mfc_pll_div2" , }; +PNAME (mout_sclk_decon_tv_eclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsd_c_p) = {"mout_sclk_dsd_b" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsd_b_p) = {"mout_sclk_dsd_a" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsd_a_p) = {"fin_pll" ,"mout_mfc_pll_div2" , }; + +PNAME (mout_sclk_dsim0_c_p) = {"mout_sclk_dsim0_b" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsim0_b_p) = {"mout_sclk_dsim0_a" ,"mout_mfc_pll_div2" }; +PNAME (mout_sclk_dsim0_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; + +PNAME (mout_sclk_decon_tv_vclk_c_p) = {"mout_sclk_decon_tv_vclk_b" , +"sclk_mphy_pll" , }; +PNAME (mout_sclk_decon_tv_vclk_b_p) = {"mout_sclk_decon_tv_vclk_a" ,
Quoted 8 lines
drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 947
Quoted 6 lines
drivers/clk/samsung/clk-exynos5433.c +6
-0+ "mout_mfc_pll_div2", }; +PNAME (mout_sclk_decon_tv_vclk_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +PNAME (mout_sclk_dsim1_c_p) = {"mout_sclk_dsim1_b" ,"sclk_mphy_pll" , }; +PNAME (mout_sclk_dsim1_b_p) = {"mout_sclk_dsim1_a" ,"mout_mfc_pll_div2" ,}; +PNAME (mout_sclk_dsim1_a_p) = {"fin_pll" ,"mout_bus_pll_div2" , }; +Same way I can see {"
fin_pll", "mout_bus_pll_div2", } this combination of parents is repeated six times above in different PNAME, which can be replaced by one PNAME list with some common name, thus saving of 5 lines.
OK.
Quoted 9 lines
drivers/clk/samsung/clk-exynos5433.c static struct samsung_pll_clock mif_pll_clks[] __initdata = { · line 955
Quoted 9 lines
drivers/clk/samsung/clk-exynos5433.c +8
-0+static struct samsung_fixed_factor_clock mif_fixed_factor_clks[]__initdata = { +/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ +FFACTOR (CLK_DOUT_MFC_PLL ,"dout_mfc_pll" ,"mout_mfc_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_BUS_PLL ,"dout_bus_pll" ,"mout_bus_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_MEM1_PLL ,"dout_mem1_pll" ,"mout_mem1_pll" ,1 ,1 ,0 ), +FFACTOR (CLK_DOUT_MEM0_PLL ,"dout_mem0_pll" ,"mout_mem0_pll" ,1 ,1 ,0 ), +}; +
Thanks for your review.
Best Regards,
Chanwoo Choi
Chanwoo Choi
maintainerPATCH v2 7/19 clk: samsung: exynos5433: Add clocks for CMU_DISP domain
In reply to Chanwoo ChoiThis patch adds the the mux/divider/gate clocks for CMU_DISP domain which includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks related to CMU_DISP should be always on state.
Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp' from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 9 + drivers/clk/samsung/clk-exynos5433.c | 465 ++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 114 ++++- 3 files changed, 577 insertions(+), 11 deletions(-)
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +9 -0
@@ -21,6 +21,8 @@ Required Properties: which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D which generates clocks for G2D/MDMA IPs. + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. - reg: physical base address of the controller and length of memory mapped region.
@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_disp: clock-controller at 0x13b90000 { + compatible = "samsung,exynos5433-cmu-disp"; + reg = <0x13b90000 0x0c04>; + #clock-cells = <1>; + }; + + Example 2: UART controller node that consumes the clock generated by the clock controller.
drivers/clk/samsung/clk-exynos5433.c +455 -10
500 lines not on this page · raw message
include/dt-bindings/clock/exynos5433.h +113 -1
131 lines not on this page · raw message
Signature · 1 line
1.8.5.5
Re: [PATCH 07/19] clk: samsung: exynos5433: Add clocks for CMU_DISP domain
Hi Chanwoo,
Quoted 228 lines · Chanwoo Choi
This patch adds the the mux/divider/gate clocks for
CMU_DISPdomain which includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). TheCMU_DISPclocks is used to need the source clock ofCMU_MIFdomain so, the CMU_MIF's clocks related toCMU_DISPshould be always on state.Also,
CMU_DISPmust need the source clock of 'sclk_hdmi_spdif_disp' fromCMU_TOPdomain. This patch adds the clocks ofCMU_TOPrelated to HDMI.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- .../devicetree/bindings/clock/exynos5433-clock.txt | 9 + drivers/clk/samsung/clk-exynos5433.c | 465 ++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 114 ++++- 3 files changed, 577 insertions(+), 11 deletions(-)Documentation/devicetree/bindings/clock/exynos5433-clock.txt +9
-0@@ -21,6 +21,8 @@ Required Properties: which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D which generates clocks for G2D/MDMA IPs. + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. - reg: physical base address of the controller and length of memory mapped region.@@ -78,6 +80,13 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_disp: clock-controller at 0x13b90000 { + compatible = "samsung,exynos5433-cmu-disp"; + reg = <0x13b90000 0x0c04>; + #clock-cells = <1>; + }; + + Example 2: UART controller node that consumes the clock generated by the clock controller.drivers/clk/samsung/clk-exynos5433.c +128
-10@@ -245,6 +245,8 @@ PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "fin_pll",PNAME (mout_sclk_audio0_p) = {"ioclk_audiocdclk0" ,"fin_pll" ,"mout_aud_pll_user_t" ,}; +PNAME (mout_sclk_hdmi_spdif_p) = {"sclk_audio1" ,"ioclk_spdif_extclk" , }; +static struct samsung_fixed_factor_clock top_fixed_factor_clks[]__initdata = {FFACTOR (0 ,"sclk_bus_pll" ,"fout_bus_pll" ,1 ,1 ,0 ),FFACTOR (0 ,"sclk_mfc_pll" ,"fout_mfc_pll" ,1 ,1 ,0 ),@@ -397,6 +399,10 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = { MUX_SEL_TOP_PERIC1, 4, 2),MUX (CLK_MOUT_SCLK_AUDIO0 ,"mout_sclk_audio0" , mout_sclk_audio0_p,MUX_SEL_TOP_PERIC1 ,0 ,2 ), + +/* MUX_SEL_TOP_DISP */ +MUX (CLK_MOUT_SCLK_HDMI_SPDIF ,"mout_sclk_hdmi_spdif" , + mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), }; static struct samsung_div_clock top_div_clks[] __initdata = {@@ -1256,9 +1262,9 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {/* ENABLE_ACLK_MIF3 */ GATE (CLK_ACLK_BUS2_400 ,"aclk_bus2_400" ,"div_aclk_bus2_400" , -ENABLE_ACLK_MIF3 ,4 ,0 ,0 ), +ENABLE_ACLK_MIF3 ,4 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_ACLK_DISP_333 ,"aclk_disp_333" ,"div_aclk_disp_333" , -ENABLE_ACLK_MIF3 ,1 ,0 ,0 ), +ENABLE_ACLK_MIF3 ,1 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_ACLK_CPIF_200 ,"aclk_cpif_200" ,"div_aclk_cpif_200" , ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED, 0),@@ -1333,21 +1339,30 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {/* ENABLE_SCLK_MIF */ GATE (CLK_SCLK_DSIM1_DISP ,"sclk_dsim1_disp" ,"div_sclk_dsim1" , -ENABLE_SCLK_MIF ,15 ,0 ,0 ), +ENABLE_SCLK_MIF ,15 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_DECON_TV_VCLK_DISP ,"sclk_decon_tv_vclk_disp" , -"div_sclk_decon_tv_vclk" ,ENABLE_SCLK_MIF ,14 ,0 ,0 ), +"div_sclk_decon_tv_vclk" ,ENABLE_SCLK_MIF , +14 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_DSIM0_DISP ,"sclk_dsim0_disp" ,"div_sclk_dsim0" , -ENABLE_SCLK_MIF ,9 ,0 ,0 ), +ENABLE_SCLK_MIF ,9 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_DSD_DISP ,"sclk_dsd_disp" ,"div_sclk_dsd" , -ENABLE_SCLK_MIF ,8 ,0 ,0 ), +ENABLE_SCLK_MIF ,8 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_DECON_TV_ECLK_DISP ,"sclk_decon_tv_eclk_disp" , -"div_sclk_decon_tv_eclk" ,ENABLE_SCLK_MIF ,7 ,0 ,0 ), +"div_sclk_decon_tv_eclk" ,ENABLE_SCLK_MIF , +7 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_DECON_VCLK_DISP ,"sclk_decon_vclk_disp" , -"div_sclk_decon_vclk" ,ENABLE_SCLK_MIF ,6 ,0 ,0 ), +"div_sclk_decon_vclk" ,ENABLE_SCLK_MIF , +6 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_DECON_ECLK_DISP ,"sclk_decon_eclk_disp" , -"div_sclk_decon_eclk" ,ENABLE_SCLK_MIF ,5 ,0 ,0 ), +"div_sclk_decon_eclk" ,ENABLE_SCLK_MIF , +5 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_HPM_MIF ,"sclk_hpm_mif" ,"div_sclk_hpm_mif" , - ENABLE_SCLK_MIF, 4, 0, 0), +ENABLE_SCLK_MIF ,4 ,CLK_IGNORE_UNUSED ,0 ), + +/* ENABLE_SCLK_TOP_DISP */ +GATE (CLK_SCLK_HDMI_SPDIF_DISP ,"sclk_hdmi_spdif_disp" , +"mout_sclk_hdmi_spdif" ,ENABLE_SCLK_TOP_DISP ,0 , + CLK_IGNORE_UNUSED, 0), }; static struct samsung_cmu_info mif_cmu_info __initdata = {@@ -2009,3 +2024,433 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np)CLK_OF_DECLARE (exynos5433_cmu_g2d,"samsung,exynos5433-cmu-g2d" , exynos5433_cmu_g2d_init); + +/* +* Register offset definitions for CMU_DISP +*/ +#define DISP_PLL_LOCK 0x0000 +#define DISP_PLL_CON0 0x0100 +#define DISP_PLL_CON1 0x0104 +#define DISP_PLL_FREQ_DET 0x0108 +#define MUX_SEL_DISP0 0x0200 +#define MUX_SEL_DISP1 0x0204 +#define MUX_SEL_DISP2 0x0208 +#define MUX_SEL_DISP3 0x020c +#define MUX_SEL_DISP4 0x0210 +#define MUX_ENABLE_DISP0 0x0300 +#define MUX_ENABLE_DISP1 0x0304 +#define MUX_ENABLE_DISP2 0x0308 +#define MUX_ENABLE_DISP3 0x030c +#define MUX_ENABLE_DISP4 0x0310 +#define MUX_STAT_DISP0 0x0400 +#define MUX_STAT_DISP1 0x0404 +#define MUX_STAT_DISP2 0x0408 +#define MUX_STAT_DISP3 0x040c +#define MUX_STAT_DISP4 0x0410 +#define MUX_IGNORE_DISP2 0x0508 +#define DIV_DISP 0x0600 +#define DIV_DISP_PLL_FREQ_DET 0x0604 +#define DIV_STAT_DISP 0x0700 +#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 +#define ENABLE_ACLK_DISP0 0x0800 +#define ENABLE_ACLK_DISP1 0x0804 +#define ENABLE_PCLK_DISP 0x0900 +#define ENABLE_SCLK_DISP 0x0a00 +#define ENABLE_IP_DISP0 0x0b00 +#define ENABLE_IP_DISP1 0x0b04 +#define CLKOUT_CMU_DISP 0x0c00 +#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 + +static unsigned long disp_clk_regs[]__initdata = { +DISP_PLL_LOCK , +DISP_PLL_CON0 , +DISP_PLL_CON1 , +DISP_PLL_FREQ_DET , +MUX_SEL_DISP0 , +MUX_SEL_DISP1 , +MUX_SEL_DISP2 , +MUX_SEL_DISP3 , +MUX_SEL_DISP4 , +MUX_ENABLE_DISP0 , +MUX_ENABLE_DISP1 , +MUX_ENABLE_DISP2 , +MUX_ENABLE_DISP3 , +MUX_ENABLE_DISP4 , +MUX_STAT_DISP0 , +MUX_STAT_DISP1 , +MUX_STAT_DISP2 , +MUX_STAT_DISP3 , +MUX_STAT_DISP4 , +MUX_IGNORE_DISP2 , +DIV_DISP , +DIV_DISP_PLL_FREQ_DET , +DIV_STAT_DISP , +DIV_STAT_DISP_PLL_FREQ_DET , +ENABLE_ACLK_DISP0 , +ENABLE_ACLK_DISP1 , +ENABLE_PCLK_DISP , +ENABLE_SCLK_DISP , +ENABLE_IP_DISP0 , +ENABLE_IP_DISP1 , +CLKOUT_CMU_DISP , +CLKOUT_CMU_DISP_DIV_STAT , +}; + +/* list of all parent clock list */ +PNAME (mout_disp_pll_p) = {"fin_pll" ,"fout_disp_pll" , }; +PNAME (mout_sclk_dsim1_user_p) = {"fin_pll" ,"sclk_dsim1_disp" , }; +PNAME (mout_sclk_dsim0_user_p) = {"fin_pll" ,"sclk_dsim0_disp" , }; +PNAME (mout_sclk_dsd_user_p) = {"fin_pll" ,"sclk_dsd_disp" , }; +PNAME (mout_sclk_decon_tv_eclk_user_p) = {"fin_pll" , +"sclk_decon_tv_eclk_disp" , }; +PNAME (mout_sclk_decon_vclk_user_p) = {"fin_pll" , +"sclk_decon_vclk_disp" , }; +PNAME (mout_sclk_decon_eclk_user_p) = {"fin_pll" , +"sclk_decon_eclk_disp" , }; +PNAME (mout_sclk_decon_tv_vlkc_user_p) = {"fin_pll" , +"sclk_decon_tv_vclk_disp" , }; +PNAME (mout_aclk_disp_333_user_p) = {"fin_pll" ,"aclk_disp_333" , }; + +PNAME (mout_phyclk_mipidphy1_bitclkdiv8_user_p) = {"fin_pll" , +"phyclk_mipidphy1_bitclkdiv8_phy" , }; +PNAME (mout_phyclk_mipidphy1_rxclkesc0_user_p) = {"fin_pll" , +"phyclk_mipidphy1_rxclkesc0_phy" , }; +PNAME (mout_phyclk_mipidphy0_bitclkdiv8_user_p) = {"fin_pll" , +"phyclk_mipidphy0_bitclkdiv8_phy" , }; +PNAME (mout_phyclk_mipidphy0_rxclkesc0_user_p) = {"fin_pll" , +"phyclk_mipidphy0_rxclkesc0_phy" , }; +PNAME (mout_phyclk_hdmiphy_tmds_clko_user_p) = {"fin_pll" , +"phyclk_hdmiphy_tmds_clko_phy" , }; +PNAME (mout_phyclk_hdmiphy_pixel_clko_user_p) = {"fin_pll" , +"phyclk_hdmiphy_pixel_clko_phy" , }; + +PNAME (mout_sclk_dsim0_p) = {"mout_disp_pll" , +"mout_sclk_dsim0_user" , }; +PNAME (mout_sclk_decon_tv_eclk_p) = {"mout_disp_pll" ,
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_g2d_init(struct device_node *np) · line 2139
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+ "mout_sclk_decon_tv_eclk_user", }; +PNAME (mout_sclk_decon_vclk_p) = {"mout_disp_pll" , +"mout_sclk_decon_vclk_user" , }; +PNAME (mout_sclk_decon_eclk_p) = {"mout_disp_pll" , +"mout_sclk_decon_eclk_user" , }; + +PNAME (mout_sclk_dsim1_b_disp_p) = {"mout_sclk_dsim1_a_disp" , +"mout_sclk_dsim1_user" , }; +PNAME (mout_sclk_dsim1_a_disp_p) = {"mout_disp_pll" , +"mout_sclk_dsim0_user" , };
mout_sclk_dsim1_a_disp_p and mout_sclk_dsim0_p has same parent list, so one can be dropped.
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_g2d_init(struct device_node *np) · line 2147
Quoted 8 lines
drivers/clk/samsung/clk-exynos5433.c +8
-0+PNAME (mout_sclk_decon_tv_vclk_c_disp_p) = { +"mout_phyclk_hdmiphy_pixel_clko_user" , +"mout_sclk_decon_tv_vclk_b_disp" , }; +PNAME (mout_sclk_decon_tv_vclk_b_disp_p) = {"mout_sclk_decon_tv_vclk_a_disp" , +"mout_sclk_decon_tv_vclk_user" , }; +PNAME (mout_sclk_decon_tv_vclk_a_disp_p) = {"mout_disp_pll" , +"mout_sclk_decon_vclk_user" , }; +
mout_sclk_decon_tv_vclk_a_disp_p and mout_sclk_decon_vclk_p has same parent list, so one of them can be dropped.
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_g2d_init(struct device_node *np) · line 2156
Quoted 9 lines
drivers/clk/samsung/clk-exynos5433.c +9
-0+static struct samsung_pll_clock disp_pll_clks[]__initdata = { +PLL (pll_35xx,CLK_FOUT_DISP_PLL ,"fout_disp_pll" ,"fin_pll" , +DISP_PLL_LOCK ,DISP_PLL_CON0 , exynos5443_pll_rates), +}; + +static struct samsung_fixed_factor_clock disp_fixed_factor_clks[]__initdata = { +/* +* sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. +* The divider has fixed value (2) betwwen sclk_rgb_{vclk|tv_vclk}
typo: %s/betwwen/between
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_g2d_init(struct device_node *np) · line 2164
Quoted 8 lines
drivers/clk/samsung/clk-exynos5433.c +8
-0+* and sclk_decon_{vclk|tv_vclk}. +*/ +FFACTOR (CLK_SCLK_RGB_VCLK ,"sclk_rgb_vclk" ,"sclk_decon_vclk" , +1 ,2 ,0 ), +FFACTOR (CLK_SCLK_RGB_TV_VCLK ,"sclk_rgb_tv_vclk" ,"sclk_decon_tv_vclk" , + 1, 2, 0), +}; +
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 8/19 clk: samsung: exynos5433: Add clocks for CMU_AUD domain
In reply to Chanwoo ChoiThis patch adds the mux/divider/gate clocks for CMU_AUD domain which includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 7 + drivers/clk/samsung/clk-exynos5433.c | 173 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 53 +++++++ 3 files changed, 233 insertions(+)
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +7 -0
@@ -23,6 +23,8 @@ Required Properties: which generates clocks for G2D/MDMA IPs. - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD + which generates clocks for Cortex-A5/BUS/AUDIO clocks. - reg: physical base address of the controller and length of memory mapped region.
@@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_aud: clock-controller at 0x114c0000 { + compatible = "samsung,exynos5433-cmu-aud"; + reg = <0x114c0000 0x0b04>; + #clock-cells = <1>; + }; Example 2: UART controller node that consumes the clock generated by the clock controller.
drivers/clk/samsung/clk-exynos5433.c +173 -0
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include/dt-bindings/clock/exynos5433.h +53 -0
57 lines not on this page · raw message
Signature · 1 line
1.8.5.5
Re: [PATCH 08/19] clk: samsung: exynos5433: Add clocks for CMU_AUD domain
Hi Chanwoo,
Quoted 2 lines · Chanwoo Choi
This patch adds the mux/divider/gate clocks for
CMU_AUDdomain which includes the clocks of Cortex-A6/Bus/Audio clocks.
Cortex-A6? I think it should be Cortex-A5?
Quoted 17 lines
Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- .../devicetree/bindings/clock/exynos5433-clock.txt | 7 + drivers/clk/samsung/clk-exynos5433.c | 173 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 53 +++++++ 3 files changed, 233 insertions(+)Documentation/devicetree/bindings/clock/exynos5433-clock.txt +0
-0
Documentation/devicetree/bindings/clock/exynos5433-clock.txt Required Properties: · line 27
Quoted 5 lines
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +2
-0@@ -23,6 +23,8 @@ Required Properties: which generates clocks for G2D/MDMA IPs. - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD + which generates clocks for Cortex-A5/BUS/AUDIO clocks.
Commit message says Cortex-A6?
Quoted 55 lines
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +5
-0- reg: physical base address of the controller and length of memory mapped region.@@ -86,6 +88,11 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_aud: clock-controller at 0x114c0000 { + compatible = "samsung,exynos5433-cmu-aud"; + reg = <0x114c0000 0x0b04>; + #clock-cells = <1>; + }; Example 2: UART controller node that consumes the clock generated by the clock controller.drivers/clk/samsung/clk-exynos5433.c +32
-0@@ -2454,3 +2454,176 @@ static void __init exynos5433_cmu_disp_init(struct device_node *np)CLK_OF_DECLARE (exynos5433_cmu_disp,"samsung,exynos5433-cmu-disp" , exynos5433_cmu_disp_init); + +/* +* Register offset definitions for CMU_AUD +*/ +#define MUX_SEL_AUD0 0x0200 +#define MUX_SEL_AUD1 0x0204 +#define MUX_ENABLE_AUD0 0x0300 +#define MUX_ENABLE_AUD1 0x0304 +#define MUX_STAT_AUD0 0x0400 +#define DIV_AUD0 0x0600 +#define DIV_AUD1 0x0604 +#define DIV_STAT_AUD0 0x0700 +#define DIV_STAT_AUD1 0x0704 +#define ENABLE_ACLK_AUD 0x0800 +#define ENABLE_PCLK_AUD 0x0900 +#define ENABLE_SCLK_AUD0 0x0a00 +#define ENABLE_SCLK_AUD1 0x0a04 +#define ENABLE_IP_AUD0 0x0b00 +#define ENABLE_IP_AUD1 0x0b04 + +static unsigned long aud_clk_regs[]__initdata = { +MUX_SEL_AUD0 , +MUX_SEL_AUD1 , +MUX_ENABLE_AUD0 , +MUX_ENABLE_AUD1 , +MUX_STAT_AUD0 , +DIV_AUD0 , +DIV_AUD1 , +DIV_STAT_AUD0 , +DIV_STAT_AUD1 , +ENABLE_ACLK_AUD , +ENABLE_PCLK_AUD ,
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_disp_init(struct device_node *np) · line 2498
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+ENABLE_SCLK_AUD0 , +ENABLE_SCLK_AUD1 , +ENABLE_IP_AUD0 , + ENABLE_IP_AUD1, +}; + +/* list of all parent clock list */ +PNAME (mout_aud_pll_user_aud_p) = {"fin_pll" ,"fout_aud_pll" , }; +PNAME (mout_sclk_aud_pcm_p) = {"mout_aud_pll_user" ,"ioclk_audiocdclk0" ,}; +PNAME (mout_sclk_aud_i2s_p) = {"mout_aud_pll_user" ,"ioclk_audiocdclk0" ,};
Above two lines can be clubbed with some common name as both has same parent clocks.
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_disp_init(struct device_node *np) · line 2503
Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c +5
-0+ +static struct samsung_fixed_rate_clock aud_fixed_clks[]__initdata = { +FRATE (0 ,"ioclk_jtag_tclk" ,NULL ,CLK_IS_ROOT ,188000000 ), +FRATE (0 ,"ioclk_slimbus_clk" ,NULL ,CLK_IS_ROOT ,188000000 ), +FRATE (0 ,"ioclk_i2s_bclk" ,NULL ,CLK_IS_ROOT ,188000000 ),
Are you sure about these clock rates?
As per UM I have, these are having rates as 33 MHz, 25 MHz and 50 MHz respectively.
Quoted 4 lines
drivers/clk/samsung/clk-exynos5433.c +4
-0+}; + +static struct samsung_mux_clock aud_mux_clks[]__initdata = { +/* MUX_SEL_AUD0 */
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_disp_init(struct device_node *np) · line 2517
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+MUX (CLK_MOUT_AUD_PLL_USER ,"mout_aud_pll_user" , + mout_aud_pll_user_aud_p,MUX_SEL_AUD0 ,0 ,1 ), + +/* MUX_SEL_AUD1 */ +MUX (CLK_MOUT_SCLK_AUD_PCM ,"mout_sclk_aud_pcm" , mout_sclk_aud_pcm_p, +MUX_SEL_AUD1 ,8 ,1 ), +MUX (CLK_MOUT_SCLK_AUD_I2S ,"mout_sclk_aud_i2s" , mout_sclk_aud_i2s_p, + MUX_SEL_AUD1, 0, 1), +}; +
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 9/19 clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
In reply to Chanwoo ChoiThis patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains which contain global data buses clocked at up the 400MHz. These blocks transfer data between DRAM and various sub-blocks. These clock domains also contain global peripheral buses clocked at 67/111/200/222/266/333/400 MHz and used for regiser accesses.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Cc Arnd Bergmann <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 21 +++ drivers/clk/samsung/clk-exynos5433.c | 185 ++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 29 +++- 3 files changed, 232 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +21 -0
@@ -25,6 +25,9 @@ Required Properties: which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD which generates clocks for Cortex-A5/BUS/AUDIO clocks. + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS + which generates global data buses clock and global peripheral buses clock. - reg: physical base address of the controller and length of memory mapped region.
@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_bus0: clock-controller at 0x13600000 { + compatible = "samsung,exynos5433-cmu-bus0"; + reg = <0x13600000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus1: clock-controller at 0x14800000 { + compatible = "samsung,exynos5433-cmu-bus1"; + reg = <0x14800000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus2: clock-controller at 0x13400000 { + compatible = "samsung,exynos5433-cmu-bus2"; + reg = <0x13400000 0x0b04>; + #clock-cells = <1>; + }; + Example 2: UART controller node that consumes the clock generated by the clock controller.
drivers/clk/samsung/clk-exynos5433.c +184 -1
206 lines not on this page · raw message
include/dt-bindings/clock/exynos5433.h +27 -2
@@ -71,7 +71,7 @@#define CLK_MOUT_SCLK_HDMI_SPDIF 64#define CLK_DIV_ACLK_FSYS_200 100 -#define CLK_DIV_ACLK_IMEM_SSSX 101 +#define CLK_DIV_ACLK_IMEM_SSSX_266 101#define CLK_DIV_ACLK_IMEM_200 102#define CLK_DIV_ACLK_IMEM_266 103#define CLK_DIV_ACLK_PERIC_66_B 104
@@ -107,6 +107,9 @@#define CLK_DIV_ACLK_MFC_400 134#define CLK_DIV_ACLK_G2D_266 135#define CLK_DIV_ACLK_G2D_400 136 +#define CLK_DIV_ACLK_G3D_400 137 +#define CLK_DIV_ACLK_BUS0_400 138 +#define CLK_DIV_ACLK_BUS1_400 139#define CLK_ACLK_PERIC_66 200#define CLK_ACLK_PERIS_66 201
@@ -130,8 +133,14 @@#define CLK_SCLK_AUDIO0 219#define CLK_ACLK_G2D_266 220#define CLK_ACLK_G2D_400 221 +#define CLK_ACLK_G3D_400 222 +#define CLK_ACLK_IMEM_SSX_266 223 +#define CLK_ACLK_BUS0_400 224 +#define CLK_ACLK_BUS1_400 225 +#define CLK_ACLK_IMEM_200 226 +#define CLK_ACLK_IMEM_266 227 -#define TOP_NR_CLK 222 +#define TOP_NR_CLK 228/* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1
@@ -679,4 +688,20 @@#define AUD_NR_CLK 48 +/* CMU_BUS{0|1|2} */ +#define CLK_DIV_PCLK_BUS_133 1 + +#define CLK_ACLK_AHB2APB_BUSP 2 +#define CLK_ACLK_BUSNP_133 3 +#define CLK_ACLK_BUSND_400 4 +#define CLK_PCLK_BUSSRVND_133 5 +#define CLK_PCLK_PMU_BUS 6 +#define CLK_PCLK_SYSREG_BUS 7 + +#define CLK_MOUT_ACLK_BUS2_400_USER 8/* Only CMU_BUS2 */ +#define CLK_ACLK_BUS2BEND_400 9/* Only CMU_BUS2 */ +#define CLK_ACLK_BUS2RTND_400 10/* Only CMU_BUS2 */ + +#define BUSx_NR_CLK 11 +#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
Signature · 1 line
1.8.5.5
Re: [PATCH 09/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
Hi Chanwoo,
Quoted 5 lines · Chanwoo Choi
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains which contain global data buses clocked at up the 400MHz. These blocks transfer data between DRAM and various sub-blocks. These clock domains also contain global peripheral buses clocked at 67/111/200/222/266/333/400 MHz and used for regiser accesses.
typo: %s/regiser/register
Quoted 57 lines
Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Cc Arnd Bergmann <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- .../devicetree/bindings/clock/exynos5433-clock.txt | 21 +++ drivers/clk/samsung/clk-exynos5433.c | 185 ++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 29 +++- 3 files changed, 232 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/clock/exynos5433-clock.txt +21
-0@@ -25,6 +25,9 @@ Required Properties: which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD which generates clocks for Cortex-A5/BUS/AUDIO clocks. + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS + which generates global data buses clock and global peripheral buses clock. - reg: physical base address of the controller and length of memory mapped region.@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_bus0: clock-controller@0x13600000 { + compatible = "samsung,exynos5433-cmu-bus0"; + reg = <0x13600000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus1: clock-controller@0x14800000 { + compatible = "samsung,exynos5433-cmu-bus1"; + reg = <0x14800000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus2: clock-controller@0x13400000 { + compatible = "samsung,exynos5433-cmu-bus2"; + reg = <0x13400000 0x0b04>; + #clock-cells = <1>; + }; + Example 2: UART controller node that consumes the clock generated by the clock controller.drivers/clk/samsung/clk-exynos5433.c +0
-0
drivers/clk/samsung/clk-exynos5433.c static struct samsung_div_clock top_div_clks[] __initdata = { · line 428
Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c +1
-1@@ -425,7 +425,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = { DIV_TOP2, 0, 3),/* DIV_TOP3 */ - DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx", + DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
This change can be moved to patch 1/19 itself.
Quoted 5 lines
drivers/clk/samsung/clk-exynos5433.c +0
-0"mout_bus_pll_user", DIV_TOP3, 24, 3),DIV (CLK_DIV_ACLK_IMEM_200 ,"div_aclk_imem_200" , "mout_bus_pll_user", DIV_TOP3, 20, 3),@@ -440,6 +440,14 @@ static struct samsung_div_clock top_div_clks[] __initdata = { DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
drivers/clk/samsung/clk-exynos5433.c static struct samsung_div_clock top_div_clks[] __initdata = { · line 450
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +8
-0"mout_bus_pll_user", DIV_TOP3, 0, 3), +/* DIV_TOP4 */ +DIV (CLK_DIV_ACLK_G3D_400 ,"div_aclk_g3d_400" ,"mout_bus_pll_user" , +DIV_TOP4 ,8 ,3 ), +DIV (CLK_DIV_ACLK_BUS0_400 ,"div_aclk_bus0_400" ,"mout_aclk_bus0_400" , +DIV_TOP4 ,4 ,3 ), +DIV (CLK_DIV_ACLK_BUS1_400 ,"div_aclk_bus1_400" ,"mout_bus_pll_user" , + DIV_TOP4, 0, 3), +
With these changes you can have:
Reviewed-by Pankaj Dubey <[email protected]>
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 10/19 clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
In reply to Chanwoo ChoiThis patch adds the mux/divider/gate clocks for CMU_FSYS domain which contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- drivers/clk/samsung/clk-exynos5433.c | 286 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 82 +++++++++- 2 files changed, 365 insertions(+), 3 deletions(-)
drivers/clk/samsung/clk-exynos5433.c +286 -0
@@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata = {DIV (CLK_DIV_SCLK_MMC2_A ,"div_sclk_mmc2_a" ,"mout_sclk_mmc2_b" ,DIV_TOP_FSYS1 ,0 ,4 ), +/* DIV_TOP_FSYS2 */ +DIV (CLK_DIV_SCLK_PCIE_100 ,"div_sclk_pcie_100" ,"mout_sclk_pcie_100" , +DIV_TOP_FSYS2 ,12 ,3 ), +DIV (CLK_DIV_SCLK_USBHOST30 ,"div_sclk_usbhost30" , +"mout_sclk_usbhost30" ,DIV_TOP_FSYS2 ,8 ,4 ), +DIV (CLK_DIV_SCLK_UFSUNIPRO ,"div_sclk_ufsunipro" , +"mout_sclk_ufsunipro" ,DIV_TOP_FSYS2 ,4 ,4 ), +DIV (CLK_DIV_SCLK_USBDRD30 ,"div_sclk_usbdrd30" ,"mout_sclk_usbdrd30" , +DIV_TOP_FSYS2 ,0 ,4 ), +/* DIV_TOP_PERIC0 */ DIV (CLK_DIV_SCLK_SPI1_B ,"div_sclk_spi1_b" ,"div_sclk_spi1_a" , DIV_TOP_PERIC0, 16, 8),
@@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),/* ENABLE_SCLK_TOP_FSYS */ +GATE (CLK_SCLK_PCIE_100_FSYS ,"sclk_pcie_100_fsys" ,"div_sclk_pcie_100" , +ENABLE_SCLK_TOP_FSYS ,7 ,0 ,0 ),GATE (CLK_SCLK_MMC2_FSYS ,"sclk_mmc2_fsys" ,"div_sclk_mmc2_b" ,ENABLE_SCLK_TOP_FSYS ,6 ,0 ,0 ),GATE (CLK_SCLK_MMC1_FSYS ,"sclk_mmc1_fsys" ,"div_sclk_mmc1_b" ,ENABLE_SCLK_TOP_FSYS ,5 ,0 ,0 ),GATE (CLK_SCLK_MMC0_FSYS ,"sclk_mmc0_fsys" ,"div_sclk_mmc0_b" ,ENABLE_SCLK_TOP_FSYS ,4 ,0 ,0 ), +GATE (CLK_SCLK_UFSUNIPRO_FSYS ,"sclk_ufsunipro_fsys" , +"div_sclk_ufsunipro" ,ENABLE_SCLK_TOP_FSYS ,7 ,0 ,0 ), +GATE (CLK_SCLK_USBHOST30_FSYS ,"sclk_usbhost30_fsys" , +"div_sclk_usbhost30" ,ENABLE_SCLK_TOP_FSYS ,7 ,0 ,0 ), +GATE (CLK_SCLK_USBDRD30_FSYS ,"sclk_usbdrd30_fsys" , +"div_sclk_usbdrd30" ,ENABLE_SCLK_TOP_FSYS ,7 ,0 ,0 ),/* ENABLE_SCLK_TOP_PERIC */ GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
@@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",#define ENABLE_IP_FSYS1 0x0b04/* list of all parent clock list */ +PNAME (mout_sclk_ufs_mphy_user_p) = {"fin_pll" ,"sclk_ufs_mphy" , };PNAME (mout_aclk_fsys_200_user_p) = {"fin_pll" ,"aclk_fsys_200" , }; +PNAME (mout_sclk_pcie_100_user_p) = {"fin_pll" ,"sclk_ufsunipro_fsys" ,}; +PNAME (mout_sclk_ufsunipro_user_p) = {"fin_pll" ,"sclk_ufsunipro_fsys" ,};PNAME (mout_sclk_mmc2_user_p) = {"fin_pll" ,"sclk_mmc2_fsys" , };PNAME (mout_sclk_mmc1_user_p) = {"fin_pll" ,"sclk_mmc1_fsys" , };PNAME (mout_sclk_mmc0_user_p) = {"fin_pll" ,"sclk_mmc0_fsys" , }; +PNAME (mout_sclk_usbhost30_user_p) = {"fin_pll" ,"sclk_usbhost30_fsys" ,}; +PNAME (mout_sclk_usbdrd30_user_p) = {"fin_pll" ,"sclk_usbdrd30_fsys" , }; + +PNAME (mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_pipe_pclk_phy" , }; +PNAME (mout_phyclk_usbhost30_uhost30_phyclock_user_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_phyclock_phy" , }; +PNAME (mout_phyclk_usbhost20_phy_hsic1_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_hsic1_phy" , }; +PNAME (mout_phyclk_usbhost20_phy_clk48mohci_user_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_clk48mohci_phy" , }; +PNAME (mout_phyclk_usbhost20_phy_phyclock_user_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_phyclock_phy" , }; +PNAME (mout_phyclk_usbhost20_phy_freeclk_user_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_freeclk_phy" , }; +PNAME (mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_pipe_pclk_phy" , }; +PNAME (mout_phyclk_usbdrd30_udrd30_phyclock_user_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_phyclock_phy" , }; +PNAME (mout_phyclk_ufs_rx1_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_rx1_symbol_phy" , }; +PNAME (mout_phyclk_ufs_rx0_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_rx0_symbol_phy" , }; +PNAME (mout_phyclk_ufs_tx1_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_tx1_symbol_phy" , }; +PNAME (mout_phyclk_ufs_tx0_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_tx0_symbol_phy" , }; +PNAME (mout_phyclk_lli_mphy_to_ufs_user_p) + = {"fin_pll" ,"phyclk_lli_mphy_to_ufs_phy" , }; +PNAME (mout_sclk_mphy_p) + = {"mout_sclk_ufs_mphy_user" , +"mout_phyclk_lli_mphy_to_ufs_user" , };static unsigned long fsys_clk_regs[]__initdata = {MUX_SEL_FSYS0 ,
@@ -1850,18 +1903,117 @@ static unsigned long fsys_clk_regs[] __initdata = { ENABLE_IP_FSYS1, }; +static struct samsung_fixed_rate_clock fsys_fixed_clks[]__initdata = { +/* PHY clocks from USBDRD30_PHY */ +FRATE (0 ,"phyclk_usbdrd30_udrd30_phyclock_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +FRATE (0 ,"phyclk_usbdrd30_udrd30_pipe_pclk_phy" ,NULL ,CLK_IS_ROOT , +125000000 ), +/* PHY clocks from USBHOST30_PHY */ +FRATE (0 ,"phyclk_usbhost30_uhost30_phyclock_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +FRATE (0 ,"phyclk_usbhost30_uhost30_pipe_pclk_phy" ,NULL ,CLK_IS_ROOT , +125000000 ), +/* PHY clocks from USBHOST20_PHY */ +FRATE (0 ,"phyclk_usbhost20_phy_freeclk_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +FRATE (0 ,"phyclk_usbhost20_phy_phyclock_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +FRATE (0 ,"phyclk_usbhost20_phy_clk48mohci_phy" ,NULL ,CLK_IS_ROOT , +48000000 ), +FRATE (0 ,"phyclk_usbhost20_phy_hsic1_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +/* PHY clocks from UFS_PHY */ +FRATE (0 ,"phyclk_ufs_tx0_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +FRATE (0 ,"phyclk_ufs_rx0_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +FRATE (0 ,"phyclk_ufs_tx1_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +FRATE (0 ,"phyclk_ufs_rx1_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +/* PHY clocks from LLI_PHY */ +FRATE (0 ,"phyclk_lli_mphy_to_ufs_phy" ,NULL ,CLK_IS_ROOT ,260000000 ), +}; +static struct samsung_mux_clock fsys_mux_clks[]__initdata = {/* MUX_SEL_FSYS0 */ +MUX (CLK_MOUT_SCLK_UFS_MPHY_USER ,"mout_sclk_ufs_mphy_user" , + mout_sclk_ufs_mphy_user_p,MUX_SEL_FSYS0 ,4 ,1 ),MUX (CLK_MOUT_ACLK_FSYS_200_USER ,"mout_aclk_fsys_200_user" , mout_aclk_fsys_200_user_p,MUX_SEL_FSYS0 ,0 ,1 ),/* MUX_SEL_FSYS1 */ +MUX (CLK_MOUT_SCLK_PCIE_100_USER ,"mout_sclk_pcie_100_user" , + mout_sclk_pcie_100_user_p,MUX_SEL_FSYS1 ,28 ,1 ), +MUX (CLK_MOUT_SCLK_UFSUNIPRO_USER ,"mout_sclk_ufsunipro_user" , + mout_sclk_ufsunipro_user_p,MUX_SEL_FSYS1 ,24 ,1 ),MUX (CLK_MOUT_SCLK_MMC2_USER ,"mout_sclk_mmc2_user" , mout_sclk_mmc2_user_p,MUX_SEL_FSYS1 ,20 ,1 ),MUX (CLK_MOUT_SCLK_MMC1_USER ,"mout_sclk_mmc1_user" , mout_sclk_mmc1_user_p,MUX_SEL_FSYS1 ,16 ,1 ),MUX (CLK_MOUT_SCLK_MMC0_USER ,"mout_sclk_mmc0_user" , mout_sclk_mmc0_user_p,MUX_SEL_FSYS1 ,12 ,1 ), +MUX (CLK_MOUT_SCLK_USBHOST30_USER ,"mout_sclk_usbhost30_user" , + mout_sclk_usbhost30_user_p,MUX_SEL_FSYS1 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_USBDRD30_USER ,"mout_sclk_usbdrd30_user" , + mout_sclk_usbdrd30_user_p,MUX_SEL_FSYS1 ,0 ,1 ), + +/* MUX_SEL_FSYS2 */ +MUX (CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER , +"mout_phyclk_usbhost30_uhost30_pipe_pclk_user" , + mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, +MUX_SEL_FSYS2 ,28 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER , +"mout_phyclk_usbhost30_uhost30_phyclock_user" , + mout_phyclk_usbhost30_uhost30_phyclock_user_p, +MUX_SEL_FSYS2 ,24 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER , +"mout_phyclk_usbhost20_phy_hsic1" , + mout_phyclk_usbhost20_phy_hsic1_p, +MUX_SEL_FSYS2 ,20 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER , +"mout_phyclk_usbhost20_phy_clk48mohci_user" , + mout_phyclk_usbhost20_phy_clk48mohci_user_p, +MUX_SEL_FSYS2 ,16 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER , +"mout_phyclk_usbhost20_phy_phyclock_user" , + mout_phyclk_usbhost20_phy_phyclock_user_p, +MUX_SEL_FSYS2 ,12 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER , +"mout_phyclk_usbhost20_phy_freeclk_user" , + mout_phyclk_usbhost20_phy_freeclk_user_p, +MUX_SEL_FSYS2 ,8 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER , +"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user" , + mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, +MUX_SEL_FSYS2 ,4 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER , +"mout_phyclk_usbdrd30_udrd30_phyclock_user" , + mout_phyclk_usbdrd30_udrd30_phyclock_user_p, +MUX_SEL_FSYS2 ,0 ,1 ), + +/* MUX_SEL_FSYS3 */ +MUX (CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER , +"mout_phyclk_ufs_rx1_symbol_user" , + mout_phyclk_ufs_rx1_symbol_user_p, +MUX_SEL_FSYS3 ,16 ,1 ), +MUX (CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER , +"mout_phyclk_ufs_rx0_symbol_user" , + mout_phyclk_ufs_rx0_symbol_user_p, +MUX_SEL_FSYS3 ,12 ,1 ), +MUX (CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER , +"mout_phyclk_ufs_tx1_symbol_user" , + mout_phyclk_ufs_tx1_symbol_user_p, +MUX_SEL_FSYS3 ,8 ,1 ), +MUX (CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER , +"mout_phyclk_ufs_tx0_symbol_user" , + mout_phyclk_ufs_tx0_symbol_user_p, +MUX_SEL_FSYS3 ,4 ,1 ), +MUX (CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER , +"mout_phyclk_lli_mphy_to_ufs_user" , + mout_phyclk_lli_mphy_to_ufs_user_p, +MUX_SEL_FSYS4 ,0 ,1 ), + +/* MUX_SEL_FSYS4 */ +MUX (CLK_MOUT_SCLK_MPHY ,"mout_sclk_mphy" , mout_sclk_mphy_p, +MUX_SEL_FSYS4 ,0 ,1 ), };static struct samsung_gate_clock fsys_gate_clks[]__initdata = {
@@ -1889,13 +2041,145 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {GATE (CLK_ACLK_PDMA0 ,"aclk_pdma0" ,"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS0 ,0 ,CLK_IGNORE_UNUSED ,0 ), +/* ENABLE_ACLK_FSYS1 */ +GATE (CLK_ACLK_XIU_FSYSPX ,"aclk_xiu_fsyspx" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,27 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB_USBLINKH1 ,"aclk_ahb_usblinkh1" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +26 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_SMMU_PDMA1 ,"aclk_smmu_pdma1" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,25 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_BTS_PCIE ,"aclk_bts_pcie" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,24 ,0 ,0 ), +GATE (CLK_ACLK_AXIUS_PDMA1 ,"aclk_axius_pdma1" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +22 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_SMMU_PDMA0 ,"aclk_smmu_pdma0" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,17 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_BTS_UFS ,"aclk_bts_ufs" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,14 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_BTS_USBHOST30 ,"aclk_bts_usbhost30" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +13 ,0 ,0 ), +GATE (CLK_ACLK_BTS_USBDRD30 ,"aclk_bts_usbdrd30" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +12 ,0 ,0 ), +GATE (CLK_ACLK_AXIUS_PDMA0 ,"aclk_axius_pdma0" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +11 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AXIUS_USBHS ,"aclk_axius_usbhs" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +10 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AXIUS_FSYSSX ,"aclk_axius_fsyssx" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +9 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2APB_FSYSP ,"aclk_ahb2apb_fsysp" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +8 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB2AXI_USBHS ,"aclk_ahb2axi_usbhs" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +7 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB_USBLINKH0 ,"aclk_ahb_usblinkh0" , +"mout_aclk_fsys_200_user" ,ENABLE_ACLK_FSYS1 , +6 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB_USBHS ,"aclk_ahb_usbhs" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,5 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_AHB_FSYSH ,"aclk_ahb_fsysh" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,4 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_XIU_FSYSX ,"aclk_xiu_fsysx" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_XIU_FSYSSX ,"aclk_xiu_fsyssx" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_FSYSNP_200 ,"aclk_fsysnp_200" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_ACLK_FSYSND_200 ,"aclk_fsysnd_200" ,"mout_aclk_fsys_200_user" , +ENABLE_ACLK_FSYS1 ,0 ,CLK_IGNORE_UNUSED ,0 ), + +/* ENABLE_PCLK_FSYS */ +GATE (CLK_PCLK_PCIE_CTRL ,"pclk_pcie_ctrl" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,17 ,0 ,0 ), +GATE (CLK_PCLK_SMMU_PDMA1 ,"pclk_smmu_pdma1" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,16 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_PCIE_PHY ,"pclk_pcie_phy" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,14 ,0 ,0 ), +GATE (CLK_PCLK_BTS_PCIE ,"pclk_bts_pcie" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,13 ,0 ,0 ), +GATE (CLK_PCLK_SMMU_PDMA0 ,"pclk_smmu_pdma0" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,8 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_BTS_UFS ,"pclk_bts_ufs" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,5 ,0 ,0 ), +GATE (CLK_PCLK_BTS_USBHOST30 ,"pclk_bts_usbhost30" , +"mout_aclk_fsys_200_user" ,ENABLE_PCLK_FSYS ,4 ,0 ,0 ), +GATE (CLK_PCLK_BTS_USBDRD30 ,"pclk_bts_usbdrd30" , +"mout_aclk_fsys_200_user" ,ENABLE_PCLK_FSYS ,3 ,0 ,0 ), +GATE (CLK_PCLK_GPIO_FSYS ,"pclk_gpio_fsys" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,2 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_PMU_FSYS ,"pclk_pmu_fsys" ,"mout_aclk_fsys_200_user" , +ENABLE_PCLK_FSYS ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_PCLK_SYSREG_FSYS ,"pclk_sysreg_fsys" , +"mout_aclk_fsys_200_user" ,ENABLE_PCLK_FSYS , +0 ,CLK_IGNORE_UNUSED ,0 ), +/* ENABLE_SCLK_FSYS */ +GATE (CLK_SCLK_PCIE_100 ,"sclk_pcie_100" ,"mout_sclk_pcie_100_user" , +ENABLE_SCLK_FSYS ,21 ,0 ,0 ), +GATE (CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK , +"phyclk_usbhost30_uhost30_pipe_pclk" , +"mout_phyclk_usbhost30_uhost30_pipe_pclk_user" , +ENABLE_SCLK_FSYS ,18 ,0 ,0 ), +GATE (CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK , +"phyclk_usbhost30_uhost30_phyclock" , +"mout_phyclk_usbhost30_uhost30_phyclock_user" , +ENABLE_SCLK_FSYS ,17 ,0 ,0 ), +GATE (CLK_PHYCLK_UFS_RX1_SYMBOL ,"phyclk_ufs_rx1_symbol" , +"mout_phyclk_ufs_rx1_symbol_user" ,ENABLE_SCLK_FSYS , +16 ,0 ,0 ), +GATE (CLK_PHYCLK_UFS_RX0_SYMBOL ,"phyclk_ufs_rx0_symbol" , +"mout_phyclk_ufs_rx0_symbol_user" ,ENABLE_SCLK_FSYS , +15 ,0 ,0 ), +GATE (CLK_PHYCLK_UFS_TX1_SYMBOL ,"phyclk_ufs_tx1_symbol" , +"mout_phyclk_ufs_tx1_symbol_user" ,ENABLE_SCLK_FSYS , +14 ,0 ,0 ), +GATE (CLK_PHYCLK_UFS_TX0_SYMBOL ,"phyclk_ufs_tx0_symbol" , +"mout_phyclk_ufs_tx0_symbol_user" ,ENABLE_SCLK_FSYS , +13 ,0 ,0 ), +GATE (CLK_PHYCLK_USBHOST20_PHY_HSIC1 ,"phyclk_usbhost20_phy_hsic1" , +"mout_phyclk_usbhost20_phy_hsic1" ,ENABLE_SCLK_FSYS , +12 ,0 ,0 ), +GATE (CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI , +"phyclk_usbhost20_phy_clk48mohci" , +"mout_phyclk_usbhost20_phy_clk48mohci_user" , +ENABLE_SCLK_FSYS ,11 ,0 ,0 ), +GATE (CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK , +"phyclk_usbhost20_phy_phyclock" , +"mout_phyclk_usbhost20_phy_phyclock_user" , +ENABLE_SCLK_FSYS ,10 ,0 ,0 ), +GATE (CLK_PHYCLK_USBHOST20_PHY_FREECLK , +"phyclk_usbhost20_phy_freeclk" , +"mout_phyclk_usbhost20_phy_freeclk_user" , +ENABLE_SCLK_FSYS ,9 ,0 ,0 ), +GATE (CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK , +"phyclk_usbdrd30_udrd30_pipe_pclk" , +"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user" , +ENABLE_SCLK_FSYS ,8 ,0 ,0 ), +GATE (CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK , +"phyclk_usbdrd30_udrd30_phyclock" , +"mout_phyclk_usbdrd30_udrd30_phyclock_user" , +ENABLE_SCLK_FSYS ,7 ,0 ,0 ), +GATE (CLK_SCLK_MPHY ,"sclk_mphy" ,"mout_sclk_mphy" , +ENABLE_SCLK_FSYS ,6 ,0 ,0 ), +GATE (CLK_SCLK_UFSUNIPRO ,"sclk_ufsunipro" ,"mout_sclk_ufsunipro_user" , +ENABLE_SCLK_FSYS ,5 ,0 ,0 ),GATE (CLK_SCLK_MMC2 ,"sclk_mmc2" ,"mout_sclk_mmc2_user" ,ENABLE_SCLK_FSYS ,4 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_MMC1 ,"sclk_mmc1" ,"mout_sclk_mmc1_user" ,ENABLE_SCLK_FSYS ,3 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_MMC0 ,"sclk_mmc0" ,"mout_sclk_mmc0_user" ,ENABLE_SCLK_FSYS ,2 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_USBHOST30 ,"sclk_usbhost30" ,"mout_sclk_usbhost30_user" , +ENABLE_SCLK_FSYS ,1 ,0 ,0 ), +GATE (CLK_SCLK_USBDRD30 ,"sclk_usbdrd30" ,"mout_sclk_usbdrd30_user" , +ENABLE_SCLK_FSYS ,0 ,0 ,0 ),/* ENABLE_IP_FSYS0 */ GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
@@ -1907,6 +2191,8 @@ static struct samsung_cmu_info fsys_cmu_info __initdata = { .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), .gate_clks = fsys_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), + .fixed_clks = fsys_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), .nr_clk_ids = FSYS_NR_CLK, .clk_regs = fsys_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
include/dt-bindings/clock/exynos5433.h +79 -3
107 lines not on this page · raw message
Signature · 1 line
1.8.5.5
Re: [PATCH 10/19] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
Hi Chanwoo,
Quoted 38 lines · Chanwoo Choi
This patch adds the mux/divider/gate clocks for
CMU_FSYSdomain which contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- drivers/clk/samsung/clk-exynos5433.c | 286 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 82 +++++++++- 2 files changed, 365 insertions(+), 3 deletions(-)drivers/clk/samsung/clk-exynos5433.c +10
-0@@ -464,6 +464,16 @@ static struct samsung_div_clock top_div_clks[] __initdata = {DIV (CLK_DIV_SCLK_MMC2_A ,"div_sclk_mmc2_a" ,"mout_sclk_mmc2_b" ,DIV_TOP_FSYS1 ,0 ,4 ), +/* DIV_TOP_FSYS2 */ +DIV (CLK_DIV_SCLK_PCIE_100 ,"div_sclk_pcie_100" ,"mout_sclk_pcie_100" , +DIV_TOP_FSYS2 ,12 ,3 ), +DIV (CLK_DIV_SCLK_USBHOST30 ,"div_sclk_usbhost30" , +"mout_sclk_usbhost30" ,DIV_TOP_FSYS2 ,8 ,4 ), +DIV (CLK_DIV_SCLK_UFSUNIPRO ,"div_sclk_ufsunipro" , +"mout_sclk_ufsunipro" ,DIV_TOP_FSYS2 ,4 ,4 ), +DIV (CLK_DIV_SCLK_USBDRD30 ,"div_sclk_usbdrd30" ,"mout_sclk_usbdrd30" , +DIV_TOP_FSYS2 ,0 ,4 ), +/* DIV_TOP_PERIC0 */ DIV (CLK_DIV_SCLK_SPI1_B ,"div_sclk_spi1_b" ,"div_sclk_spi1_a" , DIV_TOP_PERIC0, 16, 8),@@ -536,12 +546,20 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { ENABLE_ACLK_TOP, 0, CLK_IGNORE_UNUSED, 0),/* ENABLE_SCLK_TOP_FSYS */
drivers/clk/samsung/clk-exynos5433.c static struct samsung_gate_clock top_gate_clks[] __initdata = { · line 558
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +4
-0+GATE (CLK_SCLK_PCIE_100_FSYS ,"sclk_pcie_100_fsys" ,"div_sclk_pcie_100" , +ENABLE_SCLK_TOP_FSYS ,7 ,0 ,0 ),GATE (CLK_SCLK_MMC2_FSYS ,"sclk_mmc2_fsys" ,"div_sclk_mmc2_b" ,ENABLE_SCLK_TOP_FSYS ,6 ,0 ,0 ),GATE (CLK_SCLK_MMC1_FSYS ,"sclk_mmc1_fsys" ,"div_sclk_mmc1_b" ,ENABLE_SCLK_TOP_FSYS ,5 ,0 ,0 ),GATE (CLK_SCLK_MMC0_FSYS ,"sclk_mmc0_fsys" ,"div_sclk_mmc0_b" ,ENABLE_SCLK_TOP_FSYS ,4 ,0 ,0 ), +GATE (CLK_SCLK_UFSUNIPRO_FSYS ,"sclk_ufsunipro_fsys" , + "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_ufsunipro_fsys is '3'.
drivers/clk/samsung/clk-exynos5433.c static struct samsung_gate_clock top_gate_clks[] __initdata = { · line 560
Quoted 2 lines
drivers/clk/samsung/clk-exynos5433.c +2
-0+GATE (CLK_SCLK_USBHOST30_FSYS ,"sclk_usbhost30_fsys" , + "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_usbhost30_fsys is '1'.
drivers/clk/samsung/clk-exynos5433.c static struct samsung_gate_clock top_gate_clks[] __initdata = { · line 562
Quoted 2 lines
drivers/clk/samsung/clk-exynos5433.c +2
-0+GATE (CLK_SCLK_USBDRD30_FSYS ,"sclk_usbdrd30_fsys" , + "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
bit_index for sclk_usbdrd30_fsys is '0'.
drivers/clk/samsung/clk-exynos5433.c CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", · line 1842
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +2
-0/* ENABLE_SCLK_TOP_PERIC */ GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",@@ -1819,10 +1837,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",#define ENABLE_IP_FSYS1 0x0b04/* list of all parent clock list */ +PNAME (mout_sclk_ufs_mphy_user_p) = {"fin_pll" ,"sclk_ufs_mphy" , };PNAME (mout_aclk_fsys_200_user_p) = {"fin_pll" ,"aclk_fsys_200" , }; +PNAME (mout_sclk_pcie_100_user_p) = {"fin_pll" ,"sclk_ufsunipro_fsys" ,};
This parent list looks wrong.
As per UM, it should be: { "fin_pll", "sclk_pcie_100_fsys",};
Quoted 11 lines
drivers/clk/samsung/clk-exynos5433.c +8
-0+PNAME (mout_sclk_ufsunipro_user_p) = {"fin_pll" ,"sclk_ufsunipro_fsys" ,};PNAME (mout_sclk_mmc2_user_p) = {"fin_pll" ,"sclk_mmc2_fsys" , };PNAME (mout_sclk_mmc1_user_p) = {"fin_pll" ,"sclk_mmc1_fsys" , };PNAME (mout_sclk_mmc0_user_p) = {"fin_pll" ,"sclk_mmc0_fsys" , }; +PNAME (mout_sclk_usbhost30_user_p) = {"fin_pll" ,"sclk_usbhost30_fsys" ,}; +PNAME (mout_sclk_usbdrd30_user_p) = {"fin_pll" ,"sclk_usbdrd30_fsys" , }; + +PNAME (mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_pipe_pclk_phy" , }; +PNAME (mout_phyclk_usbhost30_uhost30_phyclock_user_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_phyclock_phy" , };
drivers/clk/samsung/clk-exynos5433.c CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", · line 1863
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+PNAME (mout_phyclk_usbhost20_phy_hsic1_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_hsic1_phy" , }; +PNAME (mout_phyclk_usbhost20_phy_clk48mohci_user_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_clk48mohci_phy" , }; +PNAME (mout_phyclk_usbhost20_phy_phyclock_user_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_phyclock_phy" , }; +PNAME (mout_phyclk_usbhost20_phy_freeclk_user_p) + = {"fin_pll" ,"phyclk_usbhost20_phy_freeclk_phy" , }; +PNAME (mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_pipe_pclk_phy" , };
Here second parent should be 'phyclk_usbdrd30_udrd30_pipe_pclk_phy'.
drivers/clk/samsung/clk-exynos5433.c CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", · line 1865
Quoted 2 lines
drivers/clk/samsung/clk-exynos5433.c +2
-0+PNAME (mout_phyclk_usbdrd30_udrd30_phyclock_user_p) + = {"fin_pll" ,"phyclk_usbhost30_uhost30_phyclock_phy" , };
Here second parent should be 'phyclk_usbdrd30_udrd30_phyclock_phy'.
Quoted 37 lines
drivers/clk/samsung/clk-exynos5433.c +30
-0+PNAME (mout_phyclk_ufs_rx1_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_rx1_symbol_phy" , }; +PNAME (mout_phyclk_ufs_rx0_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_rx0_symbol_phy" , }; +PNAME (mout_phyclk_ufs_tx1_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_tx1_symbol_phy" , }; +PNAME (mout_phyclk_ufs_tx0_symbol_user_p) + = {"fin_pll" ,"phyclk_ufs_tx0_symbol_phy" , }; +PNAME (mout_phyclk_lli_mphy_to_ufs_user_p) + = {"fin_pll" ,"phyclk_lli_mphy_to_ufs_phy" , }; +PNAME (mout_sclk_mphy_p) + = {"mout_sclk_ufs_mphy_user" , +"mout_phyclk_lli_mphy_to_ufs_user" , };static unsigned long fsys_clk_regs[]__initdata = {MUX_SEL_FSYS0 ,@@ -1850,18 +1903,117 @@ static unsigned long fsys_clk_regs[] __initdata = { ENABLE_IP_FSYS1, }; +static struct samsung_fixed_rate_clock fsys_fixed_clks[]__initdata = { +/* PHY clocks from USBDRD30_PHY */ +FRATE (0 ,"phyclk_usbdrd30_udrd30_phyclock_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +FRATE (0 ,"phyclk_usbdrd30_udrd30_pipe_pclk_phy" ,NULL ,CLK_IS_ROOT , +125000000 ), +/* PHY clocks from USBHOST30_PHY */ +FRATE (0 ,"phyclk_usbhost30_uhost30_phyclock_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +FRATE (0 ,"phyclk_usbhost30_uhost30_pipe_pclk_phy" ,NULL ,CLK_IS_ROOT , +125000000 ), +/* PHY clocks from USBHOST20_PHY */ +FRATE (0 ,"phyclk_usbhost20_phy_freeclk_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +FRATE (0 ,"phyclk_usbhost20_phy_phyclock_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), + FRATE(0, "phyclk_usbhost20_phy_clk48mohci_phy", NULL, CLK_IS_ROOT,
drivers/clk/samsung/clk-exynos5433.c static unsigned long fsys_clk_regs[] __initdata = { · line 1932
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+ 48000000), +FRATE (0 ,"phyclk_usbhost20_phy_hsic1_phy" ,NULL ,CLK_IS_ROOT , +60000000 ), +/* PHY clocks from UFS_PHY */ +FRATE (0 ,"phyclk_ufs_tx0_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +FRATE (0 ,"phyclk_ufs_rx0_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +FRATE (0 ,"phyclk_ufs_tx1_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +FRATE (0 ,"phyclk_ufs_rx1_symbol_phy" ,NULL ,CLK_IS_ROOT ,300000000 ), +/* PHY clocks from LLI_PHY */ + FRATE(0, "phyclk_lli_mphy_to_ufs_phy", NULL, CLK_IS_ROOT, 260000000),
This should be 26 MHz or 260 MHz? Please cross verify.
Quoted 70 lines
drivers/clk/samsung/clk-exynos5433.c +58
-0+}; +static struct samsung_mux_clock fsys_mux_clks[]__initdata = {/* MUX_SEL_FSYS0 */ +MUX (CLK_MOUT_SCLK_UFS_MPHY_USER ,"mout_sclk_ufs_mphy_user" , + mout_sclk_ufs_mphy_user_p,MUX_SEL_FSYS0 ,4 ,1 ),MUX (CLK_MOUT_ACLK_FSYS_200_USER ,"mout_aclk_fsys_200_user" , mout_aclk_fsys_200_user_p,MUX_SEL_FSYS0 ,0 ,1 ),/* MUX_SEL_FSYS1 */ +MUX (CLK_MOUT_SCLK_PCIE_100_USER ,"mout_sclk_pcie_100_user" , + mout_sclk_pcie_100_user_p,MUX_SEL_FSYS1 ,28 ,1 ), +MUX (CLK_MOUT_SCLK_UFSUNIPRO_USER ,"mout_sclk_ufsunipro_user" , + mout_sclk_ufsunipro_user_p,MUX_SEL_FSYS1 ,24 ,1 ),MUX (CLK_MOUT_SCLK_MMC2_USER ,"mout_sclk_mmc2_user" , mout_sclk_mmc2_user_p,MUX_SEL_FSYS1 ,20 ,1 ),MUX (CLK_MOUT_SCLK_MMC1_USER ,"mout_sclk_mmc1_user" , mout_sclk_mmc1_user_p,MUX_SEL_FSYS1 ,16 ,1 ),MUX (CLK_MOUT_SCLK_MMC0_USER ,"mout_sclk_mmc0_user" , mout_sclk_mmc0_user_p,MUX_SEL_FSYS1 ,12 ,1 ), +MUX (CLK_MOUT_SCLK_USBHOST30_USER ,"mout_sclk_usbhost30_user" , + mout_sclk_usbhost30_user_p,MUX_SEL_FSYS1 ,4 ,1 ), +MUX (CLK_MOUT_SCLK_USBDRD30_USER ,"mout_sclk_usbdrd30_user" , + mout_sclk_usbdrd30_user_p,MUX_SEL_FSYS1 ,0 ,1 ), + +/* MUX_SEL_FSYS2 */ +MUX (CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER , +"mout_phyclk_usbhost30_uhost30_pipe_pclk_user" , + mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, +MUX_SEL_FSYS2 ,28 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER , +"mout_phyclk_usbhost30_uhost30_phyclock_user" , + mout_phyclk_usbhost30_uhost30_phyclock_user_p, +MUX_SEL_FSYS2 ,24 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER , +"mout_phyclk_usbhost20_phy_hsic1" , + mout_phyclk_usbhost20_phy_hsic1_p, +MUX_SEL_FSYS2 ,20 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER , +"mout_phyclk_usbhost20_phy_clk48mohci_user" , + mout_phyclk_usbhost20_phy_clk48mohci_user_p, +MUX_SEL_FSYS2 ,16 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER , +"mout_phyclk_usbhost20_phy_phyclock_user" , + mout_phyclk_usbhost20_phy_phyclock_user_p, +MUX_SEL_FSYS2 ,12 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER , +"mout_phyclk_usbhost20_phy_freeclk_user" , + mout_phyclk_usbhost20_phy_freeclk_user_p, +MUX_SEL_FSYS2 ,8 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER , +"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user" , + mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, +MUX_SEL_FSYS2 ,4 ,1 ), +MUX (CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER , +"mout_phyclk_usbdrd30_udrd30_phyclock_user" , + mout_phyclk_usbdrd30_udrd30_phyclock_user_p, +MUX_SEL_FSYS2 ,0 ,1 ), + +/* MUX_SEL_FSYS3 */ +MUX (CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER , +"mout_phyclk_ufs_rx1_symbol_user" , + mout_phyclk_ufs_rx1_symbol_user_p, +MUX_SEL_FSYS3 ,16 ,1 ), +MUX (CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER , +"mout_phyclk_ufs_rx0_symbol_user" , + mout_phyclk_ufs_rx0_symbol_user_p, +MUX_SEL_FSYS3 ,12 ,1 ), + MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, + "mout_phyclk_ufs_tx1_symbol_user",
drivers/clk/samsung/clk-exynos5433.c static unsigned long fsys_clk_regs[] __initdata = { · line 2012
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+ mout_phyclk_ufs_tx1_symbol_user_p, + MUX_SEL_FSYS3, 8, 1), +MUX (CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER , +"mout_phyclk_ufs_tx0_symbol_user" , + mout_phyclk_ufs_tx0_symbol_user_p, +MUX_SEL_FSYS3 ,4 ,1 ), +MUX (CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER , +"mout_phyclk_lli_mphy_to_ufs_user" , + mout_phyclk_lli_mphy_to_ufs_user_p, + MUX_SEL_FSYS4, 0, 1),
Please change MUX_SEL_FSYS4 -> MUX_SEL_FSYS3
drivers/clk/samsung/clk-exynos5433.c static unsigned long fsys_clk_regs[] __initdata = { · line 2018
Quoted 6 lines
drivers/clk/samsung/clk-exynos5433.c +4
-0+ +/* MUX_SEL_FSYS4 */ + MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, + MUX_SEL_FSYS4, 0, 1), };
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 11/19 clk: samsung: exynos5433: Add clocks for CMU_G3D domain
In reply to Chanwoo ChoiThis patch adds the mux/divider/gate clocks for CMU_G3D domain which contains the clocks for GPU(3D Graphics Engine).
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 127 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 25 ++++ 3 files changed, 160 insertions(+)
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +8 -0
@@ -28,6 +28,8 @@ Required Properties: - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS which generates global data buses clock and global peripheral buses clock. + - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D + which generates clocks for 3D Graphics Engine IP. - reg: physical base address of the controller and length of memory mapped region.
@@ -115,6 +117,12 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_g3d: clock-controller at 0x14aa0000 { + compatible = "samsung,exynos5433-cmu-g3d"; + reg = <0x14aa0000 0x1000>; + #clock-cells = <1>; + }; + Example 2: UART controller node that consumes the clock generated by the clock controller.
drivers/clk/samsung/clk-exynos5433.c +127 -0
130 lines not on this page · raw message
include/dt-bindings/clock/exynos5433.h +25 -0
@@ -780,4 +780,29 @@#define BUSx_NR_CLK 11 +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 + +#define CLK_MOUT_ACLK_G3D_400 2 +#define CLK_MOUT_G3D_PLL 3 + +#define CLK_DIV_SCLK_HPM_G3D 4 +#define CLK_DIV_PCLK_G3D 5 +#define CLK_DIV_ACLK_G3D 6 +#define CLK_ACLK_BTS_G3D1 7 +#define CLK_ACLK_BTS_G3D0 8 +#define CLK_ACLK_ASYNCAPBS_G3D 9 +#define CLK_ACLK_ASYNCAPBM_G3D 10 +#define CLK_ACLK_AHB2APB_G3DP 11 +#define CLK_ACLK_G3DNP_150 12 +#define CLK_ACLK_G3DND_600 13 +#define CLK_ACLK_G3D 14 +#define CLK_PCLK_BTS_G3D1 15 +#define CLK_PCLK_BTS_G3D0 16 +#define CLK_PCLK_PMU_G3D 17 +#define CLK_PCLK_SYSREG_G3D 18 +#define CLK_SCLK_HPM_G3D 19 + +#define G3D_NR_CLK 20 +#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
Signature · 1 line
1.8.5.5
Re: [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
Hi Chanwoo,
Quoted 8 lines · Chanwoo Choi
This patch adds the mux/divider/gate clocks for
CMU_G3Ddomain which contains the clocks for GPU(3D Graphics Engine).Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>
Reviewed-by Pankaj Dubey <[email protected]>
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 12/19 clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
In reply to Chanwoo ChoiThis patch adds the divider/gate of CMU_GSCL domain which contains gscaler clocks.
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 37 +++++- 3 files changed, 188 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos5433-clock.txt +8 -0
@@ -30,6 +30,8 @@ Required Properties: which generates global data buses clock and global peripheral buses clock. - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D which generates clocks for 3D Graphics Engine IP. + - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL + which generates clocks for GSCALER IPs. - reg: physical base address of the controller and length of memory mapped region.
@@ -123,6 +125,12 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; + cmu_gscl: clock-controller at 0x13cf0000 { + compatible = "samsung,exynos5433-cmu-gscl"; + reg = <0x13cf0000 0x0b10>; + #clock-cells = <1>; + }; + Example 2: UART controller node that consumes the clock generated by the clock controller.
drivers/clk/samsung/clk-exynos5433.c +144 -0
153 lines not on this page · raw message
include/dt-bindings/clock/exynos5433.h +36 -1
@@ -147,8 +147,10 @@#define CLK_SCLK_UFSUNIPRO_FSYS 229#define CLK_SCLK_USBHOST30_FSYS 230#define CLK_SCLK_USBDRD30_FSYS 231 +#define CLK_ACLK_GSCL_111 232 +#define CLK_ACLK_GSCL_333 233 -#define TOP_NR_CLK 232 +#define TOP_NR_CLK 234/* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1
@@ -805,4 +807,37 @@#define G3D_NR_CLK 20 +/* CMU_GSCL */ +#define CLK_MOUT_ACLK_GSCL_111_USER 1 +#define CLK_MOUT_ACLK_GSCL_333_USER 2 + +#define CLK_ACLK_BTS_GSCL2 3 +#define CLK_ACLK_BTS_GSCL1 4 +#define CLK_ACLK_BTS_GSCL0 5 +#define CLK_ACLK_AHB2APB_GSCLP 6 +#define CLK_ACLK_XIU_GSCLX 7 +#define CLK_ACLK_GSCLNP_111 8 +#define CLK_ACLK_GSCLRTND_333 9 +#define CLK_ACLK_GSCLBEND_333 10 +#define CLK_ACLK_GSD 11 +#define CLK_ACLK_GSCL2 12 +#define CLK_ACLK_GSCL1 13 +#define CLK_ACLK_GSCL0 14 +#define CLK_ACLK_SMMU_GSCL0 15 +#define CLK_ACLK_SMMU_GSCL1 16 +#define CLK_ACLK_SMMU_GSCL2 17 +#define CLK_PCLK_BTS_GSCL2 18 +#define CLK_PCLK_BTS_GSCL1 19 +#define CLK_PCLK_BTS_GSCL0 20 +#define CLK_PCLK_PMU_GSCL 21 +#define CLK_PCLK_SYSREG_GSCL 22 +#define CLK_PCLK_GSCL2 23 +#define CLK_PCLK_GSCL1 24 +#define CLK_PCLK_GSCL0 25 +#define CLK_PCLK_SMMU_GSCL0 26 +#define CLK_PCLK_SMMU_GSCL1 27 +#define CLK_PCLK_SMMU_GSCL2 28 + +#define GSCL_NR_CLK 29 +#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
Signature · 1 line
1.8.5.5
Re: [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
Hi Chanwoo,
Quoted 14 lines · Chanwoo Choi
This patch adds the divider/gate of
CMU_GSCLdomain which contains gscaler clocks.Cc Sylwester Nawrocki <[email protected]>Cc Tomasz Figa <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++ drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 37 +++++- 3 files changed, 188 insertions(+), 1 deletion(-)
[snip]
Quoted 14 lines
} CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d", exynos5433_cmu_g3d_init);drivers/clk/samsung/clk-exynos5433.c +11
-0+ +/* +* Register offset definitions for CMU_GSCL +*/ +#define MUX_SEL_GSCL 0x0200 +#define MUX_ENABLE_GSCL 0x0300 +#define MUX_STAT_GSCL 0x0400 +#define ENABLE_ACLK_GSCL 0x0800 +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_g3d_init(struct device_node *np) · line 3250
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+#define ENABLE_PCLK_GSCL 0x0900 +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c +#define ENABLE_IP_GSCL0 0x0b00 +#define ENABLE_IP_GSCL1 0x0b04 +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 +
nit: tabspace after #define should be changed to one whitespace.
Quoted 19 lines
drivers/clk/samsung/clk-exynos5433.c +19
-0+static unsigned long gscl_clk_regs[]__initdata = { +MUX_SEL_GSCL , +MUX_ENABLE_GSCL , +MUX_STAT_GSCL , +ENABLE_ACLK_GSCL , +ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 , +ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 , +ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 , +ENABLE_PCLK_GSCL , +ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 , +ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 , +ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 , +ENABLE_IP_GSCL0 , +ENABLE_IP_GSCL1 , +ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 , +ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 , +ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 , +}; +
drivers/clk/samsung/clk-exynos5433.c static void __init exynos5433_cmu_g3d_init(struct device_node *np) · line 3279
Quoted 10 lines
drivers/clk/samsung/clk-exynos5433.c +10
-0+/* list of all parent clock list */ +PNAME (aclk_gscl_111_user_p) = {"fin_pll" ,"aclk_gscl_111" , }; +PNAME (aclk_gscl_333_user_p) = {"fin_pll" ,"aclk_gscl_333" , }; + +static struct samsung_mux_clock gscl_mux_clks[]__initdata = { +/* MUX_SEL_GSCL */ +MUX (CLK_MOUT_ACLK_GSCL_111_USER ,"mout_aclk_gscl_111_user" , + aclk_gscl_111_user_p,MUX_SEL_GSCL ,4 ,1 ), +MUX (CLK_MOUT_ACLK_GSCL_333_USER ,"mout_aclk_gscl_333_user" , + aclk_gscl_333_user_p,MUX_SEL_GSCL ,4 ,1 ),
aclk_gscl_333_user mux clock has a shift of '0'.
Review
Quoted 2 lines
(quoted diff) +2
-0+}; +
Thanks,
Pankaj Dubey
Chanwoo Choi
maintainerPATCH v2 13/19 arm64: exynos5433: Enable ARMv8-based Exynos5433 SoC support
In reply to Chanwoo ChoiThis patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC.
Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Geunsik Lim <[email protected]>
Acked-by Inki Dae <[email protected]>
--- arch/arm64/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm64/Kconfig +10 -0
@@ -146,6 +146,16 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool "ARMv8 based Samsung Exynos5433" + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS
Signature · 1 line
1.8.5.5
Chanwoo Choi
maintainerPATCH v2 14/19 arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
In reply to Chanwoo ChoiThis patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports PSCI (Power State Coordination Interface) v0.1.
Cc Kukjin Kim <[email protected]>
Cc Mark Rutland <[email protected]>
Cc Marc Zyngier <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++++++++++++++ 2 files changed, 1213 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi new file +698 -0
@@ -0,0 +1,698 @@ +/* + * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_aud { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", + "gpz0-4", "gpz0-5", "gpz0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_cpif { + gpv6: gpv6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_ese { + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_finger { + gpd5: gpd5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c6_bus: hs-i2c6-bus { + samsung,pins = "gpd5-3", "gpd5-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + +}; + +&pinctrl_fsys { + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr4: gpr4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr0: gpr0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr1: gpr1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr2: gpr2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr3: gpr3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + sd0_clk: sd0-clk { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpr0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpr0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_qrdy: sd0-qrdy { + samsung,pins = "gpr0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpr1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpr2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpr2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpr3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + pcie_bus: pcie_bus { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpr4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpr4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpr4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk_output: sd2-clk-output { + samsung,pins = "gpr4-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd_output: sd2-cmd-output { + samsung,pins = "gpr4-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; +}; + +&pinctrl_imem { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_nfc { + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c4_bus: hs-i2c4-bus { + samsung,pins = "gpj0-1", "gpj0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + +}; + +&pinctrl_peric { + gpv7: gpv7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd4: gpd4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd8: gpd8 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd6: gpd6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd7: gpd7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c8_bus: hs-i2c8-bus { + samsung,pins = "gpb0-1", "gpb0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c9_bus: hs-i2c9-bus { + samsung,pins = "gpb0-3", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpd4-3", "gpd4-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin0: fimc-is-spi-pin0 { + samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin1: fimc-is-spi-pin1 { + samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_bus: uart0-bus { + samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c2_bus: hs-i2c2-bus { + samsung,pins = "gpd0-3", "gpd0-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_bus: uart2-bus { + samsung,pins = "gpd1-5", "gpd1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart1_bus: uart1-bus { + samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c3_bus: hs-i2c3-bus { + samsung,pins = "gpd1-3", "gpd1-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + + hs_i2c0_bus: hs-i2c0-bus { + samsung,pins = "gpd2-1", "gpd2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c1_bus: hs-i2c1-bus { + samsung,pins = "gpd2-3", "gpd2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c7_bus: hs-i2c7-bus { + samsung,pins = "gpd2-7", "gpd2-6"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c10_bus: hs-i2c10-bus { + samsung,pins = "gpg3-1", "gpg3-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c11_bus: hs-i2c11-bus { + samsung,pins = "gpg3-3", "gpg3-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi3_bus: spi3-bus { + samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi4_bus: spi4-bus { + samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpc1-1", "gpc0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_i2c: fimc-is-ch0_i2c { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_mclk: fimc-is-ch0_mclk { + samsung,pins = "gpd7-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_i2c: fimc-is-ch1-i2c { + samsung,pins = "gpc2-3", "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_mclk: fimc-is-ch1-mclk { + samsung,pins = "gpd7-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_i2c: fimc-is-ch2-i2c { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_mclk: fimc-is-ch2-mclk { + samsung,pins = "gpd7-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_touch { + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c5_bus: hs-i2c5-bus { + samsung,pins = "gpj1-1", "gpj1-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +};
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +515 -0
515 lines not on this page · raw message
Signature · 1 line
1.8.5.5
Mark Rutland
reviewerRe: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Hi,
Quoted 20 lines · Chanwoo Choi
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports PSCI (Power State Coordination Interface) v0.1.
Cc Kukjin Kim <[email protected]>Cc Mark Rutland <[email protected]>Cc Marc Zyngier <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++++++++++++++ 2 files changed, 1213 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
[...]
Quoted 57 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +57
-0+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu1: cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu2: cpu at 102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x102>; + }; + + cpu3: cpu at 103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x103>; + }; + + cpu4: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu5: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu6: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu7: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci";
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 123
Quoted 10 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +10
-0+ reg = <0x3>; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + };
Given your comments on the latest posting, has CPU_OFF been tested, and does it work for _all_ CPUs (including CPU0)?
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 129
Quoted 6 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +6
-0+ + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges;
Is that valid when changing the number of cells? The address spaces aren't strictly identical in that case, and I'd expect a translation something like:
ranges = <0x0 0x0 0x0 0xff000000>;
Where the final cell is a sufficiently large value to cover all addresses in the soc node.
[...]
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 247
Quoted 10 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +10
-0+ gic:interrupt-controller at 11001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x11001000 0x1000>, + <0x11002000 0x1000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; + interrupts = <1 9 0xf04>; + };
The GICC needs to be 0x2000 long to map the GICC_DIR, which is at 0x1000-0x1003.
[...]
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 293
Quoted 9 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +9
-0+ pinctrl_alive: pinctrl at 10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = <0 16 0>; + }; + };
How exactly does the wakeup interrupt controller interact with the GIC? Surely the relationship between the two should be described?
Is it a subcomponent of the pincontrol block?
Thanks,
Mark.
Chanwoo Choi
maintainerRe: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Dear Mark,
Quoted 88 lines · Mark Rutland
Hi,
Quoted 20 lines · Chanwoo Choi
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports PSCI (Power State Coordination Interface) v0.1.
Cc Kukjin Kim <[email protected]>Cc Mark Rutland <[email protected]>Cc Marc Zyngier <[email protected]>Cc Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>Cc Catalin Marinas <[email protected]>Cc Will Deacon <[email protected]>Signed-off-by Chanwoo Choi <[email protected]>Acked-by Inki Dae <[email protected]>Acked-by Geunsik Lim <[email protected]>--- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 515 +++++++++++++++ 2 files changed, 1213 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi[...]
Quoted 62 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +62
-0+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu1: cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu2: cpu at 102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x102>; + }; + + cpu3: cpu at 103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x103>; + }; + + cpu4: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu5: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu6: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu7: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + psci {
Quoted 8 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 123
Quoted 5 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +5
-0+ compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + };Given your comments on the latest posting, has
CPU_OFFbeen tested, and does it work for _all_ CPUs (including CPU0)?
At current version,CPU_OFF of Exynos5433 is not working. I'm now working to find the cause of CPU_OFF fail. (I got CPU_ON of Exynos5433 all cores.)
Quoted 8 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 129
Quoted 7 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +6
-0+ + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges;
Quoted 5 lines
Is that valid when changing the number of cells? The address spaces aren't strictly identical in that case, and I'd expect a translation something like:
ranges = <0x0 0x0 0x0 0xff000000>;
I'll fix it after checking correct spec.
Quoted 17 lines
Where the final cell is a sufficiently large value to cover all addresses in the soc node.
[...]
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 247
Quoted 10 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +10
-0+ gic:interrupt-controller at 11001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x11001000 0x1000>, + <0x11002000 0x1000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; + interrupts = <1 9 0xf04>; + };
Quoted 2 lines
The GICC needs to be
0x2000long to map theGICC_DIR, which is at 0x1000-0x1003.
Do you mean that following dt node is right for gic-400?
reg = <0x11001000 0x1000>, <0x11002000 0x2000>, <- I changed the the range of GICC. <0x11004000 0x2000>, <0x11006000 0x2000>;
Quoted 13 lines
[...]
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 293
Quoted 9 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +9
-0+ pinctrl_alive: pinctrl at 10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = <0 16 0>; + }; + };
Quoted 2 lines
How exactly does the wakeup interrupt controller interact with the GIC? Surely the relationship between the two should be described?
The pinctrl_alive contains the alive part of GPIO PAD (gpa0~gpa3).
The each GPA0/GPA1 of pinctrl_alive pad did map to unique SPI number of GIC amd GPA2/GPA3 use only one interrupt (SPI[16]) as following:
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ #interrupt-cells = <2>;
+ };
gpa0-0 - SPI[0]
gpa0-1 - SPI[1]
gpa0-2 - SPI[2]
gpa0-3 - SPI[3]
gpa0-4 - SPI[4]
gpa0-5 - SPI[5]
gpa0-6 - SPI[6]
gpa0-7 - SPI[7]
gpa1-0 - SPI[8]
gpa1-1 - SPI[9]
gpa1-2 - SPI[10]
gpa1-3 - SPI[11]
gpa1-4 - SPI[12]
gpa1-5 - SPI[13]
gpa1-6 - SPI[14]
gpa1-7 - SPI[15]
GPA2/GPA3 use only one interrupt (SPI[16]).The pinctrl-exynos.c driver initialized external wakeup interrupt (e.g., GPA0/GPA1/GPA2/GPA3 of Exynos5433) in exynos_eint_wkup_init() function.
Following patch[1] adds the control for Exynos5433 wakeup irq.The exynos5433_pin_ctrl structure includes '.eint_wkup_init = exynos_eint_wkup_init;' fields to handle wakeup interrupt of Exynos SoC.
[PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207
+struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5433_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ .label = "exynos5433-gpio-ctrl0",
+ }, {And,
'struct exynos_irq_chip exynos7_wkup_irq_chip' handles the external interrupt of Exynos5433 SoC because Exynos5433 is the same with Exynos7 EINT (External Interrupt) register offset.
We can check it following patch[1] to control wakeup interrupt for Exynos7/Exynos5433.
- [1] [patch] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=14c255d35b25126149fb2fd199b030404229af65
+static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ .irq_request_resources = exynos_irq_request_resources,
+ .irq_release_resources = exynos_irq_release_resources,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
If happen external interrupt by pressing power button, the ops of 'struct exynos_irq_chip exynos7_wkup_irq_chip' would handle the interrupt.
For exampl, If I use following GPAx as interrupt, I can check it on the result of /proc/interrupts.
gpa2-7 - power key
gpa2-0 - volume-up key
gpa2-1 - volume-up key
gpa0-7 - s2mps13 pmic irq
'exynos7_wkup_irq_chip' would handle the external interrupt(gpa).
#cat /proc/interrupts
1: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 0 volume-up key 2: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 1 volume-down key 7: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 7 s2mps13 8: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 7 power key
IMHO,
Happen SPI -> GIC -> Cortex-A57/Cortex-A53 -> pinctrl-exynos.c -> exynos7_wkup_irq_chip -> irq handling
Best Regards,
Chanwoo Choi
Quoted 10 lines
Is it a subcomponent of the pincontrol block?
Thanks,
Mark.
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Mark Rutland
reviewerRe: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Hi,
Quoted 7 lines
Quoted 7 lines
Quoted 6 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +6
-0+ psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + };
Quoted 6 lines
Quoted 2 lines
Given your comments on the latest posting, has
CPU_OFFbeen tested, and does it work for _all_ CPUs (including CPU0)?At current version,
CPU_OFFof Exynos5433 is not working. I'm now working to find the cause ofCPU_OFFfail. (I gotCPU_ONof Exynos5433 all cores.)
CPU_OFF should not be described in the DT unless it works.
[...]
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +5
-0+ soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges;
Quoted 7 lines
Quoted 5 lines
Is that valid when changing the number of cells? The address spaces aren't strictly identical in that case, and I'd expect a translation something like:
ranges = <0x0 0x0 0x0 0xff000000>;I'll fix it after checking correct spec.
Thanks.
[...]
Quoted 14 lines
Quoted 11 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 247
Quoted 10 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +10
-0+ gic:interrupt-controller at 11001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x11001000 0x1000>, + <0x11002000 0x1000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; + interrupts = <1 9 0xf04>; + };Quoted 2 lines
The GICC needs to be
0x2000long to map theGICC_DIR, which is at 0x1000-0x1003.
Quoted 6 lines
Do you mean that following dt node is right for gic-400?
reg = <0x11001000 0x1000>, <0x11002000 0x2000>, <- I changed the the range of GICC. <0x11004000 0x2000>, <0x11006000 0x2000>;
Yes.
[...]
Quoted 118 lines
Quoted 10 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 293
Quoted 9 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +9
-0+ pinctrl_alive: pinctrl at 10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = <0 16 0>; + }; + };Quoted 2 lines
How exactly does the wakeup interrupt controller interact with the GIC? Surely the relationship between the two should be described?
The
pinctrl_alivecontains the alive part of GPIO PAD (gpa0~gpa3).The each GPA0/GPA1 of
pinctrl_alivepad did map to unique SPI number of GIC amd GPA2/GPA3 use only one interrupt (SPI[16]) as following:+&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + #interrupt-cells = <2>; + }; gpa0-0 - SPI[0] gpa0-1 - SPI[1] gpa0-2 - SPI[2] gpa0-3 - SPI[3] gpa0-4 - SPI[4] gpa0-5 - SPI[5] gpa0-6 - SPI[6] gpa0-7 - SPI[7] gpa1-0 - SPI[8] gpa1-1 - SPI[9] gpa1-2 - SPI[10] gpa1-3 - SPI[11] gpa1-4 - SPI[12] gpa1-5 - SPI[13] gpa1-6 - SPI[14] gpa1-7 - SPI[15] GPA2/GPA3 use only one interrupt (SPI[16]).The
pinctrl-exynos.cdriver initialized external wakeup interrupt (e.g., GPA0/GPA1/GPA2/GPA3 of Exynos5433) inexynos_eint_wkup_init()function.Following patch[1] adds the control for Exynos5433 wakeup irq.The
exynos5433_pin_ctrlstructure includes '.eint_wkup_init =exynos_eint_wkup_init;' fields to handle wakeup interrupt of Exynos SoC.[PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207+struct
samsung_pin_ctrlexynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks =exynos5433_pin_banks0,
+ .nr_banks =ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init =exynos_eint_wkup_init,
+ .suspend =exynos_pinctrl_suspend,
+ .resume =exynos_pinctrl_resume,
+ .label = "exynos5433-gpio-ctrl0",
+ }, {And,
'structexynos_irq_chipexynos7_wkup_irq_chip' handles the external interrupt of Exynos5433 SoC because Exynos5433 is the same with Exynos7 EINT (External Interrupt) register offset.We can check it following patch[1] to control wakeup interrupt for Exynos7/Exynos5433.
- [1] [patch] pinctrl: exynos: Addirq_chipinstance for Exynos7 wakeup interrupts
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=14c255d35b25126149fb2fd199b030404229af65+static struct
exynos_irq_chipexynos7_wkup_irq_chip__initdata= {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask =exynos_irq_unmask,
+ .irq_mask =exynos_irq_mask,
+ .irq_ack =exynos_irq_ack,
+ .irq_set_type =exynos_irq_set_type,
+ .irq_set_wake =exynos_wkup_irq_set_wake,
+ .irq_request_resources =exynos_irq_request_resources,
+ .irq_release_resources =exynos_irq_release_resources,
+ },
+ .eint_con =EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask =EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend =EXYNOS7_WKUP_EPEND_OFFSET,
+};If happen external interrupt by pressing power button, the ops of 'struct
exynos_irq_chipexynos7_wkup_irq_chip' would handle the interrupt.For exampl, If I use following GPAx as interrupt, I can check it on the result of
/proc/interrupts.
gpa2-7 - power key
gpa2-0 - volume-up key
gpa2-1 - volume-up key
gpa0-7 - s2mps13 pmic irq'
exynos7_wkup_irq_chip' would handle the external interrupt(gpa).#cat
/proc/interrupts
Quoted 8 lines
1: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 0 volume-up key 2: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 1 volume-down key 7: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 7 s2mps13 8: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 7 power keyIMHO,
Happen SPI -> GIC -> Cortex-A57/Cortex-A53 ->pinctrl-exynos.c->exynos7_wkup_irq_chip-> irq handling
So physically interrupts are fed into the wakeup IRQ chip, which routes them to the GIC? And we describe such in DT, as opposed to pretending interrupts are fed straight into the GIC, and bolting the wakeup controller on the side?
If so, that sounds fine to me.
Thanks,
Mark.
Re: [PATCH 14/19] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
Dear Mark,
Quoted 9 lines · Mark Rutland
Hi,
Quoted 7 lines
Quoted 7 lines
Quoted 6 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +6
-0+ psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + };
Quoted 8 lines
Quoted 6 lines
Quoted 2 lines
Given your comments on the latest posting, has
CPU_OFFbeen tested, and does it work for _all_ CPUs (including CPU0)?At current version,
CPU_OFFof Exynos5433 is not working. I'm now working to find the cause ofCPU_OFFfail. (I gotCPU_ONof Exynos5433 all cores.)
CPU_OFFshould not be described in the DT unless it works.
OK, I'll drop 'cpu_off" property on next patchset. After fixing it, I'll re-send separate patch.
Quoted 35 lines
[...]
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +5
-0+ soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges;Quoted 7 lines
Quoted 5 lines
Is that valid when changing the number of cells? The address spaces aren't strictly identical in that case, and I'd expect a translation something like:
ranges = <0x0 0x0 0x0 0xff000000>;I'll fix it after checking correct spec.
Thanks.
[...]
Quoted 14 lines
Quoted 13 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 247
Quoted 10 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +10
-0+ gic:interrupt-controller at 11001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x11001000 0x1000>, + <0x11002000 0x1000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; + interrupts = <1 9 0xf04>; + };The GICC needs to be
0x2000long to map theGICC_DIR, which is at 0x1000-0x1003.
Quoted 8 lines
Quoted 6 lines
Do you mean that following dt node is right for gic-400?
reg = <0x11001000 0x1000>, <0x11002000 0x2000>, <- I changed the the range of GICC. <0x11004000 0x2000>, <0x11006000 0x2000>;Yes.
OK. I'll fix it.
Quoted 127 lines
[...]
Quoted 124 lines
Quoted 10 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi line 293
Quoted 9 lines
arch/arm64/boot/dts/exynos/exynos5433.dtsi new file +9
-0+ pinctrl_alive: pinctrl at 10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = <0 16 0>; + }; + };Quoted 2 lines
How exactly does the wakeup interrupt controller interact with the GIC? Surely the relationship between the two should be described?
The
pinctrl_alivecontains the alive part of GPIO PAD (gpa0~gpa3).The each GPA0/GPA1 of
pinctrl_alivepad did map to unique SPI number of GIC amd GPA2/GPA3 use only one interrupt (SPI[16]) as following:+&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + #interrupt-cells = <2>; + }; gpa0-0 - SPI[0] gpa0-1 - SPI[1] gpa0-2 - SPI[2] gpa0-3 - SPI[3] gpa0-4 - SPI[4] gpa0-5 - SPI[5] gpa0-6 - SPI[6] gpa0-7 - SPI[7] gpa1-0 - SPI[8] gpa1-1 - SPI[9] gpa1-2 - SPI[10] gpa1-3 - SPI[11] gpa1-4 - SPI[12] gpa1-5 - SPI[13] gpa1-6 - SPI[14] gpa1-7 - SPI[15] GPA2/GPA3 use only one interrupt (SPI[16]).The
pinctrl-exynos.cdriver initialized external wakeup interrupt (e.g., GPA0/GPA1/GPA2/GPA3 of Exynos5433) inexynos_eint_wkup_init()function.Following patch[1] adds the control for Exynos5433 wakeup irq.The
exynos5433_pin_ctrlstructure includes '.eint_wkup_init =exynos_eint_wkup_init;' fields to handle wakeup interrupt of Exynos SoC.[PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207+struct
samsung_pin_ctrlexynos5433_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks =exynos5433_pin_banks0,
+ .nr_banks =ARRAY_SIZE(exynos5433_pin_banks0),
+ .eint_wkup_init =exynos_eint_wkup_init,
+ .suspend =exynos_pinctrl_suspend,
+ .resume =exynos_pinctrl_resume,
+ .label = "exynos5433-gpio-ctrl0",
+ }, {And,
'structexynos_irq_chipexynos7_wkup_irq_chip' handles the external interrupt of Exynos5433 SoC because Exynos5433 is the same with Exynos7 EINT (External Interrupt) register offset.We can check it following patch[1] to control wakeup interrupt for Exynos7/Exynos5433.
- [1] [patch] pinctrl: exynos: Addirq_chipinstance for Exynos7 wakeup interrupts
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=14c255d35b25126149fb2fd199b030404229af65+static struct
exynos_irq_chipexynos7_wkup_irq_chip__initdata= {
+ .chip = {
+ .name = "exynos7_wkup_irq_chip",
+ .irq_unmask =exynos_irq_unmask,
+ .irq_mask =exynos_irq_mask,
+ .irq_ack =exynos_irq_ack,
+ .irq_set_type =exynos_irq_set_type,
+ .irq_set_wake =exynos_wkup_irq_set_wake,
+ .irq_request_resources =exynos_irq_request_resources,
+ .irq_release_resources =exynos_irq_release_resources,
+ },
+ .eint_con =EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask =EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend =EXYNOS7_WKUP_EPEND_OFFSET,
+};If happen external interrupt by pressing power button, the ops of 'struct
exynos_irq_chipexynos7_wkup_irq_chip' would handle the interrupt.For exampl, If I use following GPAx as interrupt, I can check it on the result of
/proc/interrupts.
gpa2-7 - power key
gpa2-0 - volume-up key
gpa2-1 - volume-up key
gpa0-7 - s2mps13 pmic irq'
exynos7_wkup_irq_chip' would handle the external interrupt(gpa).#cat
/proc/interrupts1: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 0 volume-up key 2: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 1 volume-down key 7: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 7 s2mps13 8: 0 0 0 0 0 0 0 exynos7_wkup_irq_chip 7 power key
Quoted 7 lines
Quoted 2 lines
IMHO,
Happen SPI -> GIC -> Cortex-A57/Cortex-A53 ->pinctrl-exynos.c->exynos7_wkup_irq_chip-> irq handlingSo physically interrupts are fed into the wakeup IRQ chip, which routes them to the GIC? And we describe such in DT, as opposed to pretending interrupts are fed straight into the GIC, and bolting the wakeup controller on the side?
GIC is well working with pinctrl-exynos.c for Exynos SoC in mainline kernel. Do you want to know the detailed relation between GIC and pinctrl-exynos driver or not?
If I misunderstand, please let me know your question again.
Best Regards,
Chanwoo Choi
Chanwoo Choi
maintainerPATCH v2 15/19 arm64: dts: exynos: Add MSHC dt node for Exynos5433
In reply to Chanwoo ChoiFrom: Jaehoon Chung <[email protected]>
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433 SoC. MSHC is an interface between the system the SD/MMC card.
Cc Kukjin Kim <[email protected]>
Cc Mark Rutland <[email protected]>
Cc Marc Zyngier <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Signed-off-by Jaehoon Chung <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
arch/arm64/boot/dts/exynos/exynos5433.dtsi +42 -0
@@ -52,6 +52,9 @@ i2c9 = &hsi2c_9; i2c10 = &hsi2c_10; i2c11 = &hsi2c_11; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; }; cpus {
@@ -502,6 +505,45 @@ status = "disabled"; }; + mshc_0: mshc at 15540000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 225 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15540000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC0>, + <&cmu_fsys CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_1: mshc at 15550000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 226 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15550000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC1>, + <&cmu_fsys CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_2: mshc at 15560000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 227 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15560000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC2>, + <&cmu_fsys CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <4 13 0xff01>,
Signature · 1 line
1.8.5.5
Chanwoo Choi
maintainerPATCH v2 16/19 arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
In reply to Chanwoo ChoiThis patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC. SPI transfers serial data by using various peripherals. SPI includes 8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used for SPI communication.
Cc Kukjin Kim <[email protected]>
Cc Mark Rutland <[email protected]>
Cc Marc Zyngier <[email protected]>
Cc Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 118 +++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+)
arch/arm64/boot/dts/exynos/exynos5433.dtsi +118 -0
@@ -55,6 +55,11 @@ mshc0 = &mshc_0; mshc1 = &mshc_1; mshc2 = &mshc_2; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; }; cpus {
@@ -249,6 +254,34 @@ interrupts = <1 9 0xf04>; }; + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + + pdma0: pdma at 15610000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15610000 0x1000>; + interrupts = <0 228 0>; + clocks = <&cmu_fsys CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma at 15600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15600000 0x1000>; + interrupts = <0 246 0>; + clocks = <&cmu_fsys CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + serial_0: serial at 14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>;
@@ -349,6 +382,91 @@ interrupts = <0 442 0>; }; + spi_0: spi at 14d20000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d20000 0x100>; + interrupts = <0 432 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI0>, + <&cmu_top CLK_SCLK_SPI0_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi at 14d30000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d30000 0x100>; + interrupts = <0 433 0>; + dmas = <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI1>, + <&cmu_top CLK_SCLK_SPI1_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + spi_2: spi at 14d40000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d40000 0x100>; + interrupts = <0 434 0>; + dmas = <&pdma0 13>, <&pdma0 12>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI2>, + <&cmu_top CLK_SCLK_SPI2_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + spi_3: spi at 14d50000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d50000 0x100>; + interrupts = <0 447 0>; + dmas = <&pdma0 23>, <&pdma0 22>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI3>, + <&cmu_top CLK_SCLK_SPI3_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + status = "disabled"; + }; + + spi_4: spi at 14d00000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d00000 0x100>; + interrupts = <0 412 0>; + dmas = <&pdma0 25>, <&pdma0 24>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI4>, + <&cmu_top CLK_SCLK_SPI4_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + status = "disabled"; + }; + hsi2c_0: hsi2c at 14e40000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e40000 0x1000>;
Signature · 1 line
1.8.5.5
Chanwoo Choi
maintainerPATCH v2 17/19 serial: samsung: Add the support for Exynos5433 SoC
In reply to Chanwoo ChoiThis patch adds new s3c24xx_serial_drv_data structure for Exynos5433 SoC because Exynos5433 has different fifo size from existing Exynos4 SoC.
Cc Greg Kroah-Hartman <[email protected]>
Cc Jiri Slaby <[email protected]>
Cc linux-serial at vger.kernel.org
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- drivers/tty/serial/samsung.c | 56 ++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 20 deletions(-)
drivers/tty/serial/samsung.c +36 -20
@@ -1771,32 +1771,43 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {#endif #if defined(CONFIG_ARCH_EXYNOS ) +#define EXYNOS_COMMON_SERIAL_DRV_DATA \ + .info = &(struct s3c24xx_uart_info) { \ + .name = "Samsung Exynos UART", \ + .type = PORT_S3C6400, \ + .has_divslot = 1, \ + .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ + .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ + .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ + .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ + .def_clk_sel = S3C2410_UCON_CLKSEL0, \ + .num_clks = 1, \ + .clksel_mask = 0, \ + .clksel_shift = 0, \ + }, \ + .def_cfg = &(struct s3c2410_uartcfg) { \ + .ucon = S5PV210_UCON_DEFAULT, \ + .ufcon = S5PV210_UFCON_DEFAULT, \ + .has_fracval = 1, \ + } \ +static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { - .info = &(struct s3c24xx_uart_info ) { - .name ="Samsung Exynos4 UART" , - .type =PORT_S3C6400 , - .has_divslot =1 , - .rx_fifomask =S5PV210_UFSTAT_RXMASK , - .rx_fifoshift =S5PV210_UFSTAT_RXSHIFT , - .rx_fifofull =S5PV210_UFSTAT_RXFULL , - .tx_fifofull =S5PV210_UFSTAT_TXFULL , - .tx_fifomask =S5PV210_UFSTAT_TXMASK , - .tx_fifoshift =S5PV210_UFSTAT_TXSHIFT , - .def_clk_sel =S3C2410_UCON_CLKSEL0 , - .num_clks =1 , - .clksel_mask =0 , - .clksel_shift =0 , - }, - .def_cfg = &(struct s3c2410_uartcfg ) { - .ucon =S5PV210_UCON_DEFAULT , - .ufcon =S5PV210_UFCON_DEFAULT , - .has_fracval =1 , - }, +EXYNOS_COMMON_SERIAL_DRV_DATA , .fifosize = {256 ,64 ,16 ,16 }, }; + +static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { +EXYNOS_COMMON_SERIAL_DRV_DATA , + .fifosize = {64 ,256 ,16 ,256 }, +}; +#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) +#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)#else #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL +#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL#endif static struct platform_device_id s3c24xx_serial_driver_ids[] = {
@@ -1818,6 +1829,9 @@ static struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "exynos4210-uart", .driver_data = EXYNOS4210_SERIAL_DRV_DATA, + }, { + .name = "exynos5433-uart", + .driver_data = EXYNOS5433_SERIAL_DRV_DATA, }, { }, };
@@ -1837,6 +1851,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = (void *)S5PV210_SERIAL_DRV_DATA }, { .compatible = "samsung,exynos4210-uart", .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, + { .compatible = "samsung,exynos5433-uart", + .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, {}, };MODULE_DEVICE_TABLE (of, s3c24xx_uart_dt_match);
Signature · 1 line
1.8.5.5
Chanwoo Choi
maintainerPATCH v2 18/19 clocksource: exynos_mct: Add the support for Exynos 64bit SoC
In reply to Chanwoo ChoiThis patch adds the support for Exynos 64bit SoC. The delay_timer is only used for Exynos 32bit SoC.
Cc Daniel Lezcano <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Kukjin Kim <[email protected]>
Cc Mark Rutland <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
--- drivers/clocksource/Kconfig | 1 - drivers/clocksource/exynos_mct.c | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-)
drivers/clocksource/Kconfig +0 -1
@@ -134,7 +134,6 @@ config CLKSRC_METAG_GENERIC config CLKSRC_EXYNOS_MCT def_bool y if ARCH_EXYNOS - depends on !ARM64 help Support for Multi Core Timer controller on Exynos SoCs.
drivers/clocksource/exynos_mct.c +4 -0
@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)return exynos4_read_count_32 (); } +#if defined(CONFIG_ARM )static struct delay_timer exynos4_delay_timer;static cycles_t exynos4_read_current_timer (void )
@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void) "cycles_t needs to move to 32-bit for ARM64 usage"); return exynos4_read_count_32(); } +#endif static void __init exynos4_clocksource_init (void ) {exynos4_mct_frc_start (); +#if defined(CONFIG_ARM ) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; exynos4_delay_timer.freq = clk_rate;register_current_timer_delay (&exynos4_delay_timer); +#endif if (clocksource_register_hz (&mct_frc, clk_rate))panic ("%s: can't register clocksource\n" , mct_frc.name);
Signature · 1 line
1.8.5.5
Chanwoo Choi
maintainerPATCH v2 19/19 arm64: Enable Exynos5433 SoC in the defconfig
In reply to Chanwoo ChoiThis patch enable Exynos5433 SoC in the arm64 defconfig.
Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Signed-off-by Chanwoo Choi <[email protected]>
Acked-by Inki Dae <[email protected]>
Acked-by Geunsik Lim <[email protected]>
--- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm64/configs/defconfig +1 -0
@@ -33,6 +33,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_EXYNOS5433=y CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_VEXPRESS=y
Signature · 1 line
1.8.5.5