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arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

RFC PATCH New Stefan Roese 2 participants 10 messages Dec 8, 2014 – Dec 18, 2014

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Arm (32-bit) Arm i.MX and Layerscape
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Stefan Roese

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#0 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

While switching a custom i.MX6DL board port to the common mx6 infrastructure without any board specific DCD file (*.cfg), booting from SD-card (mmc0) via the bmode command (bmode mmc0) did not work any more. Adding this one line for the CCGR0 solves this issue.

I have to admit that I'm not really sure why this is needed in this case. So if somebody has an explanation for the need for this CCGR0 register setup in the DCD, then please let me know.

Signed-off-by Stefan Roese <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Stefano Babic <[email protected]>
---
 arch/arm/imx-common/spl_sd.cfg | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/imx-common/spl_sd.cfg +9 -0
index 5fc3e8a..8239def 100644
@@ -6,3 +6,12 @@
 
 IMAGE_VERSION	2
 BOOT_FROM	sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* Set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
Signature · 1 line
2.2.0
reviewer
#1 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Hi Stefan,

Quoted 8 lines · Stefan Roese

While switching a custom i.MX6DL board port to the common mx6 infrastructure without any board specific DCD file (*.cfg), booting from SD-card (mmc0) via the bmode command (bmode mmc0) did not work any more. Adding this one line for the CCGR0 solves this issue.

I have to admit that I'm not really sure why this is needed in this case. So if somebody has an explanation for the need for this CCGR0 register setup in the DCD, then please let me know.

Could you please try to narrow down what exact field of the CGR0 register makes your board boot?

I suspect it could be the AIPS related clocks (CG0 / CG1).

Please confirm. If this is the case, then we should turn on the AIPS clocks inside init_aips().

Thanks,

Fabio Estevam

author
#2 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Hi Fabio,

Quoted 6 lines · Fabio Estevam
Quoted 5 lines · Stefan Roese

While switching a custom i.MX6DL board port to the common mx6 infrastructure without any board specific DCD file (*.cfg), booting from SD-card (mmc0) via the bmode command (bmode mmc0) did not work any more. Adding this one line for the CCGR0 solves this issue.

Quoted 8 lines
Quoted 3 lines

I have to admit that I'm not really sure why this is needed in this case. So if somebody has an explanation for the need for this CCGR0 register setup in the DCD, then please let me know.

Could you please try to narrow down what exact field of the CGR0 register makes your board boot?

I suspect it could be the AIPS related clocks (CG0 / CG1).

I tested with these values:

0x00C03F30
0x00C03F33
0x00C03F3C

All do not boot. Only the original one does:

0x00C03F3F

So yes, AIPS related clocks are definitely needed!

I'm wondering about this, since the default value after reset should be 0xffffffff for this register, right? All clocks enabled. But this does not seem to be the case. As SPL is not started correctly (no output at all on the console) when I don't add this line to spl_sd.cfg.

Its not easy for me to debug this issue since the board usually boots from NAND. I can't strap this board to boot via MMC0 right now. So I have to use the "bmode mmc0" command. And JTAG debugging via BDI3000 doesn't seem to "survive" the bmode command.

Quoted 2 lines

Please confirm. If this is the case, then we should turn on the AIPS clocks inside init_aips().

See above.

Could you test this on one of your board? If your board also fails to boot via the "bmode mmc0" command if the CCGR0 register value is missing?

Thanks,
Stefan

reviewer
#3 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Hi Stefan,

Quoted 2 lines · Stefan Roese

Could you test this on one of your board? If your board also fails to boot via the "bmode mmc0" command if the CCGR0 register value is missing?

I am currently out of the office without access to my mx6 board, but looking in board/freescale/mx6sabresd/mx6sabresd.c we have:
writel(0x00C03F3F, &ccm->CCGR0);

,which turns on the AIPS clocks.

Can't you just turn on the AIPS clocks inside in your board file like we do on sabresd?

I am not sure where the AIPS clocks are being turned off in your case though.

Regards,

Fabio Estevam

author
#4 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Hi Fabio,

Quoted 4 lines · Fabio Estevam
Quoted 2 lines

Could you test this on one of your board? If your board also fails to boot via the "bmode mmc0" command if the CCGR0 register value is missing?

I am currently out of the office without access to my mx6 board,

I see. Perhaps you could do that once you are back in the office...

Quoted 8 lines

but
looking in board/freescale/mx6sabresd/mx6sabresd.c we have:
writel(0x00C03F3F, &ccm->CCGR0);

,which turns on the AIPS clocks.

Can't you just turn on the AIPS clocks inside in your board file like we do on sabresd?

I'm doing just that. Its copied directly from your code. Problem is, this seems to be too late. The BootROM doesn't seem to load SPL completely from the SD card when this CCGR0 line is missing. At least this is how I'm interpreting this hangup.

Quoted 1 line

I am not sure where the AIPS clocks are being turned off in your case though.

I'm pretty sure that no "code" is turning them off. As mentioned before, its not that easy for me to debug this though.

Again, my current best guess is, that the BootROM fails to load the SPL from SD card completely. So we have no chance to configure this register via code, but need to do it via the DCD. It might be that this is related to the "bmode mmc0" command. As I'm unable to test direct SD card booting via strapping. Not sure though.

Thanks,
Stefan

reviewer
#5 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Quoted 9 lines · Stefan Roese

Hi Fabio,

Quoted 6 lines · Fabio Estevam
Quoted 4 lines

Could you test this on one of your board? If your board also fails to boot
via the "bmode mmc0" command if the CCGR0 register value is missing?

Quoted 4 lines
Quoted 1 line

I am currently out of the office without access to my mx6 board,

I see. Perhaps you could do that once you are back in the office...

Sure, I will test it and will let you know how it goes.

In the meantime, I am wondering if the change below would allow your board to boot:

arch/arm/cpu/armv7/mx6/soc.c +4 -0
@@ -105,6 +105,10 @@ void init_aips(void)
 #ifdef CONFIG_MX6SX
        struct aipstz_regs *aips3;
 #endif
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       /* Turn on AIPS1 and AIPS2 clocks */
+       setbits_le32(&ccm->CCGR0, 0xf);
 
        aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
        aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;

Regards,

Fabio Estevam

author
#6 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Quoted 11 lines · Fabio Estevam
Quoted 9 lines
Quoted 6 lines
Quoted 3 lines

Could you test this on one of your board? If your board also fails to boot
via the "bmode mmc0" command if the CCGR0 register value is missing?

I am currently out of the office without access to my mx6 board,

I see. Perhaps you could do that once you are back in the office...

Sure, I will test it and will let you know how it goes.

Thanks!

Quoted 6 lines

In the meantime, I am wondering if the change below would allow your board to boot:

arch/arm/cpu/armv7/mx6/soc.c void init_aips(void) · line 114

Quoted 10 lines
arch/arm/cpu/armv7/mx6/soc.c +4 -0
@@ -105,6 +105,10 @@ void init_aips(void)
  #ifdef CONFIG_MX6SX
         struct aipstz_regs *aips3;
  #endif
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       /* Turn on AIPS1 and AIPS2 clocks */
+       setbits_le32(&ccm->CCGR0, 0xf);
 
         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;

I just tested it. And it doesn't help. I really think this code is not reached in this failure case. As the SPL is not loaded completely.

Thanks,
Stefan

reviewer
#7 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Hi Stefan,

Quoted 2 lines · Stefan Roese

I just tested it. And it doesn't help. I really think this code is not reached in this failure case. As the SPL is not loaded completely.

Do you have this patch applied?

commit f2863ff3f47c99c4b5ba00be572e3a2c4213c5a2

Author: Nikita Kiryanov <[email protected]>
Date:   Wed Oct 29 19:28:33 2014 +0200

arm: imx: make bmode command work with SPL/U-Boot combo

The bmode command forces the SoC to use a specific boot device by writing its boot mode into SRC_GPR9, and notifying the SoC of the change using SRC_GPR10[28] bit: if the bit is on, bootROM uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine the boot device.

SPL on the other hand is oblivious to this distinction, so once the bootROM loads SPL from the device configured in SRC_GPR10, SPL will attempt to load U-Boot from the device configured in SRC_SMBR1, which is not updated by the bootROM to the value in SRC_GPR9.

The result is that the selected boot device is not used across all the boot stages.

Update spl_boot_device() to look at gpr9 when necessary.

Signed-off-by Nikita Kiryanov <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Troy Kisky <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Heiko Schocher <[email protected]>
author
#8 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Quoted 28 lines · Fabio Estevam
Quoted 2 lines

I just tested it. And it doesn't help. I really think this code is not reached in this failure case. As the SPL is not loaded completely.

Do you have this patch applied?

commit f2863ff3f47c99c4b5ba00be572e3a2c4213c5a2

Author: Nikita Kiryanov <[email protected]>
Date:   Wed Oct 29 19:28:33 2014 +0200

arm: imx: make bmode command work with SPL/U-Boot combo

The bmode command forces the SoC to use a specific boot device by writing its boot mode into SRC_GPR9, and notifying the SoC of the change using SRC_GPR10[28] bit: if the bit is on, bootROM uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine the boot device.

SPL on the other hand is oblivious to this distinction, so once the bootROM loads SPL from the device configured in SRC_GPR10, SPL will attempt to load U-Boot from the device configured in SRC_SMBR1, which is not updated by the bootROM to the value in SRC_GPR9.

The result is that the selected boot device is not used across all the boot stages.

Update spl_boot_device() to look at gpr9 when necessary.

Quoted 7 lines
Signed-off-by Nikita Kiryanov <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Troy Kisky <[email protected]>
Cc Tim Harvey <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Heiko Schocher <[email protected]>

Yes, its applied. I'm nearly on mainline right now. And it doesn't help. Which makes sense if my current guess is correct, that the BootROM doesn't load the SPL completely without this CCGR0 register setting in the DCD.

Thanks,
Stefan

reviewer
#9 lore raw

RFC PATCH 1/1 arm: mx6: Add CCGR0 configuration to default DCD (spl_sd.cfg)

Hi Stefan,

Quoted 3 lines · Stefan Roese

Yes, its applied. I'm nearly on mainline right now. And it doesn't help. Which makes sense if my current guess is correct, that the BootROM doesn't load the SPL completely without this CCGR0 register setting in the DCD.

On a mx6qsabresd booting via SPL:

U-Boot SPL 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37)

U-Boot 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37)

CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
CPU:   Temperature 46 C
Reset cause: POR
Board: MX6-SabreSD
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2

*** Warning - bad CRC, using default environment

No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

=> bmode sd3
resetting ...

U-Boot SPL 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37)

U-Boot 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37)

CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
CPU:   Temperature 47 C
Reset cause: WDOG
Board: MX6-SabreSD
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2

*** Warning - bad CRC, using default environment

No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

=>

However if I move the SD card into SD2 slot, then it fails:

=> bmode sd2
resetting ...

U-Boot SPL 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37)
MMC: no card present
spl: mmc init failed: err - -16
### ERROR ### Please RESET the board ###

The spl loaded, but it failed to load U-boot. Probably because SPL did not initialized SD2, so it seems things are working fine here.