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arm:ls1021a:configure ls1021 scfg for QSPI

PATCH New Chao Fu 3 participants 3 messages Oct 30, 2014 – Dec 10, 2014 Arm (32-bit)

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Chao Fu

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#0 lore raw

PATCH 1/1 arm:ls1021a:configure ls1021 scfg for QSPI

From: Chao Fu <[email protected]>

Configure ls1021a scfg register for QSPI clock initalization.

Signed-off-by Chao Fu <[email protected]>
Signed-off-by Alison Wang <[email protected]>
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
 board/freescale/ls1021aqds/ls1021aqds.c           | 4 ++++
 board/freescale/ls1021atwr/ls1021atwr.c           | 4 ++++
 3 files changed, 9 insertions(+)
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +1 -0
index 7995fe2..cdee199 100644
@@ -100,6 +100,7 @@ struct ccsr_gur {
 #define SCFG_ETSECDMAMCR_LE_BD_FR	0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
+#define SCFG_QSPI_CLKSEL		0xc0100000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
board/freescale/ls1021aqds/ls1021aqds.c +4 -0
index 32e0fef..70da686 100644
@@ -146,6 +146,10 @@ int board_early_init_f(void)
 	init_early_memctl_regs();
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
 	/* Workaround for the issue that DDR could not respond to
 	 * barrier transaction which is generated by executing DSB/ISB
 	 * instruction. Set CCI-400 control override register to
board/freescale/ls1021atwr/ls1021atwr.c +4 -0
index 50d5640..25b1eb9 100644
@@ -278,6 +278,10 @@ int board_init(void)
 	config_serdes_mux();
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
 	return 0;
 }
Signature · 1 line
1.8.4
#1 lore raw

PATCH 1/1 arm:ls1021a:configure ls1021 scfg for QSPI

Quoted 4 lines · Chao Fu

From: Chao Fu <[email protected]>

Configure ls1021a scfg register for QSPI clock initalization.

Quoted 8 lines
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Alison Wang <[email protected]>
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
 board/freescale/ls1021aqds/ls1021aqds.c           | 4 ++++
 board/freescale/ls1021atwr/ls1021atwr.c           | 4 ++++
 3 files changed, 9 insertions(+)

Looks like this patch can be dropped as the change is in
http://patchwork.ozlabs.org/patch/418986/.

York

#2 lore raw

PATCH 1/1 arm:ls1021a:configure ls1021 scfg for QSPI

Hi, York,

Quoted 14 lines · Chao Fu
Quoted 4 lines

From: Chao Fu <[email protected]>

Configure ls1021a scfg register for QSPI clock initalization.

Quoted 8 lines
Signed-off-by Chao Fu <[email protected]>
Signed-off-by Alison Wang <[email protected]>
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
 board/freescale/ls1021aqds/ls1021aqds.c           | 4 ++++
 board/freescale/ls1021atwr/ls1021atwr.c           | 4 ++++
 3 files changed, 9 insertions(+)
Quoted 2 lines

Looks like this patch can be dropped as the change is in
http://patchwork.ozlabs.org/patch/418986/.

[Alison Wang] Yes. Thanks.

Best Regards,
Alison Wang