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keystone: set default pci mode to root complex

PATCH In review Murali Karicheri 2 participants 3 messages Dec 9, 2014 – Jan 7, 2015 Arm (32-bit)

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Murali Karicheri

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#0 lore raw

PATCH 1/1 keystone: set default pci mode to root complex

pci ports are used as root complex in Linux. So set this as default in u-boot for keystone devices

Signed-off-by Murali Karicheri <[email protected]>
---
 arch/arm/cpu/armv7/keystone/init.c            |   33 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-keystone/hardware.h |    1 +
 2 files changed, 34 insertions(+)
arch/arm/cpu/armv7/keystone/init.c +33 -0
index c2b9478..c96845c 100644
@@ -15,6 +15,16 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/psc_defs.h>
 
+#define MAX_PCI_PORTS		2
+enum pci_mode	{
+	ENDPOINT,
+	LEGACY_ENDPOINT,
+	ROOTCOMPLEX,
+};
+
+#define DEVCFG_MODE_MASK		(BIT(2) | BIT(1))
+#define DEVCFG_MODE_SHIFT		1
+
 void chip_configuration_unlock(void)
 {
 	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);

@@ -68,6 +78,24 @@ void osr_init(void)
 }
 #endif
 
+/* Function to set up PCIe mode */
+static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
+{
+	u32 val = __raw_readl(KS2_DEVCFG);
+
+	if (pcie_port >= MAX_PCI_PORTS)
+		return;
+
+	/**
+	 * each pci port has two bits for mode and it starts at
+	 * bit 1. So use port number to get the right bit position.
+	 */
+	pcie_port <<= 1;
+	val &= ~(DEVCFG_MODE_MASK << pcie_port);
+	val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
+	__raw_writel(val, KS2_DEVCFG);
+}
+
 int arch_cpu_init(void)
 {
 	chip_configuration_unlock();

@@ -77,8 +105,13 @@ int arch_cpu_init(void)
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+
+	/* Initialize the PCIe-0 to work as Root Complex */
+	config_pcie_mode(0, ROOTCOMPLEX);
 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+	/* Initialize the PCIe-1 to work as Root Complex */
+	config_pcie_mode(1, ROOTCOMPLEX);
 #endif
 #ifdef CONFIG_SOC_K2L
 	osr_init();
arch/arm/include/asm/arch-keystone/hardware.h +1 -0
index be22bdb..16cbcee 100644
@@ -144,6 +144,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
 #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
 #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+#define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
 
 /* PSC */
 #define KS2_PSC_BASE			0x02350000
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH 1/1 keystone: set default pci mode to root complex

Quoted 74 lines · Murali Karicheri

pci ports are used as root complex in Linux. So set this as default in u-boot for keystone devices

Signed-off-by Murali Karicheri<[email protected]>
---
  arch/arm/cpu/armv7/keystone/init.c            |   33 +++++++++++++++++++++++++
  arch/arm/include/asm/arch-keystone/hardware.h |    1 +
  2 files changed, 34 insertions(+)
arch/arm/cpu/armv7/keystone/init.c +33 -0
index c2b9478..c96845c 100644
@@ -15,6 +15,16 @@
  #include<asm/arch/hardware.h>
  #include<asm/arch/psc_defs.h>
 
+#define MAX_PCI_PORTS		2
+enum pci_mode	{
+	ENDPOINT,
+	LEGACY_ENDPOINT,
+	ROOTCOMPLEX,
+};
+
+#define DEVCFG_MODE_MASK		(BIT(2) | BIT(1))
+#define DEVCFG_MODE_SHIFT		1
+
  void chip_configuration_unlock(void)
  {
  	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);

@@ -68,6 +78,24 @@ void osr_init(void)
  }
  #endif
 
+/* Function to set up PCIe mode */
+static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
+{
+	u32 val = __raw_readl(KS2_DEVCFG);
+
+	if (pcie_port>= MAX_PCI_PORTS)
+		return;
+
+	/**
+	 * each pci port has two bits for mode and it starts at
+	 * bit 1. So use port number to get the right bit position.
+	 */
+	pcie_port<<= 1;
+	val&= ~(DEVCFG_MODE_MASK<<  pcie_port);
+	val |= ((mode<<  DEVCFG_MODE_SHIFT)<<  pcie_port);
+	__raw_writel(val, KS2_DEVCFG);
+}
+
  int arch_cpu_init(void)
  {
  	chip_configuration_unlock();

@@ -77,8 +105,13 @@ int arch_cpu_init(void)
  	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
  	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
  	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+
+	/* Initialize the PCIe-0 to work as Root Complex */
+	config_pcie_mode(0, ROOTCOMPLEX);
  #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
  	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+	/* Initialize the PCIe-1 to work as Root Complex */
+	config_pcie_mode(1, ROOTCOMPLEX);
  #endif
  #ifdef CONFIG_SOC_K2L
  	osr_init();
arch/arm/include/asm/arch-keystone/hardware.h +0 -0
index be22bdb..16cbcee 100644

arch/arm/include/asm/arch-keystone/hardware.h typedef volatile unsigned int *dv_reg_p; · line 150

Quoted 7 lines
arch/arm/include/asm/arch-keystone/hardware.h +1 -0
@@ -144,6 +144,7 @@ typedef volatile unsigned int   *dv_reg_p;
  #define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
  #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
  #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+#define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
 
  /* PSC */
  #define KS2_PSC_BASE			0x02350000

Tom,

Please apply this when you get a chance if there are no comments.

Signature · 2 lines
Murali Karicheri
Linux Kernel, Texas Instruments
#2 lore raw
In reply to Murali Karicheri
Quoted 4 lines · Muralidharan

pci ports are used as root complex in Linux. So set this as default in u-boot for keystone devices

Signed-off-by Murali Karicheri <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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